[hmac] update wording from sanity to smoke
Signed-off-by: Cindy Chen <chencindy@google.com>
diff --git a/hw/ip/hmac/data/hmac_testplan.hjson b/hw/ip/hmac/data/hmac_testplan.hjson
index 46c3ebb..c667313 100644
--- a/hw/ip/hmac/data/hmac_testplan.hjson
+++ b/hw/ip/hmac/data/hmac_testplan.hjson
@@ -9,8 +9,8 @@
"hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson"]
entries: [
{
- name: sanity
- desc: '''Basic sanity test performs a few round of HMAC or SHA256-ONLY transactions with the
+ name: smoke
+ desc: '''HMAC smoke test performs a few round of HMAC or SHA256-ONLY transactions with the
prodecures below:
- Set configuration register to randomly enable SHA256, hmac, endian_swap, and digest_swap
- Set interrupt enable register to randomly enable fifo_full, hmac_done, and err_code
@@ -23,11 +23,11 @@
- Trigger HMAC hash_process
- After hmac_done interrupt, read and check digest data'''
milestone: V1
- tests: ["hmac_sanity"]
+ tests: ["hmac_smoke"]
}
{
name: long_msg
- desc: '''Long_msg test is based on the sanity test. The message length is between 0 and
+ desc: '''Long_msg test is based on the smoke test. The message length is between 0 and
10,000 bytes.'''
milestone: V2
tests: ["hmac_long_msg"]
@@ -83,7 +83,7 @@
name: write_config_and_secret_key_during_msg_wr
desc: "Change config registers and secret keys during msg write, make sure access is blocked."
milestone: V3
- tests: ["hmac_sanity"]
+ tests: ["hmac_smoke"]
}
]
}
diff --git a/hw/ip/hmac/doc/checklist.md b/hw/ip/hmac/doc/checklist.md
index 7be0178..b7bb141 100644
--- a/hw/ip/hmac/doc/checklist.md
+++ b/hw/ip/hmac/doc/checklist.md
@@ -126,11 +126,11 @@
Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done |
Testbench | [CSR_CHECK_GEN_AUTOMATED][] | waived | Revisit later. Tool setup in progress.
Testbench | [TB_GEN_AUTOMATED][] | N/A |
-Tests | [SIM_SANITY_TEST_PASSING][] | Done |
+Tests | [SIM_SMOKE_TEST_PASSING][] | Done |
Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done |
Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A |
Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done |
-Regression | [SIM_SANITY_REGRESSION_SETUP][] | Done w/ waivers| Exception (implemented in local)
+Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done w/ waivers| Exception (implemented in local)
Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done w/ waivers| Exception (implemented in local)
Regression | [FPV_REGRESSION_SETUP][] | N/A |
Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done |
@@ -149,11 +149,11 @@
[SIM_RAL_MODEL_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#sim_ral_model_gen_automated" >}}
[CSR_CHECK_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#csr_check_gen_automated" >}}
[TB_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#tb_gen_automated" >}}
-[SIM_SANITY_TEST_PASSING]: {{<relref "/doc/project/checklist.md#sim_sanity_test_passing" >}}
+[SIM_SMOKE_TEST_PASSING]: {{<relref "/doc/project/checklist.md#sim_smoke_test_passing" >}}
[SIM_CSR_MEM_TEST_SUITE_PASSING]: {{<relref "/doc/project/checklist.md#sim_csr_mem_test_suite_passing" >}}
[FPV_MAIN_ASSERTIONS_PROVEN]: {{<relref "/doc/project/checklist.md#fpv_main_assertions_proven" >}}
[SIM_ALT_TOOL_SETUP]: {{<relref "/doc/project/checklist.md#sim_alt_tool_setup" >}}
-[SIM_SANITY_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_sanity_regression_setup" >}}
+[SIM_SMOKE_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_smoke_regression_setup" >}}
[SIM_NIGHTLY_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_setup" >}}
[FPV_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#fpv_regression_setup" >}}
[SIM_COVERAGE_MODEL_ADDED]: {{<relref "/doc/project/checklist.md#sim_coverage_model_added" >}}
diff --git a/hw/ip/hmac/doc/dv_plan/index.md b/hw/ip/hmac/doc/dv_plan/index.md
index 7d0af2d..12039c3 100644
--- a/hw/ip/hmac/doc/dv_plan/index.md
+++ b/hw/ip/hmac/doc/dv_plan/index.md
@@ -137,9 +137,9 @@
[regression tool]({{< relref "hw/dv/tools/README.md" >}}) for building and running our tests and regressions.
Please take a look at the link for detailed information on the usage, capabilities, features and known
issues.
-Here's how to run a basic sanity test:
+Here's how to run a smoke test:
```console
-$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/hmac/dv/hmac_sim_cfg.hjson -i hmac_sanity
+$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/hmac/dv/hmac_sim_cfg.hjson -i hmac_smoke
```
## Testplan
diff --git a/hw/ip/hmac/dv/env/hmac_env.core b/hw/ip/hmac/dv/env/hmac_env.core
index 669ea03..7e3c32c 100644
--- a/hw/ip/hmac/dv/env/hmac_env.core
+++ b/hw/ip/hmac/dv/env/hmac_env.core
@@ -20,7 +20,7 @@
- seq_lib/hmac_vseq_list.sv: {is_include_file: true}
- seq_lib/hmac_base_vseq.sv: {is_include_file: true}
- seq_lib/hmac_common_vseq.sv: {is_include_file: true}
- - seq_lib/hmac_sanity_vseq.sv: {is_include_file: true}
+ - seq_lib/hmac_smoke_vseq.sv: {is_include_file: true}
- seq_lib/hmac_back_pressure_vseq.sv: {is_include_file: true}
- seq_lib/hmac_datapath_stress_vseq.sv: {is_include_file: true}
- seq_lib/hmac_test_vectors_hmac_vseq.sv: {is_include_file: true}
diff --git a/hw/ip/hmac/dv/env/hmac_scoreboard.sv b/hw/ip/hmac/dv/env/hmac_scoreboard.sv
index 822a141..0a96fd9 100644
--- a/hw/ip/hmac/dv/env/hmac_scoreboard.sv
+++ b/hw/ip/hmac/dv/env/hmac_scoreboard.sv
@@ -168,7 +168,7 @@
// but for coverage purpose, we will reset intr_test after collected the coverage
intr_test = 0;
if (item.d_data[HmacDone] == 1) begin
- // here sanity check DUT should only trigger hmac_done when sha is enabled, and
+ // here check DUT should only trigger hmac_done when sha is enabled, and
// previously triggered hash_process.
// future throughput test should check the accurate cycles
if (sha_en && hmac_process) begin
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_back_pressure_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_back_pressure_vseq.sv
index 5cd3fd5..f089107 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_back_pressure_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_back_pressure_vseq.sv
@@ -5,7 +5,7 @@
// This sequence generates back-pressure seq
// The sequence disabled all the rand delay and optional reg checkings
-class hmac_back_pressure_vseq extends hmac_sanity_vseq;
+class hmac_back_pressure_vseq extends hmac_smoke_vseq;
`uvm_object_utils(hmac_back_pressure_vseq)
`uvm_object_new
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_datapath_stress_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_datapath_stress_vseq.sv
index a3399a0..1c84e24 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_datapath_stress_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_datapath_stress_vseq.sv
@@ -6,7 +6,7 @@
// thus will have 2 hashes (one for key, one for msg) with the shortest message required
// TODO: potentially use DV to check throughput here
-class hmac_datapath_stress_vseq extends hmac_sanity_vseq;
+class hmac_datapath_stress_vseq extends hmac_smoke_vseq;
`uvm_object_utils(hmac_datapath_stress_vseq)
`uvm_object_new
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_long_msg_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_long_msg_vseq.sv
index 11f0e1e..01b3cd4 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_long_msg_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_long_msg_vseq.sv
@@ -5,7 +5,7 @@
// This sequence generates a mix of short and long msgs
// Long msg has a larger size than HMAC input FIFO
-class hmac_long_msg_vseq extends hmac_sanity_vseq;
+class hmac_long_msg_vseq extends hmac_smoke_vseq;
`uvm_object_utils(hmac_long_msg_vseq)
`uvm_object_new
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_sanity_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_smoke_vseq.sv
similarity index 97%
rename from hw/ip/hmac/dv/env/seq_lib/hmac_sanity_vseq.sv
rename to hw/ip/hmac/dv/env/seq_lib/hmac_smoke_vseq.sv
index a7d0b06..9af6942 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_sanity_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_smoke_vseq.sv
@@ -2,8 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-class hmac_sanity_vseq extends hmac_base_vseq;
- `uvm_object_utils(hmac_sanity_vseq)
+class hmac_smoke_vseq extends hmac_base_vseq;
+ `uvm_object_utils(hmac_smoke_vseq)
`uvm_object_new
constraint num_trans_c {
@@ -136,4 +136,4 @@
end
endtask : body
-endclass : hmac_sanity_vseq
+endclass : hmac_smoke_vseq
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_stress_all_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_stress_all_vseq.sv
index da7fbbc..35444fc 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_stress_all_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_stress_all_vseq.sv
@@ -10,7 +10,7 @@
`uvm_object_new
task body();
- string seq_names[] = {"hmac_sanity_vseq",
+ string seq_names[] = {"hmac_smoke_vseq",
"hmac_back_pressure_vseq",
"hmac_burst_wr_vseq",
"hmac_common_vseq", // for intr_test
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv
index 24ca588..b654726 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv
@@ -3,7 +3,7 @@
// SPDX-License-Identifier: Apache-2.0
`include "hmac_base_vseq.sv"
-`include "hmac_sanity_vseq.sv"
+`include "hmac_smoke_vseq.sv"
`include "hmac_long_msg_vseq.sv"
`include "hmac_test_vectors_sha_vseq.sv"
`include "hmac_test_vectors_hmac_vseq.sv"
diff --git a/hw/ip/hmac/dv/hmac_sim_cfg.hjson b/hw/ip/hmac/dv/hmac_sim_cfg.hjson
index 750b6b3..b29d9fe 100644
--- a/hw/ip/hmac/dv/hmac_sim_cfg.hjson
+++ b/hw/ip/hmac/dv/hmac_sim_cfg.hjson
@@ -54,8 +54,8 @@
// List of test specifications.
tests: [
{
- name: hmac_sanity
- uvm_test_seq: hmac_sanity_vseq
+ name: hmac_smoke
+ uvm_test_seq: hmac_smoke_vseq
}
{
@@ -114,8 +114,8 @@
// List of regressions.
regressions: [
{
- name: sanity
- tests: ["hmac_sanity", "hmac_test_sha_vectors"]
+ name: smoke
+ tests: ["hmac_smoke", "hmac_test_sha_vectors"]
}
]
}
