[doc,checklist] Make FPGA_TIMING item more descriptive
We don't really have a definition of "Fmax-10%" and, in practice,
everything passes this by being synthesized at chip-level as part of
CI checks. Amend the text to reflect this.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/doc/project/checklist.md b/doc/project/checklist.md
index cfc7859..a32988d 100644
--- a/doc/project/checklist.md
+++ b/doc/project/checklist.md
@@ -112,7 +112,7 @@
### FPGA_TIMING
-FPGA synthesis timing meet (Fmax-10%) target or better
+Block is synthesized as part of continuous integration checks and meets timing there.
### CDC_SYNCMACRO
