commit 3d16099836c108549b0385f622ded0c9cc3642c7
author Michael Schaffner <msf@opentitan.org> Tue Mar 31 18:37:53 2020 -0700
committer Michael Schaffner <msf@google.com> Wed Apr 01 10:24:50 2020 -0700
tree faca2cb34ace0257d0405fdcaef68530bcec632c
parent 812eb331bd91a6b418bd62e364397b219c8e7b22

[dvsim] Synthesis target integration

This adds the following features to dvsim:
- SynCfg for synthesis targets
- Dashboard for single synthesis runs (summaries from master configs are
not yet supported)
- Configuration and run / parsing scripts for wire-load-model-based
synthesis flow in DC

Signed-off-by: Michael Schaffner <msf@opentitan.org>

util/dvsim/dvsim.py

diff --git a/util/dvsim/dvsim.py b/util/dvsim/dvsim.py
index d61d304..b832fc8 100755
--- a/util/dvsim/dvsim.py
+++ b/util/dvsim/dvsim.py
@@ -22,6 +22,7 @@
 import Deploy
 import LintCfg
 import SimCfg
+import SynCfg
 import utils
 
 # TODO: add dvsim_cfg.hjson to retrieve this info
@@ -128,7 +129,7 @@
     parser.add_argument("-t",
                         "--tool",
                         default="",
-                        metavar="vcs|xcelium|ascentlint|...",
+                        metavar="vcs|xcelium|ascentlint|dc|...",
                         help="Override the tool that is set in hjson file")
 
     parser.add_argument(
@@ -476,6 +477,8 @@
     # and other ASIC flow targets.
     if args.tool == 'ascentlint':
         cfg = LintCfg.LintCfg(args.cfg, proj_root, args)
+    elif args.tool == 'dc':
+        cfg = SynCfg.SynCfg(args.cfg, proj_root, args)
     else:
         cfg = SimCfg.SimCfg(args.cfg, proj_root, args)