| commit | 3c5b86f1ad4077caa080b7cc19a8e1aecd23edee | [log] [tgz] |
|---|---|---|
| author | Greg Chadwick <gac@lowrisc.org> | Wed Feb 05 14:26:13 2020 +0000 |
| committer | Pirmin Vogel <vogelpi@lowrisc.org> | Thu Feb 06 10:13:38 2020 +0100 |
| tree | aab499701f6a4560bfe198be4a177617defb3eb9 | |
| parent | a5a6122923dab56d185bec9f7a81941708450295 [diff] |
Update lowrisc_ibex to lowRISC/ibex@3f0b730 Update code from upstream repository https://github.com/lowRISC/ibex.git to revision 3f0b730d57ee415abd2526fc283d3d16c6632d6b * [doc] Riviera-PRO instructions for Simple System (Greg Chadwick) * [rtl] Decouple `mip` and `mie` CSRs (Pirmin Vogel) * Extend riscv-compliance description (Tobias Wölfel) * Fix incdirs of src_files.yml (dalance) * [verilator] Fix ELF loading (Luís Marques) * Fix FPGA part number for Arty A7-100T (Stephano Cetola) * Ignore all interrupts in NMI mode, clarify interrupt documentation (Pirmin Vogel) * [rtl] Comment and naming tweaks (Greg Chadwick) * [rtl] Timing fix for pc_mux_o in ibex_controller (Greg Chadwick) * [rtl] Add multdiv_sel signal to decode (Greg Chadwick) * [rtl] Replicate instruction flops to reduce fanout (Greg Chadwick) * [RTL] Added seperate ALU for branch target (Greg Chadwick) * [dv] Fix a missed Riviera compile warning (lowRISC/ibex#576) (udinator) * [DV] Add support for Riviera (Daniel Mlynek) * Work around Riviera 2019.10 issue (Daniel Mlynek) * [DV] Use const instead of parameter (Daniel Mlynek) * [examples] Add Dual-Port Memory to Simple System (ganoam) * Update google_riscv-dv to google/riscv-dv@f7e35d7 (lowRISC/ibex#573) (udinator) * Riviera compile warnings (lowRISC/ibex#572) (udinator) * Verilator: Remove unused waivers (Philipp Wagner) * Include assert macros when they are used (Daniel Mlynek) * Simple System: Correctly tie-off unused signals (Daniel Mlynek) * Specify boot address in decimal (Daniel Mlynek) * FPGA example: add support for the Arty A7-35 (Stefan Tauner) * sw-led: do not hardcode CC in makefile (Stefan Tauner) * [DV] Test debug requests during interrupt handler execution (lowRISC/ibex#565) (udinator) * [DV] Test nested interrupts (lowRISC/ibex#560) (udinator) * Update google_riscv-dv to google/riscv-dv@a655f34 (lowRISC/ibex#564) (udinator) * Improve wording in README of simple system (Philipp Wagner) * [syn] Feed ABC faster clock for better results (Greg Chadwick) * [rtl] Fix Typo in FPGA Register File (ganoam) * [DV] Add test to assert interrupts during debug execution (lowRISC/ibex#524) (udinator) Signed-off-by: Greg Chadwick <gac@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can either access it online or build it locally by following the steps below.
$ sudo apt install curl python3 python3-pip $ pip3 install --user -r python-requirements.txt
$ ./util/build_docs.py --preview
This compiles the documentation into ./build/docs and starts a local server, which allows you to access the documentation at http://127.0.0.1:1313.
Have a look at CONTRIBUTING for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).
