[reggen] Revise devmode behavior
Register modules aren't aware of LifeCycle anymore. It determines the
error response based on `devmode_i` only.
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
index 100fc05..64b6ef1 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
@@ -5,9 +5,7 @@
// Register Top module auto-generated by `reggen`
-module flash_ctrl_reg_top #(
- parameter logic LifeCycle = 1'b0 // If 0b, assume devmode 1b always
-) (
+module flash_ctrl_reg_top (
input clk_i,
input rst_ni,
@@ -117,30 +115,7 @@
);
assign reg_rdata = reg_rdata_next ;
-
- // Ignore devmode_i if this register module isn't used in LifeCycle managed IP
- // And mandate to return error for address miss
-
- logic devmode ;
- assign devmode = LifeCycle ? devmode_i : 1'b1;
-
- assign reg_error = (devmode & addrmiss) | wr_err ;
-
- // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
- // TODO(eunchan): Make concrete scenario
- // 1. Write: No response, so that it can guarantee a request completes a clock after we
- // It means, bus_reg_ready doesn't have to be lowered.
- // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
- // _____ _____
- // a_valid _____/ \_______/ \______
- // ___________ _____
- // a_ready \_______/ \______ <- ERR though no logic malfunction
- // _____________
- // d_valid ___________/ \______
- // _____
- // d_ready ___________________/ \______
- //
- // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/gpio/rtl/gpio_reg_top.sv b/hw/ip/gpio/rtl/gpio_reg_top.sv
index 89b02b0..ac00eff 100644
--- a/hw/ip/gpio/rtl/gpio_reg_top.sv
+++ b/hw/ip/gpio/rtl/gpio_reg_top.sv
@@ -5,9 +5,7 @@
// Register Top module auto-generated by `reggen`
-module gpio_reg_top #(
- parameter logic LifeCycle = 1'b0 // If 0b, assume devmode 1b always
-) (
+module gpio_reg_top (
input clk_i,
input rst_ni,
@@ -67,30 +65,7 @@
);
assign reg_rdata = reg_rdata_next ;
-
- // Ignore devmode_i if this register module isn't used in LifeCycle managed IP
- // And mandate to return error for address miss
-
- logic devmode ;
- assign devmode = LifeCycle ? devmode_i : 1'b1;
-
- assign reg_error = (devmode & addrmiss) | wr_err ;
-
- // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
- // TODO(eunchan): Make concrete scenario
- // 1. Write: No response, so that it can guarantee a request completes a clock after we
- // It means, bus_reg_ready doesn't have to be lowered.
- // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
- // _____ _____
- // a_valid _____/ \_______/ \______
- // ___________ _____
- // a_ready \_______/ \______ <- ERR though no logic malfunction
- // _____________
- // d_valid ___________/ \______
- // _____
- // d_ready ___________________/ \______
- //
- // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/hmac/rtl/hmac_reg_top.sv b/hw/ip/hmac/rtl/hmac_reg_top.sv
index c490d46..71f7fdc 100644
--- a/hw/ip/hmac/rtl/hmac_reg_top.sv
+++ b/hw/ip/hmac/rtl/hmac_reg_top.sv
@@ -5,9 +5,7 @@
// Register Top module auto-generated by `reggen`
-module hmac_reg_top #(
- parameter logic LifeCycle = 1'b0 // If 0b, assume devmode 1b always
-) (
+module hmac_reg_top (
input clk_i,
input rst_ni,
@@ -113,30 +111,7 @@
);
assign reg_rdata = reg_rdata_next ;
-
- // Ignore devmode_i if this register module isn't used in LifeCycle managed IP
- // And mandate to return error for address miss
-
- logic devmode ;
- assign devmode = LifeCycle ? devmode_i : 1'b1;
-
- assign reg_error = (devmode & addrmiss) | wr_err ;
-
- // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
- // TODO(eunchan): Make concrete scenario
- // 1. Write: No response, so that it can guarantee a request completes a clock after we
- // It means, bus_reg_ready doesn't have to be lowered.
- // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
- // _____ _____
- // a_valid _____/ \_______/ \______
- // ___________ _____
- // a_ready \_______/ \______ <- ERR though no logic malfunction
- // _____________
- // d_valid ___________/ \______
- // _____
- // d_ready ___________________/ \______
- //
- // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv b/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
index 774739c..50ffe84 100644
--- a/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
+++ b/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
@@ -5,9 +5,7 @@
// Register Top module auto-generated by `reggen`
-module rv_plic_reg_top #(
- parameter logic LifeCycle = 1'b0 // If 0b, assume devmode 1b always
-) (
+module rv_plic_reg_top (
input clk_i,
input rst_ni,
@@ -67,30 +65,7 @@
);
assign reg_rdata = reg_rdata_next ;
-
- // Ignore devmode_i if this register module isn't used in LifeCycle managed IP
- // And mandate to return error for address miss
-
- logic devmode ;
- assign devmode = LifeCycle ? devmode_i : 1'b1;
-
- assign reg_error = (devmode & addrmiss) | wr_err ;
-
- // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
- // TODO(eunchan): Make concrete scenario
- // 1. Write: No response, so that it can guarantee a request completes a clock after we
- // It means, bus_reg_ready doesn't have to be lowered.
- // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
- // _____ _____
- // a_valid _____/ \_______/ \______
- // ___________ _____
- // a_ready \_______/ \______ <- ERR though no logic malfunction
- // _____________
- // d_valid ___________/ \______
- // _____
- // d_ready ___________________/ \______
- //
- // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv b/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv
index aeb2e88..0c4486c 100644
--- a/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv
+++ b/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv
@@ -5,9 +5,7 @@
// Register Top module auto-generated by `reggen`
-module rv_timer_reg_top #(
- parameter logic LifeCycle = 1'b0 // If 0b, assume devmode 1b always
-) (
+module rv_timer_reg_top (
input clk_i,
input rst_ni,
@@ -67,30 +65,7 @@
);
assign reg_rdata = reg_rdata_next ;
-
- // Ignore devmode_i if this register module isn't used in LifeCycle managed IP
- // And mandate to return error for address miss
-
- logic devmode ;
- assign devmode = LifeCycle ? devmode_i : 1'b1;
-
- assign reg_error = (devmode & addrmiss) | wr_err ;
-
- // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
- // TODO(eunchan): Make concrete scenario
- // 1. Write: No response, so that it can guarantee a request completes a clock after we
- // It means, bus_reg_ready doesn't have to be lowered.
- // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
- // _____ _____
- // a_valid _____/ \_______/ \______
- // ___________ _____
- // a_ready \_______/ \______ <- ERR though no logic malfunction
- // _____________
- // d_valid ___________/ \______
- // _____
- // d_ready ___________________/ \______
- //
- // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_top.sv b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
index 1fbd947..bd7028c 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_top.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
@@ -5,9 +5,7 @@
// Register Top module auto-generated by `reggen`
-module spi_device_reg_top #(
- parameter logic LifeCycle = 1'b0 // If 0b, assume devmode 1b always
-) (
+module spi_device_reg_top (
input clk_i,
input rst_ni,
@@ -113,30 +111,7 @@
);
assign reg_rdata = reg_rdata_next ;
-
- // Ignore devmode_i if this register module isn't used in LifeCycle managed IP
- // And mandate to return error for address miss
-
- logic devmode ;
- assign devmode = LifeCycle ? devmode_i : 1'b1;
-
- assign reg_error = (devmode & addrmiss) | wr_err ;
-
- // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
- // TODO(eunchan): Make concrete scenario
- // 1. Write: No response, so that it can guarantee a request completes a clock after we
- // It means, bus_reg_ready doesn't have to be lowered.
- // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
- // _____ _____
- // a_valid _____/ \_______/ \______
- // ___________ _____
- // a_ready \_______/ \______ <- ERR though no logic malfunction
- // _____________
- // d_valid ___________/ \______
- // _____
- // d_ready ___________________/ \______
- //
- // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/uart/rtl/uart_reg_top.sv b/hw/ip/uart/rtl/uart_reg_top.sv
index 1a59d73..7bf6a39 100644
--- a/hw/ip/uart/rtl/uart_reg_top.sv
+++ b/hw/ip/uart/rtl/uart_reg_top.sv
@@ -5,9 +5,7 @@
// Register Top module auto-generated by `reggen`
-module uart_reg_top #(
- parameter logic LifeCycle = 1'b0 // If 0b, assume devmode 1b always
-) (
+module uart_reg_top (
input clk_i,
input rst_ni,
@@ -67,30 +65,7 @@
);
assign reg_rdata = reg_rdata_next ;
-
- // Ignore devmode_i if this register module isn't used in LifeCycle managed IP
- // And mandate to return error for address miss
-
- logic devmode ;
- assign devmode = LifeCycle ? devmode_i : 1'b1;
-
- assign reg_error = (devmode & addrmiss) | wr_err ;
-
- // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
- // TODO(eunchan): Make concrete scenario
- // 1. Write: No response, so that it can guarantee a request completes a clock after we
- // It means, bus_reg_ready doesn't have to be lowered.
- // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
- // _____ _____
- // a_valid _____/ \_______/ \______
- // ___________ _____
- // a_ready \_______/ \______ <- ERR though no logic malfunction
- // _____________
- // d_valid ___________/ \______
- // _____
- // d_ready ___________________/ \______
- //
- // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/usbuart/rtl/usbuart_reg_top.sv b/hw/ip/usbuart/rtl/usbuart_reg_top.sv
index ac36a1a..af43812 100644
--- a/hw/ip/usbuart/rtl/usbuart_reg_top.sv
+++ b/hw/ip/usbuart/rtl/usbuart_reg_top.sv
@@ -5,9 +5,7 @@
// Register Top module auto-generated by `reggen`
-module usbuart_reg_top #(
- parameter logic LifeCycle = 1'b0 // If 0b, assume devmode 1b always
-) (
+module usbuart_reg_top (
input clk_i,
input rst_ni,
@@ -67,30 +65,7 @@
);
assign reg_rdata = reg_rdata_next ;
-
- // Ignore devmode_i if this register module isn't used in LifeCycle managed IP
- // And mandate to return error for address miss
-
- logic devmode ;
- assign devmode = LifeCycle ? devmode_i : 1'b1;
-
- assign reg_error = (devmode & addrmiss) | wr_err ;
-
- // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
- // TODO(eunchan): Make concrete scenario
- // 1. Write: No response, so that it can guarantee a request completes a clock after we
- // It means, bus_reg_ready doesn't have to be lowered.
- // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
- // _____ _____
- // a_valid _____/ \_______/ \______
- // ___________ _____
- // a_ready \_______/ \______ <- ERR though no logic malfunction
- // _____________
- // d_valid ___________/ \______
- // _____
- // d_ready ___________________/ \______
- //
- // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/top_earlgrey/rtl/rv_plic_reg_top.sv b/hw/top_earlgrey/rtl/rv_plic_reg_top.sv
index c294504..6b24e6b 100644
--- a/hw/top_earlgrey/rtl/rv_plic_reg_top.sv
+++ b/hw/top_earlgrey/rtl/rv_plic_reg_top.sv
@@ -5,9 +5,7 @@
// Register Top module auto-generated by `reggen`
-module rv_plic_reg_top #(
- parameter logic LifeCycle = 1'b0 // If 0b, assume devmode 1b always
-) (
+module rv_plic_reg_top (
input clk_i,
input rst_ni,
@@ -67,30 +65,7 @@
);
assign reg_rdata = reg_rdata_next ;
-
- // Ignore devmode_i if this register module isn't used in LifeCycle managed IP
- // And mandate to return error for address miss
-
- logic devmode ;
- assign devmode = LifeCycle ? devmode_i : 1'b1;
-
- assign reg_error = (devmode & addrmiss) | wr_err ;
-
- // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
- // TODO(eunchan): Make concrete scenario
- // 1. Write: No response, so that it can guarantee a request completes a clock after we
- // It means, bus_reg_ready doesn't have to be lowered.
- // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
- // _____ _____
- // a_valid _____/ \_______/ \______
- // ___________ _____
- // a_ready \_______/ \______ <- ERR though no logic malfunction
- // _____________
- // d_valid ___________/ \______
- // _____
- // d_ready ___________________/ \______
- //
- // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/util/reggen/reg_top.tpl.sv b/util/reggen/reg_top.tpl.sv
index a0fa793..73f4982 100644
--- a/util/reggen/reg_top.tpl.sv
+++ b/util/reggen/reg_top.tpl.sv
@@ -11,9 +11,7 @@
max_regs_char = len("{}".format(num_regs-1))
%>
-module ${block.name}_reg_top #(
- parameter logic LifeCycle = 1'b0 // If 0b, assume devmode 1b always
-) (
+module ${block.name}_reg_top (
input clk_i,
input rst_ni,
@@ -134,30 +132,7 @@
);
assign reg_rdata = reg_rdata_next ;
-
- // Ignore devmode_i if this register module isn't used in LifeCycle managed IP
- // And mandate to return error for address miss
-
- logic devmode ;
- assign devmode = LifeCycle ? devmode_i : 1'b1;
-
- assign reg_error = (devmode & addrmiss) | wr_err ;
-
- // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
- // TODO(eunchan): Make concrete scenario
- // 1. Write: No response, so that it can guarantee a request completes a clock after we
- // It means, bus_reg_ready doesn't have to be lowered.
- // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
- // _____ _____
- // a_valid _____/ \_______/ \______
- // ___________ _____
- // a_ready \_______/ \______ <- ERR though no logic malfunction
- // _____________
- // d_valid ___________/ \______
- // _____
- // d_ready ___________________/ \______
- //
- // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
