[spi_device] Instantiate Upload module
Now, spi_device has spid_upload submodule in the design. The upload
module checks incoming SPI transaction and upload to the CmdFifo,
AddrFifo, and PayloadBuffer based on the given command information.
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/hw/ip/prim/lint/prim_fifo.waiver b/hw/ip/prim/lint/prim_fifo.waiver
index 6c5dc98..bf1bb22 100644
--- a/hw/ip/prim/lint/prim_fifo.waiver
+++ b/hw/ip/prim/lint/prim_fifo.waiver
@@ -24,3 +24,8 @@
waive -rules EXPLICIT_BITLEN -location {prim_fifo_*sync.sv} -regexp {Bit length not specified for constant '1'} \
-comment "index is protected by control logic"
+
+## prim_fifo_async_sram_adapter
+waive -rules ARITH_CONTEXT -location {prim_fifo_async_sram_adapter.sv} \
+ -regexp {(r|w)_wptr_v.*_rptr_v} \
+ -comment "The pointer value width is determined. Remove the casting for readability"
diff --git a/hw/ip/prim/rtl/prim_fifo_async_sram_adapter.sv b/hw/ip/prim/rtl/prim_fifo_async_sram_adapter.sv
index 4ba6262..4771ffd 100644
--- a/hw/ip/prim/rtl/prim_fifo_async_sram_adapter.sv
+++ b/hw/ip/prim/rtl/prim_fifo_async_sram_adapter.sv
@@ -212,7 +212,8 @@
// End: SRAM Read pointer
// Full/ Empty
- localparam logic [PtrW-1:0] XorMask = PtrW'(1) << (PtrW-1);
+ // Lint complains PtrW'(1) << (PtrW-1). So changed as below
+ localparam logic [PtrW-1:0] XorMask = {1'b 1, {PtrW-1{1'b0}}};
assign w_full = (w_wptr_q == (w_rptr ^ XorMask));
assign r_full = (r_wptr == (r_rptr_q ^ XorMask));
assign r_empty = (r_wptr == r_rptr_q);
@@ -231,10 +232,10 @@
assign w_sram_addr_o = SramBaseAddr + SramAw'(w_wptr_v);
assign w_sram_wdata_o = SramDw'(wdata_i);
- assign w_sram_wmask_o = SramDw'(2**Width-1);
+ assign w_sram_wmask_o = SramDw'({Width{1'b1}});
- logic w_unused_sram;
- assign w_unused_sram = ^{w_sram_rvalid_i, w_sram_rdata_i, w_sram_rerror_i};
+ logic unused_w_sram;
+ assign unused_w_sram = ^{w_sram_rvalid_i, w_sram_rdata_i, w_sram_rerror_i};
// SRAM Read Request
// Request Scenario (!r_empty):
@@ -280,6 +281,11 @@
logic unused_rsram;
assign unused_rsram = ^{r_sram_rerror_i};
+ if (Width < SramDw) begin : g_unused_rdata
+ logic unused_rdata;
+ assign unused_rdata = ^r_sram_rdata_i[SramDw-1:Width];
+ end : g_unused_rdata
+
// read clock domain rdata storage
logic store;
diff --git a/hw/ip/spi_device/data/spi_device.hjson b/hw/ip/spi_device/data/spi_device.hjson
index 5cedd93..a35f388 100644
--- a/hw/ip/spi_device/data/spi_device.hjson
+++ b/hw/ip/spi_device/data/spi_device.hjson
@@ -461,6 +461,63 @@
} // f: threshold
]
} // R: READ_THRESHOLD
+ { name: "UPLOAD_STATUS"
+ desc: '''Upload module status register.
+ '''
+ swaccess: "ro"
+ hwaccess: "hwo"
+ fields: [
+ { bits: "4:0"
+ name: "cmdfifo_depth"
+ desc: "Command FIFO Entry"
+ } // f: cmdfifo_depth
+ { bits: "7"
+ name: "cmdfifo_notempty"
+ desc: "Upload Command FIFO Not Empty"
+ } // f: cmdfifo_notempty
+ { bits: "12:8"
+ name: "addrfifo_depth"
+ desc: "Address FIFO Entry"
+ } // f: addrfifo_depth
+ { bits: "15"
+ name: "addrfifo_notempty"
+ desc: "Upload Address FIFO Not Empty"
+ } // f: addrfifo_notempty
+ { bits: "24:16"
+ name: "payload_depth"
+ desc: '''Payload buffer depth
+ '''
+ } // f: payload_depth
+ ]
+ } // R: UPLOAD_STATUS
+ { name: "UPLOAD_CMDFIFO"
+ desc: '''Command Fifo Read Port.
+ '''
+ swaccess: "ro"
+ hwaccess: "hrw"
+ hwre: "true"
+ hwext: "true"
+ fields: [
+ { bits: "7:0"
+ name: "data"
+ desc: "read data"
+ }
+ ]
+ } // R: UPLOAD_CMDFIFO
+ { name: "UPLOAD_ADDRFIFO"
+ desc: '''Address Fifo Read Port.
+ '''
+ swaccess: "ro"
+ hwaccess: "hrw"
+ hwre: "true"
+ hwext: "true"
+ fields: [
+ { bits: "31:0"
+ name: "data"
+ desc: "read data"
+ }
+ ]
+ } // R: UPLOAD_ADDRFIFO
{ multireg: {
cname: "SPI_DEVICE"
name: "CMD_FILTER"
@@ -592,7 +649,8 @@
defines the command address field size.
The logic assumes the following SPI input stream as payload,
- which max size is 256B. If the command exceeds the maximum payload size 256B, the logic wraps the payload and overwrites.
+ which max size is 256B. If the command exceeds the maximum
+ payload size 256B, the logic wraps the payload and overwrites.
'''
} // f: upload
{ bits: "25"
diff --git a/hw/ip/spi_device/lint/spi_device.waiver b/hw/ip/spi_device/lint/spi_device.waiver
index 12d9abd..a006dd0 100644
--- a/hw/ip/spi_device/lint/spi_device.waiver
+++ b/hw/ip/spi_device/lint/spi_device.waiver
@@ -64,6 +64,12 @@
waive -rules TWO_STATE_TYPE -location {spi_device.sv} -regexp {'fwm_fifo_e' is of} \
-comment "Intended declaration"
+waive -rules TWO_STATE_TYPE -location {spi_device.sv} \
+ -regexp {'sys_sram_e' is of two state type} \
+ -comment "Enum int unsigned is used as a index. OK to be two state"
+waive -rules TWO_STATE_TYPE -location {spid_upload.sv} \
+ -regexp {'sramintf_e' is of two state type} \
+ -comment "Enum int unsigned is used as a index. OK to be two state"
waive -rules ONE_BIT_MEM_WIDTH -location {spi_device.sv spi_fwmode.sv} -regexp {Memory 'fwm_sram_.*' has word} \
-comment "Intended implementation to make it consistent with other signals"
@@ -180,3 +186,17 @@
waive -rules {TERMINAL_STATE} -location {spid_readbuffer.sv} \
-regexp {'StActive' is detected.} \
-comment "StActive is final state waiting CSb de-assertion"
+waive -rules {TERMINAL_STATE} -location {spid_upload.sv} \
+ -regexp {'StPayload' is detected.} \
+ -comment "StPayload is the final state waiting CSb"
+
+## PKG
+
+waive -rules {INPUT_NOT_READ} -location {spi_device_pkg.sv} \
+ -regexp {'ci\..*' is not read} \
+ -comment "Only portion of the cmd info struct is used"
+
+## PARAM_ENUM
+waive -rules {PARAM_ENUM_VAL} -location {spi_device.sv} \
+ -regexp {Parameter 'N' is .* 'SysSramEnd'} \
+ -comment "The enum is used as a constant in the design."
diff --git a/hw/ip/spi_device/rtl/spi_device.sv b/hw/ip/spi_device/rtl/spi_device.sv
index 25bd61e..4e7d679 100644
--- a/hw/ip/spi_device/rtl/spi_device.sv
+++ b/hw/ip/spi_device/rtl/spi_device.sv
@@ -86,6 +86,7 @@
logic mem_a_write;
logic [SramAw-1:0] mem_a_addr;
logic [SramDw-1:0] mem_a_wdata;
+ logic [SramDw-1:0] mem_a_wmask;
logic mem_a_rvalid;
logic [SramDw-1:0] mem_a_rdata;
logic [1:0] mem_a_rerror;
@@ -110,6 +111,38 @@
logic [3:0] internal_sd, internal_sd_en;
logic [3:0] passthrough_sd, passthrough_sd_en;
+ // Upload related interfaces (SRAM, FIFOs)
+ // Initially, SysSramEnd was the end of the enum variable. But lint tool
+ // raises errors the value being used in the parameter. So changed to
+ // localparam
+ typedef enum int unsigned {
+ SysSramFw = 0,
+ SysSramCmdFifo = 1,
+ SysSramAddrFifo = 2,
+ SysSramEnd = 3
+ } sys_sram_e;
+
+ sram_l2m_t sys_sram_l2m [SysSramEnd]; // FW, CMDFIFO, ADDRFIFO
+ sram_m2l_t sys_sram_m2l [SysSramEnd];
+
+ logic cmdfifo_rvalid, cmdfifo_rready;
+ logic [7:0] cmdfifo_rdata;
+ logic cmdfifo_notempty;
+
+ logic addrfifo_rvalid, addrfifo_rready;
+ logic [31:0] addrfifo_rdata;
+ logic addrfifo_notempty;
+
+ localparam int unsigned CmdFifoPtrW = $clog2(SramCmdFifoDepth+1);
+ localparam int unsigned AddrFifoPtrW = $clog2(SramAddrFifoDepth+1);
+
+ localparam int unsigned PayloadByte = SramPayloadDepth * (SramDw/$bits(spi_byte_t));
+ localparam int unsigned PayloadDepthW = $clog2(PayloadByte+1);
+
+ logic [CmdFifoPtrW-1:0] cmdfifo_depth;
+ logic [AddrFifoPtrW-1:0] addrfifo_depth;
+ logic [PayloadDepthW-1:0] payload_depth;
+
/////////////////////
// Control signals //
/////////////////////
@@ -701,7 +734,17 @@
p2s_data = sub_p2s_data[IoModeJedec];
sub_p2s_sent[IoModeJedec] = p2s_sent;
end
- // DpUpload:
+
+ DpUpload: begin
+ io_mode = sub_iomode[IoModeUpload];
+
+ p2s_valid = sub_p2s_valid[IoModeUpload];
+ p2s_data = sub_p2s_data[IoModeUpload];
+ sub_p2s_sent[IoModeUpload] = p2s_sent;
+
+ mem_b_l2m = sub_sram_l2m[IoModeUpload];
+ sub_sram_m2l[IoModeUpload] = mem_b_m2l;
+ end
// DpUnknown:
default: begin
io_mode = sub_iomode[IoModeCmdParse];
@@ -968,8 +1011,6 @@
// Temporary:
logic unused_busy;
assign unused_busy = status_busy_broadcast;
- // TODO: replace to the output of upload module
- assign status_busy_set = 1'b 0;
// Tie unused
logic unused_sub_sram_status;
@@ -1009,6 +1050,103 @@
};
assign sub_sram_l2m[IoModeJedec] = '0;
+ // Begin: Upload ===================================================
+ spid_upload #(
+ .CmdFifoBaseAddr (SramCmdFifoIdx),
+ .CmdFifoDepth (SramCmdFifoDepth),
+ .AddrFifoBaseAddr (SramAddrFifoIdx),
+ .AddrFifoDepth (SramAddrFifoDepth),
+ .PayloadBaseAddr (SramPayloadIdx),
+ .PayloadDepth (SramPayloadDepth),
+
+ .SpiByte ($bits(spi_byte_t))
+ ) u_upload (
+ .clk_i (clk_spi_in_buf),
+ .rst_ni (rst_spi_n),
+
+ .sys_clk_i (clk_i),
+ .sys_rst_ni (rst_ni),
+
+ .sys_csb_deasserted_pulse_i (csb_deasserted_busclk),
+
+ .sel_dp_i (cmd_dp_sel),
+
+ .sck_sram_o (sub_sram_l2m[IoModeUpload]),
+ .sck_sram_i (sub_sram_m2l[IoModeUpload]),
+
+ .sys_cmdfifo_sram_o (sys_sram_l2m[SysSramCmdFifo]),
+ .sys_cmdfifo_sram_i (sys_sram_m2l[SysSramCmdFifo]),
+
+ .sys_addrfifo_sram_o (sys_sram_l2m[SysSramAddrFifo]),
+ .sys_addrfifo_sram_i (sys_sram_m2l[SysSramAddrFifo]),
+
+ // SYS clock FIFO interface
+ .sys_cmdfifo_rvalid_o (cmdfifo_rvalid),
+ .sys_cmdfifo_rready_i (cmdfifo_rready),
+ .sys_cmdfifo_rdata_o (cmdfifo_rdata),
+
+ .sys_addrfifo_rvalid_o (addrfifo_rvalid),
+ .sys_addrfifo_rready_i (addrfifo_rready),
+ .sys_addrfifo_rdata_o (addrfifo_rdata),
+
+ // Interface: SPI to Parallel
+ .s2p_valid_i (s2p_data_valid),
+ .s2p_byte_i (s2p_data),
+ .s2p_bitcnt_i (s2p_bitcnt),
+
+ // Interface: Parallel to SPI
+ .p2s_valid_o (sub_p2s_valid[IoModeUpload]),
+ .p2s_data_o (sub_p2s_data [IoModeUpload]),
+ .p2s_sent_i (sub_p2s_sent [IoModeUpload]),
+
+ .spi_mode_i (spi_mode),
+
+ .cfg_addr_4b_en_i (cfg_addr_4b_en),
+
+ .cmd_info_i (cmd_info_broadcast),
+ .cmd_info_idx_i (cmd_info_idx_broadcast),
+
+ .io_mode_o (sub_iomode[IoModeUpload]),
+
+ .set_busy_o (status_busy_set),
+
+ .sys_cmdfifo_notempty_o (cmdfifo_notempty),
+ .sys_cmdfifo_full_o (), // not used
+ .sys_addrfifo_notempty_o (addrfifo_notempty),
+ .sys_addrfifo_full_o (), // not used
+
+ .sys_cmdfifo_depth_o (cmdfifo_depth),
+ .sys_addrfifo_depth_o (addrfifo_depth),
+ .sys_payload_depth_o (payload_depth)
+ );
+ // FIFO connect
+ assign cmdfifo_rready = reg2hw.upload_cmdfifo.re;
+ assign hw2reg.upload_cmdfifo.d = cmdfifo_rdata;
+ logic unused_cmdfifo_q;
+ assign unused_cmdfifo_q = ^{reg2hw.upload_cmdfifo.q, cmdfifo_rvalid};
+
+ assign addrfifo_rready = reg2hw.upload_addrfifo.re;
+ assign hw2reg.upload_addrfifo.d = addrfifo_rdata;
+ logic unused_addrfifo_q;
+ assign unused_addrfifo_q = ^{reg2hw.upload_addrfifo.q, addrfifo_rvalid};
+
+ // Connect UPLOAD_STATUS
+ assign hw2reg.upload_status.cmdfifo_depth.de = 1'b1;
+ assign hw2reg.upload_status.cmdfifo_depth.d = cmdfifo_depth;
+
+ assign hw2reg.upload_status.cmdfifo_notempty.de = 1'b1;
+ assign hw2reg.upload_status.cmdfifo_notempty.d = cmdfifo_notempty;
+
+ assign hw2reg.upload_status.addrfifo_depth.de = 1'b 1;
+ assign hw2reg.upload_status.addrfifo_depth.d = addrfifo_depth;
+
+ assign hw2reg.upload_status.addrfifo_notempty.de = 1'b 1;
+ assign hw2reg.upload_status.addrfifo_notempty.d = addrfifo_notempty;
+
+ assign hw2reg.upload_status.payload_depth.de = 1'b 1;
+ assign hw2reg.upload_status.payload_depth.d = payload_depth;
+
+ // End: Upload ---------------------------------------------------
/////////////////////
// SPI Passthrough //
/////////////////////
@@ -1051,6 +1189,8 @@
// Common modules //
////////////////////
+ logic [SramDw-1:0] sys_sram_l2m_fw_wmask;
+
tlul_adapter_sram #(
.SramAw (SramAw),
.SramDw (SramDw),
@@ -1063,17 +1203,77 @@
.tl_i (tl_sram_h2d),
.tl_o (tl_sram_d2h),
.en_ifetch_i (tlul_pkg::InstrDis),
- .req_o (mem_a_req),
+ .req_o (sys_sram_l2m[SysSramFw].req),
.req_type_o (),
- .gnt_i (mem_a_req), //Always grant when request
- .we_o (mem_a_write),
- .addr_o (mem_a_addr),
- .wdata_o (mem_a_wdata),
- .wmask_o (), // Not used
+ .gnt_i (1'b1), // TODO: Connect arbiter grant here
+ .we_o (sys_sram_l2m[SysSramFw].we),
+ .addr_o (sys_sram_l2m[SysSramFw].addr),
+ .wdata_o (sys_sram_l2m[SysSramFw].wdata),
+ .wmask_o (sys_sram_l2m_fw_wmask), // Not used
.intg_error_o(),
- .rdata_i (mem_a_rdata),
- .rvalid_i (mem_a_rvalid),
- .rerror_i (mem_a_rerror)
+ .rdata_i (sys_sram_m2l[SysSramFw].rdata),
+ .rvalid_i (sys_sram_m2l[SysSramFw].rvalid),
+ .rerror_i (sys_sram_m2l[SysSramFw].rerror)
+ );
+ assign sys_sram_l2m[SysSramFw].wstrb = sram_mask2strb(sys_sram_l2m_fw_wmask);
+
+ // Arbiter among Upload CmdFifo/AddrFifo & FW access
+ logic [SysSramEnd-1:0] sys_sram_req ;
+ logic [SysSramEnd-1:0] sys_sram_gnt ;
+ logic [SramAw-1:0] sys_sram_addr [SysSramEnd];
+ logic [SysSramEnd-1:0] sys_sram_write ;
+ logic [SramDw-1:0] sys_sram_wdata [SysSramEnd];
+ logic [SramDw-1:0] sys_sram_wmask [SysSramEnd];
+ logic [SysSramEnd-1:0] sys_sram_rvalid ;
+ logic [SramDw-1:0] sys_sram_rdata [SysSramEnd];
+ logic [1:0] sys_sram_rerror [SysSramEnd];
+
+ for (genvar i = 0 ; i < SysSramEnd ; i++) begin : g_sram_connect
+ assign sys_sram_req [i] = sys_sram_l2m[i].req;
+ assign sys_sram_addr [i] = sys_sram_l2m[i].addr;
+ assign sys_sram_write [i] = sys_sram_l2m[i].we;
+ assign sys_sram_wdata [i] = sys_sram_l2m[i].wdata;
+ assign sys_sram_wmask [i] = sram_strb2mask(sys_sram_l2m[i].wstrb);
+
+ assign sys_sram_m2l[i].rvalid = sys_sram_rvalid[i];
+ assign sys_sram_m2l[i].rdata = sys_sram_rdata[i];
+ assign sys_sram_m2l[i].rerror = sys_sram_rerror[i];
+
+ `ASSERT(ReqAlwaysAccepted_A, sys_sram_req[i] |-> sys_sram_gnt[i])
+ end : g_sram_connect
+
+ logic unused_sys_sram_gnt;
+ assign unused_sys_sram_gnt = ^sys_sram_gnt;
+
+ prim_sram_arbiter #(
+ .N (SysSramEnd),
+ .SramDw (SramDw),
+ .SramAw (SramAw),
+
+ .EnMask (1'b 1)
+ ) u_sys_sram_arbiter (
+ .clk_i,
+ .rst_ni,
+
+ .req_i (sys_sram_req),
+ .req_addr_i (sys_sram_addr),
+ .req_write_i (sys_sram_write),
+ .req_wdata_i (sys_sram_wdata),
+ .req_wmask_i (sys_sram_wmask),
+ .gnt_o (sys_sram_gnt),
+
+ .rsp_rvalid_o (sys_sram_rvalid),
+ .rsp_rdata_o (sys_sram_rdata),
+ .rsp_error_o (sys_sram_rerror),
+
+ .sram_req_o (mem_a_req),
+ .sram_addr_o (mem_a_addr),
+ .sram_write_o (mem_a_write),
+ .sram_wdata_o (mem_a_wdata),
+ .sram_wmask_o (mem_a_wmask),
+ .sram_rvalid_i (mem_a_rvalid),
+ .sram_rdata_i (mem_a_rdata),
+ .sram_rerror_i (mem_a_rerror)
);
// SRAM Wrapper
@@ -1107,7 +1307,7 @@
.a_write_i (mem_a_write),
.a_addr_i (mem_a_addr),
.a_wdata_i (mem_a_wdata),
- .a_wmask_i ({SramDw{1'b1}}),
+ .a_wmask_i (mem_a_wmask),
.a_rvalid_o (mem_a_rvalid),
.a_rdata_o (mem_a_rdata),
.a_rerror_o (mem_a_rerror),
diff --git a/hw/ip/spi_device/rtl/spi_device_pkg.sv b/hw/ip/spi_device/rtl/spi_device_pkg.sv
index 64d8690..53da87d 100644
--- a/hw/ip/spi_device/rtl/spi_device_pkg.sv
+++ b/hw/ip/spi_device/rtl/spi_device_pkg.sv
@@ -230,7 +230,8 @@
IoModeReadCmd = 2,
IoModeStatus = 3,
IoModeJedec = 4,
- IoModeEnd = 5 // Indicate of Length
+ IoModeUpload = 5,
+ IoModeEnd = 6 // Indicate of Length
} sub_io_mode_e;
// SPI Line Mode (Mode0 <-> Mode3)
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv b/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
index 8615070..e90ce9c 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
@@ -195,6 +195,16 @@
} spi_device_reg2hw_read_threshold_reg_t;
typedef struct packed {
+ logic [7:0] q;
+ logic re;
+ } spi_device_reg2hw_upload_cmdfifo_reg_t;
+
+ typedef struct packed {
+ logic [31:0] q;
+ logic re;
+ } spi_device_reg2hw_upload_addrfifo_reg_t;
+
+ typedef struct packed {
logic q;
} spi_device_reg2hw_cmd_filter_mreg_t;
@@ -326,22 +336,55 @@
} status;
} spi_device_hw2reg_flash_status_reg_t;
+ typedef struct packed {
+ struct packed {
+ logic [4:0] d;
+ logic de;
+ } cmdfifo_depth;
+ struct packed {
+ logic d;
+ logic de;
+ } cmdfifo_notempty;
+ struct packed {
+ logic [4:0] d;
+ logic de;
+ } addrfifo_depth;
+ struct packed {
+ logic d;
+ logic de;
+ } addrfifo_notempty;
+ struct packed {
+ logic [8:0] d;
+ logic de;
+ } payload_depth;
+ } spi_device_hw2reg_upload_status_reg_t;
+
+ typedef struct packed {
+ logic [7:0] d;
+ } spi_device_hw2reg_upload_cmdfifo_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } spi_device_hw2reg_upload_addrfifo_reg_t;
+
// Register -> HW type
typedef struct packed {
- spi_device_reg2hw_intr_state_reg_t intr_state; // [1104:1099]
- spi_device_reg2hw_intr_enable_reg_t intr_enable; // [1098:1093]
- spi_device_reg2hw_intr_test_reg_t intr_test; // [1092:1081]
- spi_device_reg2hw_alert_test_reg_t alert_test; // [1080:1079]
- spi_device_reg2hw_control_reg_t control; // [1078:1073]
- spi_device_reg2hw_cfg_reg_t cfg; // [1072:1060]
- spi_device_reg2hw_fifo_level_reg_t fifo_level; // [1059:1028]
- spi_device_reg2hw_rxf_ptr_reg_t rxf_ptr; // [1027:1012]
- spi_device_reg2hw_txf_ptr_reg_t txf_ptr; // [1011:996]
- spi_device_reg2hw_rxf_addr_reg_t rxf_addr; // [995:964]
- spi_device_reg2hw_txf_addr_reg_t txf_addr; // [963:932]
- spi_device_reg2hw_flash_status_reg_t flash_status; // [931:906]
- spi_device_reg2hw_jedec_id_reg_t jedec_id; // [905:882]
- spi_device_reg2hw_read_threshold_reg_t read_threshold; // [881:872]
+ spi_device_reg2hw_intr_state_reg_t intr_state; // [1146:1141]
+ spi_device_reg2hw_intr_enable_reg_t intr_enable; // [1140:1135]
+ spi_device_reg2hw_intr_test_reg_t intr_test; // [1134:1123]
+ spi_device_reg2hw_alert_test_reg_t alert_test; // [1122:1121]
+ spi_device_reg2hw_control_reg_t control; // [1120:1115]
+ spi_device_reg2hw_cfg_reg_t cfg; // [1114:1102]
+ spi_device_reg2hw_fifo_level_reg_t fifo_level; // [1101:1070]
+ spi_device_reg2hw_rxf_ptr_reg_t rxf_ptr; // [1069:1054]
+ spi_device_reg2hw_txf_ptr_reg_t txf_ptr; // [1053:1038]
+ spi_device_reg2hw_rxf_addr_reg_t rxf_addr; // [1037:1006]
+ spi_device_reg2hw_txf_addr_reg_t txf_addr; // [1005:974]
+ spi_device_reg2hw_flash_status_reg_t flash_status; // [973:948]
+ spi_device_reg2hw_jedec_id_reg_t jedec_id; // [947:924]
+ spi_device_reg2hw_read_threshold_reg_t read_threshold; // [923:914]
+ spi_device_reg2hw_upload_cmdfifo_reg_t upload_cmdfifo; // [913:905]
+ spi_device_reg2hw_upload_addrfifo_reg_t upload_addrfifo; // [904:872]
spi_device_reg2hw_cmd_filter_mreg_t [255:0] cmd_filter; // [871:616]
spi_device_reg2hw_addr_swap_mask_reg_t addr_swap_mask; // [615:584]
spi_device_reg2hw_addr_swap_data_reg_t addr_swap_data; // [583:552]
@@ -350,13 +393,16 @@
// HW -> register type
typedef struct packed {
- spi_device_hw2reg_intr_state_reg_t intr_state; // [123:112]
- spi_device_hw2reg_async_fifo_level_reg_t async_fifo_level; // [111:96]
- spi_device_hw2reg_status_reg_t status; // [95:90]
- spi_device_hw2reg_rxf_ptr_reg_t rxf_ptr; // [89:73]
- spi_device_hw2reg_txf_ptr_reg_t txf_ptr; // [72:56]
- spi_device_hw2reg_last_read_addr_reg_t last_read_addr; // [55:24]
- spi_device_hw2reg_flash_status_reg_t flash_status; // [23:0]
+ spi_device_hw2reg_intr_state_reg_t intr_state; // [189:178]
+ spi_device_hw2reg_async_fifo_level_reg_t async_fifo_level; // [177:162]
+ spi_device_hw2reg_status_reg_t status; // [161:156]
+ spi_device_hw2reg_rxf_ptr_reg_t rxf_ptr; // [155:139]
+ spi_device_hw2reg_txf_ptr_reg_t txf_ptr; // [138:122]
+ spi_device_hw2reg_last_read_addr_reg_t last_read_addr; // [121:90]
+ spi_device_hw2reg_flash_status_reg_t flash_status; // [89:66]
+ spi_device_hw2reg_upload_status_reg_t upload_status; // [65:40]
+ spi_device_hw2reg_upload_cmdfifo_reg_t upload_cmdfifo; // [39:32]
+ spi_device_hw2reg_upload_addrfifo_reg_t upload_addrfifo; // [31:0]
} spi_device_hw2reg_t;
// Register offsets
@@ -377,40 +423,43 @@
parameter logic [BlockAw-1:0] SPI_DEVICE_FLASH_STATUS_OFFSET = 13'h 38;
parameter logic [BlockAw-1:0] SPI_DEVICE_JEDEC_ID_OFFSET = 13'h 3c;
parameter logic [BlockAw-1:0] SPI_DEVICE_READ_THRESHOLD_OFFSET = 13'h 40;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_0_OFFSET = 13'h 44;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_1_OFFSET = 13'h 48;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_2_OFFSET = 13'h 4c;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_3_OFFSET = 13'h 50;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_4_OFFSET = 13'h 54;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_5_OFFSET = 13'h 58;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_6_OFFSET = 13'h 5c;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_7_OFFSET = 13'h 60;
- parameter logic [BlockAw-1:0] SPI_DEVICE_ADDR_SWAP_MASK_OFFSET = 13'h 64;
- parameter logic [BlockAw-1:0] SPI_DEVICE_ADDR_SWAP_DATA_OFFSET = 13'h 68;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_0_OFFSET = 13'h 6c;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_1_OFFSET = 13'h 70;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_2_OFFSET = 13'h 74;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_3_OFFSET = 13'h 78;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_4_OFFSET = 13'h 7c;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_5_OFFSET = 13'h 80;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_6_OFFSET = 13'h 84;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_7_OFFSET = 13'h 88;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_8_OFFSET = 13'h 8c;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_9_OFFSET = 13'h 90;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_10_OFFSET = 13'h 94;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_11_OFFSET = 13'h 98;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_12_OFFSET = 13'h 9c;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_13_OFFSET = 13'h a0;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_14_OFFSET = 13'h a4;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_15_OFFSET = 13'h a8;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_16_OFFSET = 13'h ac;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_17_OFFSET = 13'h b0;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_18_OFFSET = 13'h b4;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_19_OFFSET = 13'h b8;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_20_OFFSET = 13'h bc;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_21_OFFSET = 13'h c0;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_22_OFFSET = 13'h c4;
- parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_23_OFFSET = 13'h c8;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_UPLOAD_STATUS_OFFSET = 13'h 44;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_UPLOAD_CMDFIFO_OFFSET = 13'h 48;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_UPLOAD_ADDRFIFO_OFFSET = 13'h 4c;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_0_OFFSET = 13'h 50;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_1_OFFSET = 13'h 54;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_2_OFFSET = 13'h 58;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_3_OFFSET = 13'h 5c;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_4_OFFSET = 13'h 60;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_5_OFFSET = 13'h 64;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_6_OFFSET = 13'h 68;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_FILTER_7_OFFSET = 13'h 6c;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_ADDR_SWAP_MASK_OFFSET = 13'h 70;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_ADDR_SWAP_DATA_OFFSET = 13'h 74;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_0_OFFSET = 13'h 78;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_1_OFFSET = 13'h 7c;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_2_OFFSET = 13'h 80;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_3_OFFSET = 13'h 84;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_4_OFFSET = 13'h 88;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_5_OFFSET = 13'h 8c;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_6_OFFSET = 13'h 90;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_7_OFFSET = 13'h 94;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_8_OFFSET = 13'h 98;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_9_OFFSET = 13'h 9c;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_10_OFFSET = 13'h a0;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_11_OFFSET = 13'h a4;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_12_OFFSET = 13'h a8;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_13_OFFSET = 13'h ac;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_14_OFFSET = 13'h b0;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_15_OFFSET = 13'h b4;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_16_OFFSET = 13'h b8;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_17_OFFSET = 13'h bc;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_18_OFFSET = 13'h c0;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_19_OFFSET = 13'h c4;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_20_OFFSET = 13'h c8;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_21_OFFSET = 13'h cc;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_22_OFFSET = 13'h d0;
+ parameter logic [BlockAw-1:0] SPI_DEVICE_CMD_INFO_23_OFFSET = 13'h d4;
// Reset values for hwext registers and their fields
parameter logic [5:0] SPI_DEVICE_INTR_TEST_RESVAL = 6'h 0;
@@ -430,6 +479,8 @@
parameter logic [0:0] SPI_DEVICE_STATUS_CSB_RESVAL = 1'h 1;
parameter logic [31:0] SPI_DEVICE_LAST_READ_ADDR_RESVAL = 32'h 0;
parameter logic [23:0] SPI_DEVICE_FLASH_STATUS_RESVAL = 24'h 0;
+ parameter logic [7:0] SPI_DEVICE_UPLOAD_CMDFIFO_RESVAL = 8'h 0;
+ parameter logic [31:0] SPI_DEVICE_UPLOAD_ADDRFIFO_RESVAL = 32'h 0;
// Window parameters
parameter logic [BlockAw-1:0] SPI_DEVICE_BUFFER_OFFSET = 13'h 1000;
@@ -454,6 +505,9 @@
SPI_DEVICE_FLASH_STATUS,
SPI_DEVICE_JEDEC_ID,
SPI_DEVICE_READ_THRESHOLD,
+ SPI_DEVICE_UPLOAD_STATUS,
+ SPI_DEVICE_UPLOAD_CMDFIFO,
+ SPI_DEVICE_UPLOAD_ADDRFIFO,
SPI_DEVICE_CMD_FILTER_0,
SPI_DEVICE_CMD_FILTER_1,
SPI_DEVICE_CMD_FILTER_2,
@@ -491,7 +545,7 @@
} spi_device_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] SPI_DEVICE_PERMIT [51] = '{
+ parameter logic [3:0] SPI_DEVICE_PERMIT [54] = '{
4'b 0001, // index[ 0] SPI_DEVICE_INTR_STATE
4'b 0001, // index[ 1] SPI_DEVICE_INTR_ENABLE
4'b 0001, // index[ 2] SPI_DEVICE_INTR_TEST
@@ -509,40 +563,43 @@
4'b 0111, // index[14] SPI_DEVICE_FLASH_STATUS
4'b 0111, // index[15] SPI_DEVICE_JEDEC_ID
4'b 0011, // index[16] SPI_DEVICE_READ_THRESHOLD
- 4'b 1111, // index[17] SPI_DEVICE_CMD_FILTER_0
- 4'b 1111, // index[18] SPI_DEVICE_CMD_FILTER_1
- 4'b 1111, // index[19] SPI_DEVICE_CMD_FILTER_2
- 4'b 1111, // index[20] SPI_DEVICE_CMD_FILTER_3
- 4'b 1111, // index[21] SPI_DEVICE_CMD_FILTER_4
- 4'b 1111, // index[22] SPI_DEVICE_CMD_FILTER_5
- 4'b 1111, // index[23] SPI_DEVICE_CMD_FILTER_6
- 4'b 1111, // index[24] SPI_DEVICE_CMD_FILTER_7
- 4'b 1111, // index[25] SPI_DEVICE_ADDR_SWAP_MASK
- 4'b 1111, // index[26] SPI_DEVICE_ADDR_SWAP_DATA
- 4'b 1111, // index[27] SPI_DEVICE_CMD_INFO_0
- 4'b 1111, // index[28] SPI_DEVICE_CMD_INFO_1
- 4'b 1111, // index[29] SPI_DEVICE_CMD_INFO_2
- 4'b 1111, // index[30] SPI_DEVICE_CMD_INFO_3
- 4'b 1111, // index[31] SPI_DEVICE_CMD_INFO_4
- 4'b 1111, // index[32] SPI_DEVICE_CMD_INFO_5
- 4'b 1111, // index[33] SPI_DEVICE_CMD_INFO_6
- 4'b 1111, // index[34] SPI_DEVICE_CMD_INFO_7
- 4'b 1111, // index[35] SPI_DEVICE_CMD_INFO_8
- 4'b 1111, // index[36] SPI_DEVICE_CMD_INFO_9
- 4'b 1111, // index[37] SPI_DEVICE_CMD_INFO_10
- 4'b 1111, // index[38] SPI_DEVICE_CMD_INFO_11
- 4'b 1111, // index[39] SPI_DEVICE_CMD_INFO_12
- 4'b 1111, // index[40] SPI_DEVICE_CMD_INFO_13
- 4'b 1111, // index[41] SPI_DEVICE_CMD_INFO_14
- 4'b 1111, // index[42] SPI_DEVICE_CMD_INFO_15
- 4'b 1111, // index[43] SPI_DEVICE_CMD_INFO_16
- 4'b 1111, // index[44] SPI_DEVICE_CMD_INFO_17
- 4'b 1111, // index[45] SPI_DEVICE_CMD_INFO_18
- 4'b 1111, // index[46] SPI_DEVICE_CMD_INFO_19
- 4'b 1111, // index[47] SPI_DEVICE_CMD_INFO_20
- 4'b 1111, // index[48] SPI_DEVICE_CMD_INFO_21
- 4'b 1111, // index[49] SPI_DEVICE_CMD_INFO_22
- 4'b 1111 // index[50] SPI_DEVICE_CMD_INFO_23
+ 4'b 1111, // index[17] SPI_DEVICE_UPLOAD_STATUS
+ 4'b 0001, // index[18] SPI_DEVICE_UPLOAD_CMDFIFO
+ 4'b 1111, // index[19] SPI_DEVICE_UPLOAD_ADDRFIFO
+ 4'b 1111, // index[20] SPI_DEVICE_CMD_FILTER_0
+ 4'b 1111, // index[21] SPI_DEVICE_CMD_FILTER_1
+ 4'b 1111, // index[22] SPI_DEVICE_CMD_FILTER_2
+ 4'b 1111, // index[23] SPI_DEVICE_CMD_FILTER_3
+ 4'b 1111, // index[24] SPI_DEVICE_CMD_FILTER_4
+ 4'b 1111, // index[25] SPI_DEVICE_CMD_FILTER_5
+ 4'b 1111, // index[26] SPI_DEVICE_CMD_FILTER_6
+ 4'b 1111, // index[27] SPI_DEVICE_CMD_FILTER_7
+ 4'b 1111, // index[28] SPI_DEVICE_ADDR_SWAP_MASK
+ 4'b 1111, // index[29] SPI_DEVICE_ADDR_SWAP_DATA
+ 4'b 1111, // index[30] SPI_DEVICE_CMD_INFO_0
+ 4'b 1111, // index[31] SPI_DEVICE_CMD_INFO_1
+ 4'b 1111, // index[32] SPI_DEVICE_CMD_INFO_2
+ 4'b 1111, // index[33] SPI_DEVICE_CMD_INFO_3
+ 4'b 1111, // index[34] SPI_DEVICE_CMD_INFO_4
+ 4'b 1111, // index[35] SPI_DEVICE_CMD_INFO_5
+ 4'b 1111, // index[36] SPI_DEVICE_CMD_INFO_6
+ 4'b 1111, // index[37] SPI_DEVICE_CMD_INFO_7
+ 4'b 1111, // index[38] SPI_DEVICE_CMD_INFO_8
+ 4'b 1111, // index[39] SPI_DEVICE_CMD_INFO_9
+ 4'b 1111, // index[40] SPI_DEVICE_CMD_INFO_10
+ 4'b 1111, // index[41] SPI_DEVICE_CMD_INFO_11
+ 4'b 1111, // index[42] SPI_DEVICE_CMD_INFO_12
+ 4'b 1111, // index[43] SPI_DEVICE_CMD_INFO_13
+ 4'b 1111, // index[44] SPI_DEVICE_CMD_INFO_14
+ 4'b 1111, // index[45] SPI_DEVICE_CMD_INFO_15
+ 4'b 1111, // index[46] SPI_DEVICE_CMD_INFO_16
+ 4'b 1111, // index[47] SPI_DEVICE_CMD_INFO_17
+ 4'b 1111, // index[48] SPI_DEVICE_CMD_INFO_18
+ 4'b 1111, // index[49] SPI_DEVICE_CMD_INFO_19
+ 4'b 1111, // index[50] SPI_DEVICE_CMD_INFO_20
+ 4'b 1111, // index[51] SPI_DEVICE_CMD_INFO_21
+ 4'b 1111, // index[52] SPI_DEVICE_CMD_INFO_22
+ 4'b 1111 // index[53] SPI_DEVICE_CMD_INFO_23
};
endpackage
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_top.sv b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
index fd349e0..53cceb7 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_top.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
@@ -264,6 +264,15 @@
logic read_threshold_we;
logic [9:0] read_threshold_qs;
logic [9:0] read_threshold_wd;
+ logic [4:0] upload_status_cmdfifo_depth_qs;
+ logic upload_status_cmdfifo_notempty_qs;
+ logic [4:0] upload_status_addrfifo_depth_qs;
+ logic upload_status_addrfifo_notempty_qs;
+ logic [8:0] upload_status_payload_depth_qs;
+ logic upload_cmdfifo_re;
+ logic [7:0] upload_cmdfifo_qs;
+ logic upload_addrfifo_re;
+ logic [31:0] upload_addrfifo_qs;
logic cmd_filter_0_we;
logic cmd_filter_0_filter_0_qs;
logic cmd_filter_0_filter_0_wd;
@@ -2581,6 +2590,170 @@
);
+ // R[upload_status]: V(False)
+
+ // F[cmdfifo_depth]: 4:0
+ prim_subreg #(
+ .DW (5),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (5'h0)
+ ) u_upload_status_cmdfifo_depth (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.upload_status.cmdfifo_depth.de),
+ .d (hw2reg.upload_status.cmdfifo_depth.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (upload_status_cmdfifo_depth_qs)
+ );
+
+
+ // F[cmdfifo_notempty]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_upload_status_cmdfifo_notempty (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.upload_status.cmdfifo_notempty.de),
+ .d (hw2reg.upload_status.cmdfifo_notempty.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (upload_status_cmdfifo_notempty_qs)
+ );
+
+
+ // F[addrfifo_depth]: 12:8
+ prim_subreg #(
+ .DW (5),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (5'h0)
+ ) u_upload_status_addrfifo_depth (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.upload_status.addrfifo_depth.de),
+ .d (hw2reg.upload_status.addrfifo_depth.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (upload_status_addrfifo_depth_qs)
+ );
+
+
+ // F[addrfifo_notempty]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_upload_status_addrfifo_notempty (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.upload_status.addrfifo_notempty.de),
+ .d (hw2reg.upload_status.addrfifo_notempty.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (upload_status_addrfifo_notempty_qs)
+ );
+
+
+ // F[payload_depth]: 24:16
+ prim_subreg #(
+ .DW (9),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (9'h0)
+ ) u_upload_status_payload_depth (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.upload_status.payload_depth.de),
+ .d (hw2reg.upload_status.payload_depth.d),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (upload_status_payload_depth_qs)
+ );
+
+
+ // R[upload_cmdfifo]: V(True)
+
+ prim_subreg_ext #(
+ .DW (8)
+ ) u_upload_cmdfifo (
+ .re (upload_cmdfifo_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.upload_cmdfifo.d),
+ .qre (reg2hw.upload_cmdfifo.re),
+ .qe (),
+ .q (reg2hw.upload_cmdfifo.q),
+ .qs (upload_cmdfifo_qs)
+ );
+
+
+ // R[upload_addrfifo]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_upload_addrfifo (
+ .re (upload_addrfifo_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.upload_addrfifo.d),
+ .qre (reg2hw.upload_addrfifo.re),
+ .qe (),
+ .q (reg2hw.upload_addrfifo.q),
+ .qs (upload_addrfifo_qs)
+ );
+
+
// Subregister 0 of Multireg cmd_filter
// R[cmd_filter_0]: V(False)
@@ -16257,7 +16430,7 @@
- logic [50:0] addr_hit;
+ logic [53:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == SPI_DEVICE_INTR_STATE_OFFSET);
@@ -16277,40 +16450,43 @@
addr_hit[14] = (reg_addr == SPI_DEVICE_FLASH_STATUS_OFFSET);
addr_hit[15] = (reg_addr == SPI_DEVICE_JEDEC_ID_OFFSET);
addr_hit[16] = (reg_addr == SPI_DEVICE_READ_THRESHOLD_OFFSET);
- addr_hit[17] = (reg_addr == SPI_DEVICE_CMD_FILTER_0_OFFSET);
- addr_hit[18] = (reg_addr == SPI_DEVICE_CMD_FILTER_1_OFFSET);
- addr_hit[19] = (reg_addr == SPI_DEVICE_CMD_FILTER_2_OFFSET);
- addr_hit[20] = (reg_addr == SPI_DEVICE_CMD_FILTER_3_OFFSET);
- addr_hit[21] = (reg_addr == SPI_DEVICE_CMD_FILTER_4_OFFSET);
- addr_hit[22] = (reg_addr == SPI_DEVICE_CMD_FILTER_5_OFFSET);
- addr_hit[23] = (reg_addr == SPI_DEVICE_CMD_FILTER_6_OFFSET);
- addr_hit[24] = (reg_addr == SPI_DEVICE_CMD_FILTER_7_OFFSET);
- addr_hit[25] = (reg_addr == SPI_DEVICE_ADDR_SWAP_MASK_OFFSET);
- addr_hit[26] = (reg_addr == SPI_DEVICE_ADDR_SWAP_DATA_OFFSET);
- addr_hit[27] = (reg_addr == SPI_DEVICE_CMD_INFO_0_OFFSET);
- addr_hit[28] = (reg_addr == SPI_DEVICE_CMD_INFO_1_OFFSET);
- addr_hit[29] = (reg_addr == SPI_DEVICE_CMD_INFO_2_OFFSET);
- addr_hit[30] = (reg_addr == SPI_DEVICE_CMD_INFO_3_OFFSET);
- addr_hit[31] = (reg_addr == SPI_DEVICE_CMD_INFO_4_OFFSET);
- addr_hit[32] = (reg_addr == SPI_DEVICE_CMD_INFO_5_OFFSET);
- addr_hit[33] = (reg_addr == SPI_DEVICE_CMD_INFO_6_OFFSET);
- addr_hit[34] = (reg_addr == SPI_DEVICE_CMD_INFO_7_OFFSET);
- addr_hit[35] = (reg_addr == SPI_DEVICE_CMD_INFO_8_OFFSET);
- addr_hit[36] = (reg_addr == SPI_DEVICE_CMD_INFO_9_OFFSET);
- addr_hit[37] = (reg_addr == SPI_DEVICE_CMD_INFO_10_OFFSET);
- addr_hit[38] = (reg_addr == SPI_DEVICE_CMD_INFO_11_OFFSET);
- addr_hit[39] = (reg_addr == SPI_DEVICE_CMD_INFO_12_OFFSET);
- addr_hit[40] = (reg_addr == SPI_DEVICE_CMD_INFO_13_OFFSET);
- addr_hit[41] = (reg_addr == SPI_DEVICE_CMD_INFO_14_OFFSET);
- addr_hit[42] = (reg_addr == SPI_DEVICE_CMD_INFO_15_OFFSET);
- addr_hit[43] = (reg_addr == SPI_DEVICE_CMD_INFO_16_OFFSET);
- addr_hit[44] = (reg_addr == SPI_DEVICE_CMD_INFO_17_OFFSET);
- addr_hit[45] = (reg_addr == SPI_DEVICE_CMD_INFO_18_OFFSET);
- addr_hit[46] = (reg_addr == SPI_DEVICE_CMD_INFO_19_OFFSET);
- addr_hit[47] = (reg_addr == SPI_DEVICE_CMD_INFO_20_OFFSET);
- addr_hit[48] = (reg_addr == SPI_DEVICE_CMD_INFO_21_OFFSET);
- addr_hit[49] = (reg_addr == SPI_DEVICE_CMD_INFO_22_OFFSET);
- addr_hit[50] = (reg_addr == SPI_DEVICE_CMD_INFO_23_OFFSET);
+ addr_hit[17] = (reg_addr == SPI_DEVICE_UPLOAD_STATUS_OFFSET);
+ addr_hit[18] = (reg_addr == SPI_DEVICE_UPLOAD_CMDFIFO_OFFSET);
+ addr_hit[19] = (reg_addr == SPI_DEVICE_UPLOAD_ADDRFIFO_OFFSET);
+ addr_hit[20] = (reg_addr == SPI_DEVICE_CMD_FILTER_0_OFFSET);
+ addr_hit[21] = (reg_addr == SPI_DEVICE_CMD_FILTER_1_OFFSET);
+ addr_hit[22] = (reg_addr == SPI_DEVICE_CMD_FILTER_2_OFFSET);
+ addr_hit[23] = (reg_addr == SPI_DEVICE_CMD_FILTER_3_OFFSET);
+ addr_hit[24] = (reg_addr == SPI_DEVICE_CMD_FILTER_4_OFFSET);
+ addr_hit[25] = (reg_addr == SPI_DEVICE_CMD_FILTER_5_OFFSET);
+ addr_hit[26] = (reg_addr == SPI_DEVICE_CMD_FILTER_6_OFFSET);
+ addr_hit[27] = (reg_addr == SPI_DEVICE_CMD_FILTER_7_OFFSET);
+ addr_hit[28] = (reg_addr == SPI_DEVICE_ADDR_SWAP_MASK_OFFSET);
+ addr_hit[29] = (reg_addr == SPI_DEVICE_ADDR_SWAP_DATA_OFFSET);
+ addr_hit[30] = (reg_addr == SPI_DEVICE_CMD_INFO_0_OFFSET);
+ addr_hit[31] = (reg_addr == SPI_DEVICE_CMD_INFO_1_OFFSET);
+ addr_hit[32] = (reg_addr == SPI_DEVICE_CMD_INFO_2_OFFSET);
+ addr_hit[33] = (reg_addr == SPI_DEVICE_CMD_INFO_3_OFFSET);
+ addr_hit[34] = (reg_addr == SPI_DEVICE_CMD_INFO_4_OFFSET);
+ addr_hit[35] = (reg_addr == SPI_DEVICE_CMD_INFO_5_OFFSET);
+ addr_hit[36] = (reg_addr == SPI_DEVICE_CMD_INFO_6_OFFSET);
+ addr_hit[37] = (reg_addr == SPI_DEVICE_CMD_INFO_7_OFFSET);
+ addr_hit[38] = (reg_addr == SPI_DEVICE_CMD_INFO_8_OFFSET);
+ addr_hit[39] = (reg_addr == SPI_DEVICE_CMD_INFO_9_OFFSET);
+ addr_hit[40] = (reg_addr == SPI_DEVICE_CMD_INFO_10_OFFSET);
+ addr_hit[41] = (reg_addr == SPI_DEVICE_CMD_INFO_11_OFFSET);
+ addr_hit[42] = (reg_addr == SPI_DEVICE_CMD_INFO_12_OFFSET);
+ addr_hit[43] = (reg_addr == SPI_DEVICE_CMD_INFO_13_OFFSET);
+ addr_hit[44] = (reg_addr == SPI_DEVICE_CMD_INFO_14_OFFSET);
+ addr_hit[45] = (reg_addr == SPI_DEVICE_CMD_INFO_15_OFFSET);
+ addr_hit[46] = (reg_addr == SPI_DEVICE_CMD_INFO_16_OFFSET);
+ addr_hit[47] = (reg_addr == SPI_DEVICE_CMD_INFO_17_OFFSET);
+ addr_hit[48] = (reg_addr == SPI_DEVICE_CMD_INFO_18_OFFSET);
+ addr_hit[49] = (reg_addr == SPI_DEVICE_CMD_INFO_19_OFFSET);
+ addr_hit[50] = (reg_addr == SPI_DEVICE_CMD_INFO_20_OFFSET);
+ addr_hit[51] = (reg_addr == SPI_DEVICE_CMD_INFO_21_OFFSET);
+ addr_hit[52] = (reg_addr == SPI_DEVICE_CMD_INFO_22_OFFSET);
+ addr_hit[53] = (reg_addr == SPI_DEVICE_CMD_INFO_23_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -16368,7 +16544,10 @@
(addr_hit[47] & (|(SPI_DEVICE_PERMIT[47] & ~reg_be))) |
(addr_hit[48] & (|(SPI_DEVICE_PERMIT[48] & ~reg_be))) |
(addr_hit[49] & (|(SPI_DEVICE_PERMIT[49] & ~reg_be))) |
- (addr_hit[50] & (|(SPI_DEVICE_PERMIT[50] & ~reg_be)))));
+ (addr_hit[50] & (|(SPI_DEVICE_PERMIT[50] & ~reg_be))) |
+ (addr_hit[51] & (|(SPI_DEVICE_PERMIT[51] & ~reg_be))) |
+ (addr_hit[52] & (|(SPI_DEVICE_PERMIT[52] & ~reg_be))) |
+ (addr_hit[53] & (|(SPI_DEVICE_PERMIT[53] & ~reg_be)))));
end
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
@@ -16474,7 +16653,9 @@
assign read_threshold_we = addr_hit[16] & reg_we & !reg_error;
assign read_threshold_wd = reg_wdata[9:0];
- assign cmd_filter_0_we = addr_hit[17] & reg_we & !reg_error;
+ assign upload_cmdfifo_re = addr_hit[18] & reg_re & !reg_error;
+ assign upload_addrfifo_re = addr_hit[19] & reg_re & !reg_error;
+ assign cmd_filter_0_we = addr_hit[20] & reg_we & !reg_error;
assign cmd_filter_0_filter_0_wd = reg_wdata[0];
@@ -16539,7 +16720,7 @@
assign cmd_filter_0_filter_30_wd = reg_wdata[30];
assign cmd_filter_0_filter_31_wd = reg_wdata[31];
- assign cmd_filter_1_we = addr_hit[18] & reg_we & !reg_error;
+ assign cmd_filter_1_we = addr_hit[21] & reg_we & !reg_error;
assign cmd_filter_1_filter_32_wd = reg_wdata[0];
@@ -16604,7 +16785,7 @@
assign cmd_filter_1_filter_62_wd = reg_wdata[30];
assign cmd_filter_1_filter_63_wd = reg_wdata[31];
- assign cmd_filter_2_we = addr_hit[19] & reg_we & !reg_error;
+ assign cmd_filter_2_we = addr_hit[22] & reg_we & !reg_error;
assign cmd_filter_2_filter_64_wd = reg_wdata[0];
@@ -16669,7 +16850,7 @@
assign cmd_filter_2_filter_94_wd = reg_wdata[30];
assign cmd_filter_2_filter_95_wd = reg_wdata[31];
- assign cmd_filter_3_we = addr_hit[20] & reg_we & !reg_error;
+ assign cmd_filter_3_we = addr_hit[23] & reg_we & !reg_error;
assign cmd_filter_3_filter_96_wd = reg_wdata[0];
@@ -16734,7 +16915,7 @@
assign cmd_filter_3_filter_126_wd = reg_wdata[30];
assign cmd_filter_3_filter_127_wd = reg_wdata[31];
- assign cmd_filter_4_we = addr_hit[21] & reg_we & !reg_error;
+ assign cmd_filter_4_we = addr_hit[24] & reg_we & !reg_error;
assign cmd_filter_4_filter_128_wd = reg_wdata[0];
@@ -16799,7 +16980,7 @@
assign cmd_filter_4_filter_158_wd = reg_wdata[30];
assign cmd_filter_4_filter_159_wd = reg_wdata[31];
- assign cmd_filter_5_we = addr_hit[22] & reg_we & !reg_error;
+ assign cmd_filter_5_we = addr_hit[25] & reg_we & !reg_error;
assign cmd_filter_5_filter_160_wd = reg_wdata[0];
@@ -16864,7 +17045,7 @@
assign cmd_filter_5_filter_190_wd = reg_wdata[30];
assign cmd_filter_5_filter_191_wd = reg_wdata[31];
- assign cmd_filter_6_we = addr_hit[23] & reg_we & !reg_error;
+ assign cmd_filter_6_we = addr_hit[26] & reg_we & !reg_error;
assign cmd_filter_6_filter_192_wd = reg_wdata[0];
@@ -16929,7 +17110,7 @@
assign cmd_filter_6_filter_222_wd = reg_wdata[30];
assign cmd_filter_6_filter_223_wd = reg_wdata[31];
- assign cmd_filter_7_we = addr_hit[24] & reg_we & !reg_error;
+ assign cmd_filter_7_we = addr_hit[27] & reg_we & !reg_error;
assign cmd_filter_7_filter_224_wd = reg_wdata[0];
@@ -16994,13 +17175,13 @@
assign cmd_filter_7_filter_254_wd = reg_wdata[30];
assign cmd_filter_7_filter_255_wd = reg_wdata[31];
- assign addr_swap_mask_we = addr_hit[25] & reg_we & !reg_error;
+ assign addr_swap_mask_we = addr_hit[28] & reg_we & !reg_error;
assign addr_swap_mask_wd = reg_wdata[31:0];
- assign addr_swap_data_we = addr_hit[26] & reg_we & !reg_error;
+ assign addr_swap_data_we = addr_hit[29] & reg_we & !reg_error;
assign addr_swap_data_wd = reg_wdata[31:0];
- assign cmd_info_0_we = addr_hit[27] & reg_we & !reg_error;
+ assign cmd_info_0_we = addr_hit[30] & reg_we & !reg_error;
assign cmd_info_0_opcode_0_wd = reg_wdata[7:0];
@@ -17023,7 +17204,7 @@
assign cmd_info_0_upload_0_wd = reg_wdata[24];
assign cmd_info_0_busy_0_wd = reg_wdata[25];
- assign cmd_info_1_we = addr_hit[28] & reg_we & !reg_error;
+ assign cmd_info_1_we = addr_hit[31] & reg_we & !reg_error;
assign cmd_info_1_opcode_1_wd = reg_wdata[7:0];
@@ -17046,7 +17227,7 @@
assign cmd_info_1_upload_1_wd = reg_wdata[24];
assign cmd_info_1_busy_1_wd = reg_wdata[25];
- assign cmd_info_2_we = addr_hit[29] & reg_we & !reg_error;
+ assign cmd_info_2_we = addr_hit[32] & reg_we & !reg_error;
assign cmd_info_2_opcode_2_wd = reg_wdata[7:0];
@@ -17069,7 +17250,7 @@
assign cmd_info_2_upload_2_wd = reg_wdata[24];
assign cmd_info_2_busy_2_wd = reg_wdata[25];
- assign cmd_info_3_we = addr_hit[30] & reg_we & !reg_error;
+ assign cmd_info_3_we = addr_hit[33] & reg_we & !reg_error;
assign cmd_info_3_opcode_3_wd = reg_wdata[7:0];
@@ -17092,7 +17273,7 @@
assign cmd_info_3_upload_3_wd = reg_wdata[24];
assign cmd_info_3_busy_3_wd = reg_wdata[25];
- assign cmd_info_4_we = addr_hit[31] & reg_we & !reg_error;
+ assign cmd_info_4_we = addr_hit[34] & reg_we & !reg_error;
assign cmd_info_4_opcode_4_wd = reg_wdata[7:0];
@@ -17115,7 +17296,7 @@
assign cmd_info_4_upload_4_wd = reg_wdata[24];
assign cmd_info_4_busy_4_wd = reg_wdata[25];
- assign cmd_info_5_we = addr_hit[32] & reg_we & !reg_error;
+ assign cmd_info_5_we = addr_hit[35] & reg_we & !reg_error;
assign cmd_info_5_opcode_5_wd = reg_wdata[7:0];
@@ -17138,7 +17319,7 @@
assign cmd_info_5_upload_5_wd = reg_wdata[24];
assign cmd_info_5_busy_5_wd = reg_wdata[25];
- assign cmd_info_6_we = addr_hit[33] & reg_we & !reg_error;
+ assign cmd_info_6_we = addr_hit[36] & reg_we & !reg_error;
assign cmd_info_6_opcode_6_wd = reg_wdata[7:0];
@@ -17161,7 +17342,7 @@
assign cmd_info_6_upload_6_wd = reg_wdata[24];
assign cmd_info_6_busy_6_wd = reg_wdata[25];
- assign cmd_info_7_we = addr_hit[34] & reg_we & !reg_error;
+ assign cmd_info_7_we = addr_hit[37] & reg_we & !reg_error;
assign cmd_info_7_opcode_7_wd = reg_wdata[7:0];
@@ -17184,7 +17365,7 @@
assign cmd_info_7_upload_7_wd = reg_wdata[24];
assign cmd_info_7_busy_7_wd = reg_wdata[25];
- assign cmd_info_8_we = addr_hit[35] & reg_we & !reg_error;
+ assign cmd_info_8_we = addr_hit[38] & reg_we & !reg_error;
assign cmd_info_8_opcode_8_wd = reg_wdata[7:0];
@@ -17207,7 +17388,7 @@
assign cmd_info_8_upload_8_wd = reg_wdata[24];
assign cmd_info_8_busy_8_wd = reg_wdata[25];
- assign cmd_info_9_we = addr_hit[36] & reg_we & !reg_error;
+ assign cmd_info_9_we = addr_hit[39] & reg_we & !reg_error;
assign cmd_info_9_opcode_9_wd = reg_wdata[7:0];
@@ -17230,7 +17411,7 @@
assign cmd_info_9_upload_9_wd = reg_wdata[24];
assign cmd_info_9_busy_9_wd = reg_wdata[25];
- assign cmd_info_10_we = addr_hit[37] & reg_we & !reg_error;
+ assign cmd_info_10_we = addr_hit[40] & reg_we & !reg_error;
assign cmd_info_10_opcode_10_wd = reg_wdata[7:0];
@@ -17253,7 +17434,7 @@
assign cmd_info_10_upload_10_wd = reg_wdata[24];
assign cmd_info_10_busy_10_wd = reg_wdata[25];
- assign cmd_info_11_we = addr_hit[38] & reg_we & !reg_error;
+ assign cmd_info_11_we = addr_hit[41] & reg_we & !reg_error;
assign cmd_info_11_opcode_11_wd = reg_wdata[7:0];
@@ -17276,7 +17457,7 @@
assign cmd_info_11_upload_11_wd = reg_wdata[24];
assign cmd_info_11_busy_11_wd = reg_wdata[25];
- assign cmd_info_12_we = addr_hit[39] & reg_we & !reg_error;
+ assign cmd_info_12_we = addr_hit[42] & reg_we & !reg_error;
assign cmd_info_12_opcode_12_wd = reg_wdata[7:0];
@@ -17299,7 +17480,7 @@
assign cmd_info_12_upload_12_wd = reg_wdata[24];
assign cmd_info_12_busy_12_wd = reg_wdata[25];
- assign cmd_info_13_we = addr_hit[40] & reg_we & !reg_error;
+ assign cmd_info_13_we = addr_hit[43] & reg_we & !reg_error;
assign cmd_info_13_opcode_13_wd = reg_wdata[7:0];
@@ -17322,7 +17503,7 @@
assign cmd_info_13_upload_13_wd = reg_wdata[24];
assign cmd_info_13_busy_13_wd = reg_wdata[25];
- assign cmd_info_14_we = addr_hit[41] & reg_we & !reg_error;
+ assign cmd_info_14_we = addr_hit[44] & reg_we & !reg_error;
assign cmd_info_14_opcode_14_wd = reg_wdata[7:0];
@@ -17345,7 +17526,7 @@
assign cmd_info_14_upload_14_wd = reg_wdata[24];
assign cmd_info_14_busy_14_wd = reg_wdata[25];
- assign cmd_info_15_we = addr_hit[42] & reg_we & !reg_error;
+ assign cmd_info_15_we = addr_hit[45] & reg_we & !reg_error;
assign cmd_info_15_opcode_15_wd = reg_wdata[7:0];
@@ -17368,7 +17549,7 @@
assign cmd_info_15_upload_15_wd = reg_wdata[24];
assign cmd_info_15_busy_15_wd = reg_wdata[25];
- assign cmd_info_16_we = addr_hit[43] & reg_we & !reg_error;
+ assign cmd_info_16_we = addr_hit[46] & reg_we & !reg_error;
assign cmd_info_16_opcode_16_wd = reg_wdata[7:0];
@@ -17391,7 +17572,7 @@
assign cmd_info_16_upload_16_wd = reg_wdata[24];
assign cmd_info_16_busy_16_wd = reg_wdata[25];
- assign cmd_info_17_we = addr_hit[44] & reg_we & !reg_error;
+ assign cmd_info_17_we = addr_hit[47] & reg_we & !reg_error;
assign cmd_info_17_opcode_17_wd = reg_wdata[7:0];
@@ -17414,7 +17595,7 @@
assign cmd_info_17_upload_17_wd = reg_wdata[24];
assign cmd_info_17_busy_17_wd = reg_wdata[25];
- assign cmd_info_18_we = addr_hit[45] & reg_we & !reg_error;
+ assign cmd_info_18_we = addr_hit[48] & reg_we & !reg_error;
assign cmd_info_18_opcode_18_wd = reg_wdata[7:0];
@@ -17437,7 +17618,7 @@
assign cmd_info_18_upload_18_wd = reg_wdata[24];
assign cmd_info_18_busy_18_wd = reg_wdata[25];
- assign cmd_info_19_we = addr_hit[46] & reg_we & !reg_error;
+ assign cmd_info_19_we = addr_hit[49] & reg_we & !reg_error;
assign cmd_info_19_opcode_19_wd = reg_wdata[7:0];
@@ -17460,7 +17641,7 @@
assign cmd_info_19_upload_19_wd = reg_wdata[24];
assign cmd_info_19_busy_19_wd = reg_wdata[25];
- assign cmd_info_20_we = addr_hit[47] & reg_we & !reg_error;
+ assign cmd_info_20_we = addr_hit[50] & reg_we & !reg_error;
assign cmd_info_20_opcode_20_wd = reg_wdata[7:0];
@@ -17483,7 +17664,7 @@
assign cmd_info_20_upload_20_wd = reg_wdata[24];
assign cmd_info_20_busy_20_wd = reg_wdata[25];
- assign cmd_info_21_we = addr_hit[48] & reg_we & !reg_error;
+ assign cmd_info_21_we = addr_hit[51] & reg_we & !reg_error;
assign cmd_info_21_opcode_21_wd = reg_wdata[7:0];
@@ -17506,7 +17687,7 @@
assign cmd_info_21_upload_21_wd = reg_wdata[24];
assign cmd_info_21_busy_21_wd = reg_wdata[25];
- assign cmd_info_22_we = addr_hit[49] & reg_we & !reg_error;
+ assign cmd_info_22_we = addr_hit[52] & reg_we & !reg_error;
assign cmd_info_22_opcode_22_wd = reg_wdata[7:0];
@@ -17529,7 +17710,7 @@
assign cmd_info_22_upload_22_wd = reg_wdata[24];
assign cmd_info_22_busy_22_wd = reg_wdata[25];
- assign cmd_info_23_we = addr_hit[50] & reg_we & !reg_error;
+ assign cmd_info_23_we = addr_hit[53] & reg_we & !reg_error;
assign cmd_info_23_opcode_23_wd = reg_wdata[7:0];
@@ -17663,6 +17844,22 @@
end
addr_hit[17]: begin
+ reg_rdata_next[4:0] = upload_status_cmdfifo_depth_qs;
+ reg_rdata_next[7] = upload_status_cmdfifo_notempty_qs;
+ reg_rdata_next[12:8] = upload_status_addrfifo_depth_qs;
+ reg_rdata_next[15] = upload_status_addrfifo_notempty_qs;
+ reg_rdata_next[24:16] = upload_status_payload_depth_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[7:0] = upload_cmdfifo_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[31:0] = upload_addrfifo_qs;
+ end
+
+ addr_hit[20]: begin
reg_rdata_next[0] = cmd_filter_0_filter_0_qs;
reg_rdata_next[1] = cmd_filter_0_filter_1_qs;
reg_rdata_next[2] = cmd_filter_0_filter_2_qs;
@@ -17697,7 +17894,7 @@
reg_rdata_next[31] = cmd_filter_0_filter_31_qs;
end
- addr_hit[18]: begin
+ addr_hit[21]: begin
reg_rdata_next[0] = cmd_filter_1_filter_32_qs;
reg_rdata_next[1] = cmd_filter_1_filter_33_qs;
reg_rdata_next[2] = cmd_filter_1_filter_34_qs;
@@ -17732,7 +17929,7 @@
reg_rdata_next[31] = cmd_filter_1_filter_63_qs;
end
- addr_hit[19]: begin
+ addr_hit[22]: begin
reg_rdata_next[0] = cmd_filter_2_filter_64_qs;
reg_rdata_next[1] = cmd_filter_2_filter_65_qs;
reg_rdata_next[2] = cmd_filter_2_filter_66_qs;
@@ -17767,7 +17964,7 @@
reg_rdata_next[31] = cmd_filter_2_filter_95_qs;
end
- addr_hit[20]: begin
+ addr_hit[23]: begin
reg_rdata_next[0] = cmd_filter_3_filter_96_qs;
reg_rdata_next[1] = cmd_filter_3_filter_97_qs;
reg_rdata_next[2] = cmd_filter_3_filter_98_qs;
@@ -17802,7 +17999,7 @@
reg_rdata_next[31] = cmd_filter_3_filter_127_qs;
end
- addr_hit[21]: begin
+ addr_hit[24]: begin
reg_rdata_next[0] = cmd_filter_4_filter_128_qs;
reg_rdata_next[1] = cmd_filter_4_filter_129_qs;
reg_rdata_next[2] = cmd_filter_4_filter_130_qs;
@@ -17837,7 +18034,7 @@
reg_rdata_next[31] = cmd_filter_4_filter_159_qs;
end
- addr_hit[22]: begin
+ addr_hit[25]: begin
reg_rdata_next[0] = cmd_filter_5_filter_160_qs;
reg_rdata_next[1] = cmd_filter_5_filter_161_qs;
reg_rdata_next[2] = cmd_filter_5_filter_162_qs;
@@ -17872,7 +18069,7 @@
reg_rdata_next[31] = cmd_filter_5_filter_191_qs;
end
- addr_hit[23]: begin
+ addr_hit[26]: begin
reg_rdata_next[0] = cmd_filter_6_filter_192_qs;
reg_rdata_next[1] = cmd_filter_6_filter_193_qs;
reg_rdata_next[2] = cmd_filter_6_filter_194_qs;
@@ -17907,7 +18104,7 @@
reg_rdata_next[31] = cmd_filter_6_filter_223_qs;
end
- addr_hit[24]: begin
+ addr_hit[27]: begin
reg_rdata_next[0] = cmd_filter_7_filter_224_qs;
reg_rdata_next[1] = cmd_filter_7_filter_225_qs;
reg_rdata_next[2] = cmd_filter_7_filter_226_qs;
@@ -17942,15 +18139,15 @@
reg_rdata_next[31] = cmd_filter_7_filter_255_qs;
end
- addr_hit[25]: begin
+ addr_hit[28]: begin
reg_rdata_next[31:0] = addr_swap_mask_qs;
end
- addr_hit[26]: begin
+ addr_hit[29]: begin
reg_rdata_next[31:0] = addr_swap_data_qs;
end
- addr_hit[27]: begin
+ addr_hit[30]: begin
reg_rdata_next[7:0] = cmd_info_0_opcode_0_qs;
reg_rdata_next[8] = cmd_info_0_addr_en_0_qs;
reg_rdata_next[9] = cmd_info_0_addr_swap_en_0_qs;
@@ -17964,7 +18161,7 @@
reg_rdata_next[25] = cmd_info_0_busy_0_qs;
end
- addr_hit[28]: begin
+ addr_hit[31]: begin
reg_rdata_next[7:0] = cmd_info_1_opcode_1_qs;
reg_rdata_next[8] = cmd_info_1_addr_en_1_qs;
reg_rdata_next[9] = cmd_info_1_addr_swap_en_1_qs;
@@ -17978,7 +18175,7 @@
reg_rdata_next[25] = cmd_info_1_busy_1_qs;
end
- addr_hit[29]: begin
+ addr_hit[32]: begin
reg_rdata_next[7:0] = cmd_info_2_opcode_2_qs;
reg_rdata_next[8] = cmd_info_2_addr_en_2_qs;
reg_rdata_next[9] = cmd_info_2_addr_swap_en_2_qs;
@@ -17992,7 +18189,7 @@
reg_rdata_next[25] = cmd_info_2_busy_2_qs;
end
- addr_hit[30]: begin
+ addr_hit[33]: begin
reg_rdata_next[7:0] = cmd_info_3_opcode_3_qs;
reg_rdata_next[8] = cmd_info_3_addr_en_3_qs;
reg_rdata_next[9] = cmd_info_3_addr_swap_en_3_qs;
@@ -18006,7 +18203,7 @@
reg_rdata_next[25] = cmd_info_3_busy_3_qs;
end
- addr_hit[31]: begin
+ addr_hit[34]: begin
reg_rdata_next[7:0] = cmd_info_4_opcode_4_qs;
reg_rdata_next[8] = cmd_info_4_addr_en_4_qs;
reg_rdata_next[9] = cmd_info_4_addr_swap_en_4_qs;
@@ -18020,7 +18217,7 @@
reg_rdata_next[25] = cmd_info_4_busy_4_qs;
end
- addr_hit[32]: begin
+ addr_hit[35]: begin
reg_rdata_next[7:0] = cmd_info_5_opcode_5_qs;
reg_rdata_next[8] = cmd_info_5_addr_en_5_qs;
reg_rdata_next[9] = cmd_info_5_addr_swap_en_5_qs;
@@ -18034,7 +18231,7 @@
reg_rdata_next[25] = cmd_info_5_busy_5_qs;
end
- addr_hit[33]: begin
+ addr_hit[36]: begin
reg_rdata_next[7:0] = cmd_info_6_opcode_6_qs;
reg_rdata_next[8] = cmd_info_6_addr_en_6_qs;
reg_rdata_next[9] = cmd_info_6_addr_swap_en_6_qs;
@@ -18048,7 +18245,7 @@
reg_rdata_next[25] = cmd_info_6_busy_6_qs;
end
- addr_hit[34]: begin
+ addr_hit[37]: begin
reg_rdata_next[7:0] = cmd_info_7_opcode_7_qs;
reg_rdata_next[8] = cmd_info_7_addr_en_7_qs;
reg_rdata_next[9] = cmd_info_7_addr_swap_en_7_qs;
@@ -18062,7 +18259,7 @@
reg_rdata_next[25] = cmd_info_7_busy_7_qs;
end
- addr_hit[35]: begin
+ addr_hit[38]: begin
reg_rdata_next[7:0] = cmd_info_8_opcode_8_qs;
reg_rdata_next[8] = cmd_info_8_addr_en_8_qs;
reg_rdata_next[9] = cmd_info_8_addr_swap_en_8_qs;
@@ -18076,7 +18273,7 @@
reg_rdata_next[25] = cmd_info_8_busy_8_qs;
end
- addr_hit[36]: begin
+ addr_hit[39]: begin
reg_rdata_next[7:0] = cmd_info_9_opcode_9_qs;
reg_rdata_next[8] = cmd_info_9_addr_en_9_qs;
reg_rdata_next[9] = cmd_info_9_addr_swap_en_9_qs;
@@ -18090,7 +18287,7 @@
reg_rdata_next[25] = cmd_info_9_busy_9_qs;
end
- addr_hit[37]: begin
+ addr_hit[40]: begin
reg_rdata_next[7:0] = cmd_info_10_opcode_10_qs;
reg_rdata_next[8] = cmd_info_10_addr_en_10_qs;
reg_rdata_next[9] = cmd_info_10_addr_swap_en_10_qs;
@@ -18104,7 +18301,7 @@
reg_rdata_next[25] = cmd_info_10_busy_10_qs;
end
- addr_hit[38]: begin
+ addr_hit[41]: begin
reg_rdata_next[7:0] = cmd_info_11_opcode_11_qs;
reg_rdata_next[8] = cmd_info_11_addr_en_11_qs;
reg_rdata_next[9] = cmd_info_11_addr_swap_en_11_qs;
@@ -18118,7 +18315,7 @@
reg_rdata_next[25] = cmd_info_11_busy_11_qs;
end
- addr_hit[39]: begin
+ addr_hit[42]: begin
reg_rdata_next[7:0] = cmd_info_12_opcode_12_qs;
reg_rdata_next[8] = cmd_info_12_addr_en_12_qs;
reg_rdata_next[9] = cmd_info_12_addr_swap_en_12_qs;
@@ -18132,7 +18329,7 @@
reg_rdata_next[25] = cmd_info_12_busy_12_qs;
end
- addr_hit[40]: begin
+ addr_hit[43]: begin
reg_rdata_next[7:0] = cmd_info_13_opcode_13_qs;
reg_rdata_next[8] = cmd_info_13_addr_en_13_qs;
reg_rdata_next[9] = cmd_info_13_addr_swap_en_13_qs;
@@ -18146,7 +18343,7 @@
reg_rdata_next[25] = cmd_info_13_busy_13_qs;
end
- addr_hit[41]: begin
+ addr_hit[44]: begin
reg_rdata_next[7:0] = cmd_info_14_opcode_14_qs;
reg_rdata_next[8] = cmd_info_14_addr_en_14_qs;
reg_rdata_next[9] = cmd_info_14_addr_swap_en_14_qs;
@@ -18160,7 +18357,7 @@
reg_rdata_next[25] = cmd_info_14_busy_14_qs;
end
- addr_hit[42]: begin
+ addr_hit[45]: begin
reg_rdata_next[7:0] = cmd_info_15_opcode_15_qs;
reg_rdata_next[8] = cmd_info_15_addr_en_15_qs;
reg_rdata_next[9] = cmd_info_15_addr_swap_en_15_qs;
@@ -18174,7 +18371,7 @@
reg_rdata_next[25] = cmd_info_15_busy_15_qs;
end
- addr_hit[43]: begin
+ addr_hit[46]: begin
reg_rdata_next[7:0] = cmd_info_16_opcode_16_qs;
reg_rdata_next[8] = cmd_info_16_addr_en_16_qs;
reg_rdata_next[9] = cmd_info_16_addr_swap_en_16_qs;
@@ -18188,7 +18385,7 @@
reg_rdata_next[25] = cmd_info_16_busy_16_qs;
end
- addr_hit[44]: begin
+ addr_hit[47]: begin
reg_rdata_next[7:0] = cmd_info_17_opcode_17_qs;
reg_rdata_next[8] = cmd_info_17_addr_en_17_qs;
reg_rdata_next[9] = cmd_info_17_addr_swap_en_17_qs;
@@ -18202,7 +18399,7 @@
reg_rdata_next[25] = cmd_info_17_busy_17_qs;
end
- addr_hit[45]: begin
+ addr_hit[48]: begin
reg_rdata_next[7:0] = cmd_info_18_opcode_18_qs;
reg_rdata_next[8] = cmd_info_18_addr_en_18_qs;
reg_rdata_next[9] = cmd_info_18_addr_swap_en_18_qs;
@@ -18216,7 +18413,7 @@
reg_rdata_next[25] = cmd_info_18_busy_18_qs;
end
- addr_hit[46]: begin
+ addr_hit[49]: begin
reg_rdata_next[7:0] = cmd_info_19_opcode_19_qs;
reg_rdata_next[8] = cmd_info_19_addr_en_19_qs;
reg_rdata_next[9] = cmd_info_19_addr_swap_en_19_qs;
@@ -18230,7 +18427,7 @@
reg_rdata_next[25] = cmd_info_19_busy_19_qs;
end
- addr_hit[47]: begin
+ addr_hit[50]: begin
reg_rdata_next[7:0] = cmd_info_20_opcode_20_qs;
reg_rdata_next[8] = cmd_info_20_addr_en_20_qs;
reg_rdata_next[9] = cmd_info_20_addr_swap_en_20_qs;
@@ -18244,7 +18441,7 @@
reg_rdata_next[25] = cmd_info_20_busy_20_qs;
end
- addr_hit[48]: begin
+ addr_hit[51]: begin
reg_rdata_next[7:0] = cmd_info_21_opcode_21_qs;
reg_rdata_next[8] = cmd_info_21_addr_en_21_qs;
reg_rdata_next[9] = cmd_info_21_addr_swap_en_21_qs;
@@ -18258,7 +18455,7 @@
reg_rdata_next[25] = cmd_info_21_busy_21_qs;
end
- addr_hit[49]: begin
+ addr_hit[52]: begin
reg_rdata_next[7:0] = cmd_info_22_opcode_22_qs;
reg_rdata_next[8] = cmd_info_22_addr_en_22_qs;
reg_rdata_next[9] = cmd_info_22_addr_swap_en_22_qs;
@@ -18272,7 +18469,7 @@
reg_rdata_next[25] = cmd_info_22_busy_22_qs;
end
- addr_hit[50]: begin
+ addr_hit[53]: begin
reg_rdata_next[7:0] = cmd_info_23_opcode_23_qs;
reg_rdata_next[8] = cmd_info_23_addr_en_23_qs;
reg_rdata_next[9] = cmd_info_23_addr_swap_en_23_qs;
diff --git a/hw/ip/spi_device/rtl/spid_upload.sv b/hw/ip/spi_device/rtl/spid_upload.sv
index eeb68d6..3f72012 100644
--- a/hw/ip/spi_device/rtl/spid_upload.sv
+++ b/hw/ip/spi_device/rtl/spid_upload.sv
@@ -45,9 +45,8 @@
localparam int unsigned CmdPtrW = $clog2(CmdFifoDepth+1),
localparam int unsigned AddrPtrW = $clog2(AddrFifoDepth+1),
- localparam int unsigned PayloadByte = PayloadDepth * (SramDw/SpiByte),
- localparam int unsigned PayloadW = $clog2(PayloadByte),
- localparam int unsigned PayloadPtrW = $clog2(PayloadByte+1)
+ localparam int unsigned PayloadByte = PayloadDepth * (SramDw/SpiByte),
+ localparam int unsigned PayloadPtrW = $clog2(PayloadByte+1)
) (
input clk_i,
input rst_ni,
@@ -107,6 +106,8 @@
output logic sys_addrfifo_notempty_o,
output logic sys_addrfifo_full_o,
+ output logic [CmdPtrW-1:0] sys_cmdfifo_depth_o,
+ output logic [AddrPtrW-1:0] sys_addrfifo_depth_o,
output logic [PayloadPtrW-1:0] sys_payload_depth_o
);
@@ -382,7 +383,7 @@
.rvalid_o (sys_cmdfifo_rvalid_o),
.rready_i (sys_cmdfifo_rready_i),
.rdata_o (sys_cmdfifo_rdata_o),
- .rdepth_o (), // not used
+ .rdepth_o (sys_cmdfifo_depth_o),
.r_full_o (sys_cmdfifo_full_o),
.r_notempty_o (sys_cmdfifo_notempty_o),
@@ -443,7 +444,7 @@
.rvalid_o (sys_addrfifo_rvalid_o),
.rready_i (sys_addrfifo_rready_i),
.rdata_o (sys_addrfifo_rdata_o),
- .rdepth_o (),
+ .rdepth_o (sys_addrfifo_depth_o),
.r_full_o (sys_addrfifo_full_o),
.r_notempty_o (sys_addrfifo_notempty_o),
