[opentitanlib] Add alert_handler CRC32 generation
As per PR #13468 the register values in alert_handler are read back as
part of rom_pre_boot_check(), summed under a CRC32, and compared to a
lifecycle specific value in OTP. This PR mimics the alert_handler
register initialization to produce the same CRC32 value for programming
into OTP.
Signed-off-by: Jon Flatley <jflat@google.com>
diff --git a/sw/host/opentitanlib/BUILD b/sw/host/opentitanlib/BUILD
index fc915e2..db6a507 100644
--- a/sw/host/opentitanlib/BUILD
+++ b/sw/host/opentitanlib/BUILD
@@ -51,6 +51,8 @@
"src/io/spi.rs",
"src/io/uart.rs",
"src/lib.rs",
+ "src/otp/alert_handler.rs",
+ "src/otp/alert_handler_regs.rs",
"src/otp/lc_state.rs",
"src/otp/mod.rs",
"src/otp/otp.rs",
@@ -135,8 +137,10 @@
deps = [
"//third_party/rust/crates:anyhow",
"//third_party/rust/crates:bitflags",
+ "//third_party/rust/crates:bitvec",
"//third_party/rust/crates:byteorder",
"//third_party/rust/crates:chrono",
+ "//third_party/rust/crates:crc",
"//third_party/rust/crates:deser_hjson",
"//third_party/rust/crates:directories",
"//third_party/rust/crates:env_logger",
diff --git a/sw/host/opentitanlib/src/otp/alert_handler.rs b/sw/host/opentitanlib/src/otp/alert_handler.rs
new file mode 100644
index 0000000..cc8a1b2
--- /dev/null
+++ b/sw/host/opentitanlib/src/otp/alert_handler.rs
@@ -0,0 +1,465 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+use crate::otp::alert_handler_regs::*;
+use crate::otp::lc_state::LcStateVal;
+use crate::otp::otp_img::OtpRead;
+
+use anyhow::{bail, Result};
+use bitvec::prelude::*;
+use crc::{Crc, Digest};
+use num_enum::TryFromPrimitive;
+
+use std::convert::TryFrom;
+
+/// ALERT_HANDLER_ALERT_CLASS related register values.
+#[derive(Clone, Copy)]
+struct AlertClassRegs {
+ regwen: u32,
+ ctrl: u32,
+ accum_thresh: u32,
+ timeout_cyc: u32,
+ phase_cycs: [u32; ALERT_HANDLER_PARAM_N_PHASES as usize],
+}
+
+/// Register values for alert_handler used in CRC32 calculation.
+pub struct AlertRegs {
+ /// ALERT_HANDLER_LOC_ALERT_REGWEN
+ regwen: [u32; ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT as usize],
+ /// ALERT_HANDLER_ALERT_EN_SHADOWED
+ en: [u32; ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT as usize],
+ /// ALERT_HANDLER_ALERT_CLASS_SHADOWED
+ class: [u32; ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT as usize],
+ /// ALERT_HANDLER_LOC_ALERT_REGWEN
+ loc_regwen: [u32; ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT as usize],
+ /// ALERT_HANDLER_LOC_ALERT_EN_SHADOWED
+ loc_en: [u32; ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT as usize],
+ /// ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED
+ loc_class: [u32; ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT as usize],
+ /// Alert handler class registers
+ class_regs: [AlertClassRegs; ALERT_HANDLER_PARAM_N_CLASSES as usize],
+}
+
+/// Alert classification values.
+///
+/// Based on values generated by sparse-fsm-encode.py and defined in
+/// sw/device/silicon_creator/lib/drivers/alert.h as alert_class_t.
+#[derive(TryFromPrimitive)]
+#[repr(u8)]
+enum AlertClass {
+ X = 0x94,
+ A = 0xee,
+ B = 0x64,
+ C = 0xa7,
+ D = 0x32,
+}
+
+impl AlertClass {
+ fn index(&self) -> usize {
+ match self {
+ AlertClass::A => 0,
+ AlertClass::B => 1,
+ AlertClass::C => 2,
+ AlertClass::D => 3,
+ AlertClass::X => 0,
+ }
+ }
+
+ fn from_index(index: usize) -> Self {
+ match index {
+ 0 => AlertClass::A,
+ 1 => AlertClass::B,
+ 2 => AlertClass::C,
+ 3 => AlertClass::D,
+ _ => AlertClass::X,
+ }
+ }
+}
+
+#[derive(TryFromPrimitive)]
+#[repr(u8)]
+enum AlertEnable {
+ None = 0xa9,
+ Enabled = 0x07,
+ Locked = 0xd2,
+}
+
+#[derive(TryFromPrimitive)]
+#[repr(u8)]
+enum AlertEscalate {
+ None = 0xd1,
+ Phase0 = 0xb9,
+ Phase1 = 0xcb,
+ Phase2 = 0x25,
+ Phase3 = 0x76,
+}
+
+struct AlertClassConfig {
+ enabled: AlertEnable,
+ escalate: AlertEscalate,
+ accum_thresh: u32,
+ timeout_cyc: u32,
+ phase_cycs: [u32; ALERT_HANDLER_PARAM_N_PHASES as usize],
+}
+
+impl Default for AlertClassRegs {
+ fn default() -> Self {
+ AlertClassRegs {
+ regwen: 1,
+ ctrl: 0,
+ accum_thresh: 0,
+ timeout_cyc: 0,
+ phase_cycs: [0; ALERT_HANDLER_PARAM_N_PHASES as usize],
+ }
+ }
+}
+
+impl Default for AlertRegs {
+ fn default() -> Self {
+ AlertRegs {
+ regwen: [1; ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT as usize],
+ loc_regwen: [1; ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT as usize],
+ en: [0; ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT as usize],
+ class: [0; ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT as usize],
+ loc_en: [0; ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT as usize],
+ loc_class: [0; ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT as usize],
+ class_regs: [Default::default(); ALERT_HANDLER_PARAM_N_CLASSES as usize],
+ }
+ }
+}
+
+impl AlertRegs {
+ pub fn crc32(self) -> u32 {
+ let crc = new_crc();
+ let mut digest = crc.digest();
+ self.crc32_add(&mut digest);
+ digest.finalize()
+ }
+
+ pub fn new<T: OtpRead>(lc_state: LcStateVal, otp: &T) -> Result<Self> {
+ let mut alert = AlertRegs::default();
+
+ let lc_shift = match lc_state {
+ LcStateVal::Prod => 0,
+ LcStateVal::ProdEnd => 8,
+ LcStateVal::Dev => 16,
+ LcStateVal::Rma => 24,
+ LcStateVal::Test => return Ok(alert),
+ };
+
+ let class_enable = otp.read32("ROM_ALERT_CLASS_EN")?;
+ let class_escalate = otp.read32("ROM_ALERT_CLASS_ESCALATION")?;
+
+ for i in 0..ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT as usize {
+ let value = otp.read32_offset(Some("ROM_ALERT_CLASSIFICATION"), i * 4)?;
+ let cls = AlertClass::try_from(
+ value.view_bits::<Lsb0>()[lc_shift..lc_shift + 1].load_le::<u8>(),
+ )?;
+ let enable = AlertEnable::try_from(
+ class_enable.view_bits::<Lsb0>()[cls.index()..cls.index() + 1].load_le::<u8>(),
+ )?;
+ alert.configure(i, cls, enable)?;
+ }
+
+ for i in 0..ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT as usize {
+ let value = otp.read32_offset(Some("ROM_LOCAL_ALERT_CLASSIFICATION"), i * 4)?;
+ let cls = AlertClass::try_from(
+ value.view_bits::<Lsb0>()[lc_shift..lc_shift + 1].load_le::<u8>(),
+ )?;
+ let enable = AlertEnable::try_from(
+ class_enable.view_bits::<Lsb0>()[cls.index()..cls.index() + 1].load_le::<u8>(),
+ )?;
+ alert.local_configure(i, cls, enable)?;
+ }
+
+ for i in 0..ALERT_HANDLER_PARAM_N_CLASSES as usize {
+ let mut phase_cycs = [0; ALERT_HANDLER_PARAM_N_PHASES as usize];
+ for phase in 0..ALERT_HANDLER_PARAM_N_PHASES as usize {
+ phase_cycs[phase] = otp
+ .read32_offset(Some("ROM_ALERT_PHASE_CYCLES"), i * phase_cycs.len() + phase)?;
+ }
+ let config = AlertClassConfig {
+ enabled: AlertEnable::try_from(
+ class_enable.view_bits::<Lsb0>()[i..i + 1].load_le::<u8>(),
+ )?,
+ escalate: AlertEscalate::try_from(
+ class_escalate.view_bits::<Lsb0>()[i..i + 1].load_le::<u8>(),
+ )?,
+ accum_thresh: otp.read32_offset(Some("ROM_ALERT_ACCUM_THRESH"), i * 4)?,
+ timeout_cyc: otp.read32_offset(Some("ROM_ALERT_TIMEOUT_CYCLES"), i * 4)?,
+ phase_cycs,
+ };
+ alert.class_configure(AlertClass::from_index(i), &config)?;
+ }
+
+ Ok(alert)
+ }
+
+ fn configure(&mut self, index: usize, cls: AlertClass, enabled: AlertEnable) -> Result<()> {
+ if index >= ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT as usize {
+ bail!("Bad alert index {}", index);
+ }
+
+ self.class[index] = match cls {
+ AlertClass::A => ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA,
+ AlertClass::B => ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB,
+ AlertClass::C => ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC,
+ AlertClass::D => ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD,
+ AlertClass::X => return Ok(()),
+ };
+
+ match enabled {
+ AlertEnable::None => {}
+ AlertEnable::Enabled => self.en[index] = 1,
+ AlertEnable::Locked => {
+ self.en[index] = 1;
+ self.regwen[index] = 0;
+ }
+ };
+
+ Ok(())
+ }
+
+ fn local_configure(
+ &mut self,
+ index: usize,
+ cls: AlertClass,
+ enabled: AlertEnable,
+ ) -> Result<()> {
+ if index >= ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT as usize {
+ bail!("Bad local alert index {}", index);
+ }
+
+ self.loc_class[index] = match cls {
+ AlertClass::A => ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA,
+ AlertClass::B => ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB,
+ AlertClass::C => ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC,
+ AlertClass::D => ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD,
+ AlertClass::X => return Ok(()),
+ };
+
+ match enabled {
+ AlertEnable::None => {}
+ AlertEnable::Enabled => self.loc_en[index] = 1,
+ AlertEnable::Locked => {
+ self.loc_en[index] = 1;
+ self.loc_regwen[index] = 0;
+ }
+ };
+
+ Ok(())
+ }
+
+ fn class_configure(&mut self, cls: AlertClass, config: &AlertClassConfig) -> Result<()> {
+ let index = match cls {
+ AlertClass::A => 0,
+ AlertClass::B => 1,
+ AlertClass::C => 2,
+ AlertClass::D => 3,
+ AlertClass::X => bail!("Bad class"),
+ };
+
+ let mut reg = 0 as u32;
+ let reg_bits = reg.view_bits_mut::<Lsb0>();
+ match config.enabled {
+ AlertEnable::None => {}
+ AlertEnable::Enabled => {
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT as usize, true);
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT as usize, true);
+ }
+ AlertEnable::Locked => {
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT as usize, true)
+ }
+ }
+
+ match config.escalate {
+ AlertEscalate::Phase0 => {
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT as usize, true)
+ }
+ AlertEscalate::Phase1 => {
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT as usize, true);
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT as usize, true);
+ }
+ AlertEscalate::Phase2 => {
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT as usize, true);
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT as usize, true);
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT as usize, true);
+ }
+ AlertEscalate::Phase3 => {
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT as usize, true);
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT as usize, true);
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT as usize, true);
+ reg_bits.set(ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT as usize, true);
+ }
+ AlertEscalate::None => {}
+ }
+
+ self.class[index] = reg;
+ self.class_regs[index].accum_thresh = config.accum_thresh;
+ self.class_regs[index].timeout_cyc = config.timeout_cyc;
+ self.class_regs[index].phase_cycs = config.phase_cycs;
+
+ Ok(())
+ }
+}
+
+trait CRC32Add {
+ fn crc32_add(self, diegst: &mut Digest<u32>);
+}
+
+impl CRC32Add for u32 {
+ fn crc32_add(self, digest: &mut Digest<u32>) {
+ digest.update(self.to_le_bytes().as_slice())
+ }
+}
+
+impl<T: CRC32Add, const N: usize> CRC32Add for [T; N] {
+ fn crc32_add(self, digest: &mut Digest<u32>) {
+ self.map(|v| v.crc32_add(digest));
+ }
+}
+
+impl CRC32Add for AlertClassRegs {
+ fn crc32_add(self, digest: &mut Digest<u32>) {
+ self.regwen.crc32_add(digest);
+ self.ctrl.crc32_add(digest);
+ self.accum_thresh.crc32_add(digest);
+ self.timeout_cyc.crc32_add(digest);
+ self.phase_cycs.crc32_add(digest);
+ }
+}
+
+impl CRC32Add for AlertRegs {
+ fn crc32_add(self, digest: &mut Digest<u32>) {
+ self.regwen.crc32_add(digest);
+ self.en.crc32_add(digest);
+ self.class.crc32_add(digest);
+ self.loc_regwen.crc32_add(digest);
+ self.loc_en.crc32_add(digest);
+ self.loc_class.crc32_add(digest);
+ self.class_regs.crc32_add(digest);
+ }
+}
+
+fn new_crc() -> Crc<u32> {
+ Crc::<u32>::new(&crc::CRC_32_ISO_HDLC)
+}
+
+#[cfg(test)]
+mod test {
+ use super::*;
+
+ // Register values dumped from device after alert_handler initialization.
+ const TEST_REGS: AlertRegs = AlertRegs {
+ regwen: [
+ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+ 0x00000001, 0x00000001,
+ ],
+ en: [
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+ ],
+ class: [
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000,
+ ],
+ loc_regwen: [
+ 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+ ],
+ loc_en: [
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ ],
+ loc_class: [
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ ],
+ class_regs: [
+ AlertClassRegs {
+ regwen: 0x00000001,
+ ctrl: 0x00003900,
+ accum_thresh: 0x00000000,
+ timeout_cyc: 0x00000000,
+ phase_cycs: [0x00000000, 0x0000000a, 0x0000000a, 0xffffffff],
+ },
+ AlertClassRegs {
+ regwen: 0x00000001,
+ ctrl: 0x00003900,
+ accum_thresh: 0x00000000,
+ timeout_cyc: 0x00000000,
+ phase_cycs: [0x00000000, 0x0000000a, 0x0000000a, 0xffffffff],
+ },
+ AlertClassRegs {
+ regwen: 0x00000001,
+ ctrl: 0x00003900,
+ accum_thresh: 0x00000000,
+ timeout_cyc: 0x00000000,
+ phase_cycs: [0x00000000, 0x00000000, 0x00000000, 0x00000000],
+ },
+ AlertClassRegs {
+ regwen: 0x00000001,
+ ctrl: 0x00003900,
+ accum_thresh: 0x00000000,
+ timeout_cyc: 0x00000000,
+ phase_cycs: [0x00000000, 0x00000000, 0x00000000, 0x00000000],
+ },
+ ],
+ };
+
+ struct TestOtp {}
+
+ impl OtpRead for TestOtp {
+ fn read32_offset(&self, name: Option<&str>, offset: usize) -> Result<u32> {
+ let mut start_offset = 0;
+ if let Some(name) = name {}
+ Ok(0)
+ }
+ }
+
+ // A sanity test to make sure the correct CRC algorithm is being used.
+ #[test]
+ fn test_new_crc() {
+ let crc = new_crc();
+ let mut digest = crc.digest();
+ digest.update(b"123456789");
+ assert_eq!(digest.finalize(), 0xcbf43926);
+
+ let crc = new_crc();
+ let mut digest = crc.digest();
+ digest.update(b"The quick brown fox jumps over the lazy dog");
+ assert_eq!(digest.finalize(), 0x414fa339);
+
+ let crc = new_crc();
+ let mut digest = crc.digest();
+ digest.update(b"\xfe\xca\xfe\xca\x02\xb0\xad\x1b");
+ assert_eq!(digest.finalize(), 0x9508ac14);
+ }
+
+ #[test]
+ fn test_crc_from_regs() {
+ assert_eq!(TEST_REGS.crc32(), 0xf9616122);
+ }
+}
diff --git a/sw/host/opentitanlib/src/otp/alert_handler_regs.rs b/sw/host/opentitanlib/src/otp/alert_handler_regs.rs
new file mode 100644
index 0000000..f947327
--- /dev/null
+++ b/sw/host/opentitanlib/src/otp/alert_handler_regs.rs
@@ -0,0 +1,1263 @@
+/* automatically generated by rust-bindgen 0.60.1 */
+
+pub const ALERT_HANDLER_PARAM_N_ALERTS: u32 = 65;
+pub const ALERT_HANDLER_PARAM_N_LPG: u32 = 22;
+pub const ALERT_HANDLER_PARAM_N_LPG_WIDTH: u32 = 5;
+pub const ALERT_HANDLER_PARAM_ESC_CNT_DW: u32 = 32;
+pub const ALERT_HANDLER_PARAM_ACCU_CNT_DW: u32 = 16;
+pub const ALERT_HANDLER_PARAM_N_CLASSES: u32 = 4;
+pub const ALERT_HANDLER_PARAM_N_ESC_SEV: u32 = 4;
+pub const ALERT_HANDLER_PARAM_N_PHASES: u32 = 4;
+pub const ALERT_HANDLER_PARAM_N_LOC_ALERT: u32 = 7;
+pub const ALERT_HANDLER_PARAM_PING_CNT_DW: u32 = 16;
+pub const ALERT_HANDLER_PARAM_PHASE_DW: u32 = 2;
+pub const ALERT_HANDLER_PARAM_CLASS_DW: u32 = 2;
+pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_PINGFAIL: u32 = 0;
+pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_PINGFAIL: u32 = 1;
+pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_INTEGFAIL: u32 = 2;
+pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_INTEGFAIL: u32 = 3;
+pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_BUS_INTEGFAIL: u32 = 4;
+pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR: u32 = 5;
+pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR: u32 = 6;
+pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_LAST: u32 = 6;
+pub const ALERT_HANDLER_PARAM_REG_WIDTH: u32 = 32;
+pub const ALERT_HANDLER_INTR_COMMON_CLASSA_BIT: u32 = 0;
+pub const ALERT_HANDLER_INTR_COMMON_CLASSB_BIT: u32 = 1;
+pub const ALERT_HANDLER_INTR_COMMON_CLASSC_BIT: u32 = 2;
+pub const ALERT_HANDLER_INTR_COMMON_CLASSD_BIT: u32 = 3;
+pub const ALERT_HANDLER_INTR_STATE_REG_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_INTR_STATE_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_INTR_STATE_CLASSA_BIT: u32 = 0;
+pub const ALERT_HANDLER_INTR_STATE_CLASSB_BIT: u32 = 1;
+pub const ALERT_HANDLER_INTR_STATE_CLASSC_BIT: u32 = 2;
+pub const ALERT_HANDLER_INTR_STATE_CLASSD_BIT: u32 = 3;
+pub const ALERT_HANDLER_INTR_ENABLE_REG_OFFSET: u32 = 4;
+pub const ALERT_HANDLER_INTR_ENABLE_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_INTR_ENABLE_CLASSA_BIT: u32 = 0;
+pub const ALERT_HANDLER_INTR_ENABLE_CLASSB_BIT: u32 = 1;
+pub const ALERT_HANDLER_INTR_ENABLE_CLASSC_BIT: u32 = 2;
+pub const ALERT_HANDLER_INTR_ENABLE_CLASSD_BIT: u32 = 3;
+pub const ALERT_HANDLER_INTR_TEST_REG_OFFSET: u32 = 8;
+pub const ALERT_HANDLER_INTR_TEST_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_INTR_TEST_CLASSA_BIT: u32 = 0;
+pub const ALERT_HANDLER_INTR_TEST_CLASSB_BIT: u32 = 1;
+pub const ALERT_HANDLER_INTR_TEST_CLASSC_BIT: u32 = 2;
+pub const ALERT_HANDLER_INTR_TEST_CLASSD_BIT: u32 = 3;
+pub const ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET: u32 = 12;
+pub const ALERT_HANDLER_PING_TIMER_REGWEN_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_PING_TIMER_REGWEN_PING_TIMER_REGWEN_BIT: u32 = 0;
+pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 16;
+pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 256;
+pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK: u32 = 65535;
+pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET: u32 = 20;
+pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT: u32 = 65;
+pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET: u32 = 24;
+pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_0_EN_0_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_1_REG_OFFSET: u32 = 28;
+pub const ALERT_HANDLER_ALERT_REGWEN_1_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_1_EN_1_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_2_REG_OFFSET: u32 = 32;
+pub const ALERT_HANDLER_ALERT_REGWEN_2_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_2_EN_2_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_3_REG_OFFSET: u32 = 36;
+pub const ALERT_HANDLER_ALERT_REGWEN_3_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_3_EN_3_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_4_REG_OFFSET: u32 = 40;
+pub const ALERT_HANDLER_ALERT_REGWEN_4_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_4_EN_4_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_5_REG_OFFSET: u32 = 44;
+pub const ALERT_HANDLER_ALERT_REGWEN_5_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_5_EN_5_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_6_REG_OFFSET: u32 = 48;
+pub const ALERT_HANDLER_ALERT_REGWEN_6_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_6_EN_6_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_7_REG_OFFSET: u32 = 52;
+pub const ALERT_HANDLER_ALERT_REGWEN_7_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_7_EN_7_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_8_REG_OFFSET: u32 = 56;
+pub const ALERT_HANDLER_ALERT_REGWEN_8_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_8_EN_8_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_9_REG_OFFSET: u32 = 60;
+pub const ALERT_HANDLER_ALERT_REGWEN_9_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_9_EN_9_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_10_REG_OFFSET: u32 = 64;
+pub const ALERT_HANDLER_ALERT_REGWEN_10_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_10_EN_10_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_11_REG_OFFSET: u32 = 68;
+pub const ALERT_HANDLER_ALERT_REGWEN_11_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_11_EN_11_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_12_REG_OFFSET: u32 = 72;
+pub const ALERT_HANDLER_ALERT_REGWEN_12_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_12_EN_12_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_13_REG_OFFSET: u32 = 76;
+pub const ALERT_HANDLER_ALERT_REGWEN_13_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_13_EN_13_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_14_REG_OFFSET: u32 = 80;
+pub const ALERT_HANDLER_ALERT_REGWEN_14_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_14_EN_14_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_15_REG_OFFSET: u32 = 84;
+pub const ALERT_HANDLER_ALERT_REGWEN_15_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_15_EN_15_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_16_REG_OFFSET: u32 = 88;
+pub const ALERT_HANDLER_ALERT_REGWEN_16_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_16_EN_16_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_17_REG_OFFSET: u32 = 92;
+pub const ALERT_HANDLER_ALERT_REGWEN_17_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_17_EN_17_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_18_REG_OFFSET: u32 = 96;
+pub const ALERT_HANDLER_ALERT_REGWEN_18_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_18_EN_18_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_19_REG_OFFSET: u32 = 100;
+pub const ALERT_HANDLER_ALERT_REGWEN_19_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_19_EN_19_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_20_REG_OFFSET: u32 = 104;
+pub const ALERT_HANDLER_ALERT_REGWEN_20_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_20_EN_20_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_21_REG_OFFSET: u32 = 108;
+pub const ALERT_HANDLER_ALERT_REGWEN_21_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_21_EN_21_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_22_REG_OFFSET: u32 = 112;
+pub const ALERT_HANDLER_ALERT_REGWEN_22_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_22_EN_22_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_23_REG_OFFSET: u32 = 116;
+pub const ALERT_HANDLER_ALERT_REGWEN_23_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_23_EN_23_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_24_REG_OFFSET: u32 = 120;
+pub const ALERT_HANDLER_ALERT_REGWEN_24_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_24_EN_24_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_25_REG_OFFSET: u32 = 124;
+pub const ALERT_HANDLER_ALERT_REGWEN_25_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_25_EN_25_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_26_REG_OFFSET: u32 = 128;
+pub const ALERT_HANDLER_ALERT_REGWEN_26_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_26_EN_26_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_27_REG_OFFSET: u32 = 132;
+pub const ALERT_HANDLER_ALERT_REGWEN_27_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_27_EN_27_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_28_REG_OFFSET: u32 = 136;
+pub const ALERT_HANDLER_ALERT_REGWEN_28_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_28_EN_28_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_29_REG_OFFSET: u32 = 140;
+pub const ALERT_HANDLER_ALERT_REGWEN_29_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_29_EN_29_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_30_REG_OFFSET: u32 = 144;
+pub const ALERT_HANDLER_ALERT_REGWEN_30_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_30_EN_30_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_31_REG_OFFSET: u32 = 148;
+pub const ALERT_HANDLER_ALERT_REGWEN_31_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_31_EN_31_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_32_REG_OFFSET: u32 = 152;
+pub const ALERT_HANDLER_ALERT_REGWEN_32_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_32_EN_32_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_33_REG_OFFSET: u32 = 156;
+pub const ALERT_HANDLER_ALERT_REGWEN_33_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_33_EN_33_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_34_REG_OFFSET: u32 = 160;
+pub const ALERT_HANDLER_ALERT_REGWEN_34_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_34_EN_34_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_35_REG_OFFSET: u32 = 164;
+pub const ALERT_HANDLER_ALERT_REGWEN_35_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_35_EN_35_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_36_REG_OFFSET: u32 = 168;
+pub const ALERT_HANDLER_ALERT_REGWEN_36_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_36_EN_36_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_37_REG_OFFSET: u32 = 172;
+pub const ALERT_HANDLER_ALERT_REGWEN_37_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_37_EN_37_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_38_REG_OFFSET: u32 = 176;
+pub const ALERT_HANDLER_ALERT_REGWEN_38_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_38_EN_38_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_39_REG_OFFSET: u32 = 180;
+pub const ALERT_HANDLER_ALERT_REGWEN_39_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_39_EN_39_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_40_REG_OFFSET: u32 = 184;
+pub const ALERT_HANDLER_ALERT_REGWEN_40_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_40_EN_40_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_41_REG_OFFSET: u32 = 188;
+pub const ALERT_HANDLER_ALERT_REGWEN_41_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_41_EN_41_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_42_REG_OFFSET: u32 = 192;
+pub const ALERT_HANDLER_ALERT_REGWEN_42_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_42_EN_42_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_43_REG_OFFSET: u32 = 196;
+pub const ALERT_HANDLER_ALERT_REGWEN_43_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_43_EN_43_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_44_REG_OFFSET: u32 = 200;
+pub const ALERT_HANDLER_ALERT_REGWEN_44_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_44_EN_44_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_45_REG_OFFSET: u32 = 204;
+pub const ALERT_HANDLER_ALERT_REGWEN_45_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_45_EN_45_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_46_REG_OFFSET: u32 = 208;
+pub const ALERT_HANDLER_ALERT_REGWEN_46_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_46_EN_46_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_47_REG_OFFSET: u32 = 212;
+pub const ALERT_HANDLER_ALERT_REGWEN_47_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_47_EN_47_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_48_REG_OFFSET: u32 = 216;
+pub const ALERT_HANDLER_ALERT_REGWEN_48_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_48_EN_48_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_49_REG_OFFSET: u32 = 220;
+pub const ALERT_HANDLER_ALERT_REGWEN_49_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_49_EN_49_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_50_REG_OFFSET: u32 = 224;
+pub const ALERT_HANDLER_ALERT_REGWEN_50_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_50_EN_50_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_51_REG_OFFSET: u32 = 228;
+pub const ALERT_HANDLER_ALERT_REGWEN_51_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_51_EN_51_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_52_REG_OFFSET: u32 = 232;
+pub const ALERT_HANDLER_ALERT_REGWEN_52_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_52_EN_52_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_53_REG_OFFSET: u32 = 236;
+pub const ALERT_HANDLER_ALERT_REGWEN_53_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_53_EN_53_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_54_REG_OFFSET: u32 = 240;
+pub const ALERT_HANDLER_ALERT_REGWEN_54_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_54_EN_54_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_55_REG_OFFSET: u32 = 244;
+pub const ALERT_HANDLER_ALERT_REGWEN_55_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_55_EN_55_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_56_REG_OFFSET: u32 = 248;
+pub const ALERT_HANDLER_ALERT_REGWEN_56_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_56_EN_56_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_57_REG_OFFSET: u32 = 252;
+pub const ALERT_HANDLER_ALERT_REGWEN_57_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_57_EN_57_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_58_REG_OFFSET: u32 = 256;
+pub const ALERT_HANDLER_ALERT_REGWEN_58_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_58_EN_58_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_59_REG_OFFSET: u32 = 260;
+pub const ALERT_HANDLER_ALERT_REGWEN_59_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_59_EN_59_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_60_REG_OFFSET: u32 = 264;
+pub const ALERT_HANDLER_ALERT_REGWEN_60_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_60_EN_60_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_61_REG_OFFSET: u32 = 268;
+pub const ALERT_HANDLER_ALERT_REGWEN_61_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_61_EN_61_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_62_REG_OFFSET: u32 = 272;
+pub const ALERT_HANDLER_ALERT_REGWEN_62_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_62_EN_62_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_63_REG_OFFSET: u32 = 276;
+pub const ALERT_HANDLER_ALERT_REGWEN_63_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_63_EN_63_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_OFFSET: u32 = 280;
+pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_ALERT_REGWEN_64_EN_64_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_EN_A_FIELD_WIDTH: u32 = 1;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 65;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 284;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_EN_A_0_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 288;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_EN_A_1_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 292;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_EN_A_2_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 296;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_EN_A_3_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 300;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_EN_A_4_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 304;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_EN_A_5_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 308;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_EN_A_6_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET: u32 = 312;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_EN_A_7_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET: u32 = 316;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_EN_A_8_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET: u32 = 320;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_EN_A_9_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET: u32 = 324;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_EN_A_10_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET: u32 = 328;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_EN_A_11_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET: u32 = 332;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_EN_A_12_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET: u32 = 336;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_EN_A_13_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET: u32 = 340;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_EN_A_14_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET: u32 = 344;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_EN_A_15_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET: u32 = 348;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_EN_A_16_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET: u32 = 352;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_EN_A_17_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET: u32 = 356;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_EN_A_18_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET: u32 = 360;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_EN_A_19_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET: u32 = 364;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_EN_A_20_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET: u32 = 368;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_EN_A_21_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET: u32 = 372;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_EN_A_22_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET: u32 = 376;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_EN_A_23_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET: u32 = 380;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_EN_A_24_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET: u32 = 384;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_EN_A_25_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET: u32 = 388;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_EN_A_26_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET: u32 = 392;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_EN_A_27_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET: u32 = 396;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_EN_A_28_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET: u32 = 400;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_EN_A_29_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET: u32 = 404;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_EN_A_30_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET: u32 = 408;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_EN_A_31_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET: u32 = 412;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_EN_A_32_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET: u32 = 416;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_EN_A_33_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET: u32 = 420;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_EN_A_34_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET: u32 = 424;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_EN_A_35_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET: u32 = 428;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_EN_A_36_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET: u32 = 432;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_EN_A_37_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET: u32 = 436;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_EN_A_38_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET: u32 = 440;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_EN_A_39_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET: u32 = 444;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_EN_A_40_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET: u32 = 448;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_EN_A_41_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET: u32 = 452;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_EN_A_42_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET: u32 = 456;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_EN_A_43_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET: u32 = 460;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_EN_A_44_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET: u32 = 464;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_EN_A_45_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET: u32 = 468;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_EN_A_46_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET: u32 = 472;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_EN_A_47_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET: u32 = 476;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_EN_A_48_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET: u32 = 480;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_EN_A_49_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET: u32 = 484;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_EN_A_50_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET: u32 = 488;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_EN_A_51_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET: u32 = 492;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_EN_A_52_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET: u32 = 496;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_EN_A_53_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET: u32 = 500;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_EN_A_54_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET: u32 = 504;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_EN_A_55_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET: u32 = 508;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_EN_A_56_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET: u32 = 512;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_EN_A_57_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET: u32 = 516;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_EN_A_58_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET: u32 = 520;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_EN_A_59_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET: u32 = 524;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_EN_A_60_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET: u32 = 528;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_EN_A_61_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET: u32 = 532;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_EN_A_62_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET: u32 = 536;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_EN_A_63_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_OFFSET: u32 = 540;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_EN_A_64_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_CLASS_A_FIELD_WIDTH: u32 = 2;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 65;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 544;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB: u32 = 1;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC: u32 = 2;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 548;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 552;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 556;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 560;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 564;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 568;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET: u32 = 572;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET: u32 = 576;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET: u32 = 580;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET: u32 = 584;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET: u32 = 588;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET: u32 = 592;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET: u32 = 596;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET: u32 = 600;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET: u32 = 604;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET: u32 = 608;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET: u32 = 612;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET: u32 = 616;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET: u32 = 620;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET: u32 = 624;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET: u32 = 628;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET: u32 = 632;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET: u32 = 636;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET: u32 = 640;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET: u32 = 644;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET: u32 = 648;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET: u32 = 652;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET: u32 = 656;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET: u32 = 660;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET: u32 = 664;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET: u32 = 668;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET: u32 = 672;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET: u32 = 676;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET: u32 = 680;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET: u32 = 684;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET: u32 = 688;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET: u32 = 692;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET: u32 = 696;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET: u32 = 700;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET: u32 = 704;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET: u32 = 708;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET: u32 = 712;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET: u32 = 716;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET: u32 = 720;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET: u32 = 724;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET: u32 = 728;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET: u32 = 732;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET: u32 = 736;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET: u32 = 740;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET: u32 = 744;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET: u32 = 748;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET: u32 = 752;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET: u32 = 756;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET: u32 = 760;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET: u32 = 764;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET: u32 = 768;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET: u32 = 772;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET: u32 = 776;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET: u32 = 780;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET: u32 = 784;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET: u32 = 788;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET: u32 = 792;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET: u32 = 796;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_OFFSET: u32 = 800;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK: u32 = 3;
+pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_A_FIELD_WIDTH: u32 = 1;
+pub const ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT: u32 = 65;
+pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET: u32 = 804;
+pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_0_A_0_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET: u32 = 808;
+pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_1_A_1_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET: u32 = 812;
+pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_2_A_2_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET: u32 = 816;
+pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_3_A_3_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET: u32 = 820;
+pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_4_A_4_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET: u32 = 824;
+pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_5_A_5_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET: u32 = 828;
+pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_6_A_6_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET: u32 = 832;
+pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_7_A_7_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET: u32 = 836;
+pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_8_A_8_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET: u32 = 840;
+pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_9_A_9_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET: u32 = 844;
+pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_10_A_10_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET: u32 = 848;
+pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_11_A_11_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET: u32 = 852;
+pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_12_A_12_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET: u32 = 856;
+pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_13_A_13_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET: u32 = 860;
+pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_14_A_14_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET: u32 = 864;
+pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_15_A_15_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET: u32 = 868;
+pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_16_A_16_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET: u32 = 872;
+pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_17_A_17_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET: u32 = 876;
+pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_18_A_18_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET: u32 = 880;
+pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_19_A_19_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET: u32 = 884;
+pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_20_A_20_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET: u32 = 888;
+pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_21_A_21_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET: u32 = 892;
+pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_22_A_22_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET: u32 = 896;
+pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_23_A_23_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET: u32 = 900;
+pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_24_A_24_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET: u32 = 904;
+pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_25_A_25_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET: u32 = 908;
+pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_26_A_26_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET: u32 = 912;
+pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_27_A_27_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET: u32 = 916;
+pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_28_A_28_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET: u32 = 920;
+pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_29_A_29_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET: u32 = 924;
+pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_30_A_30_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET: u32 = 928;
+pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_31_A_31_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET: u32 = 932;
+pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_32_A_32_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET: u32 = 936;
+pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_33_A_33_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET: u32 = 940;
+pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_34_A_34_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET: u32 = 944;
+pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_35_A_35_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET: u32 = 948;
+pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_36_A_36_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET: u32 = 952;
+pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_37_A_37_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET: u32 = 956;
+pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_38_A_38_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET: u32 = 960;
+pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_39_A_39_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET: u32 = 964;
+pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_40_A_40_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET: u32 = 968;
+pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_41_A_41_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET: u32 = 972;
+pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_42_A_42_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET: u32 = 976;
+pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_43_A_43_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET: u32 = 980;
+pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_44_A_44_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET: u32 = 984;
+pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_45_A_45_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET: u32 = 988;
+pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_46_A_46_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET: u32 = 992;
+pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_47_A_47_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET: u32 = 996;
+pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_48_A_48_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET: u32 = 1000;
+pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_49_A_49_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET: u32 = 1004;
+pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_50_A_50_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET: u32 = 1008;
+pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_51_A_51_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET: u32 = 1012;
+pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_52_A_52_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET: u32 = 1016;
+pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_53_A_53_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET: u32 = 1020;
+pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_54_A_54_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET: u32 = 1024;
+pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_55_A_55_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET: u32 = 1028;
+pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_56_A_56_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET: u32 = 1032;
+pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_57_A_57_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET: u32 = 1036;
+pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_58_A_58_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET: u32 = 1040;
+pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_59_A_59_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET: u32 = 1044;
+pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_60_A_60_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET: u32 = 1048;
+pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_61_A_61_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET: u32 = 1052;
+pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_62_A_62_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET: u32 = 1056;
+pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_63_A_63_BIT: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_OFFSET: u32 = 1060;
+pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_ALERT_CAUSE_64_A_64_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT: u32 = 7;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET: u32 = 1064;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_EN_0_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET: u32 = 1068;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_EN_1_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET: u32 = 1072;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_EN_2_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET: u32 = 1076;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_EN_3_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET: u32 = 1080;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_EN_4_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET: u32 = 1084;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_EN_5_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET: u32 = 1088;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_EN_6_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_EN_LA_FIELD_WIDTH: u32 = 1;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 7;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 1092;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_EN_LA_0_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 1096;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_EN_LA_1_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 1100;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_EN_LA_2_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 1104;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_EN_LA_3_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 1108;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 1112;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_EN_LA_5_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 1116;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_EN_LA_6_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_CLASS_LA_FIELD_WIDTH: u32 = 2;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 7;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 1120;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK: u32 = 3;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB: u32 = 1;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC: u32 = 2;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD: u32 = 3;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 1124;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK: u32 = 3;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 1128;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK: u32 = 3;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 1132;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK: u32 = 3;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 1136;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK: u32 = 3;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 1140;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK: u32 = 3;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 1144;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK: u32 = 3;
+pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_LA_FIELD_WIDTH: u32 = 1;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_MULTIREG_COUNT: u32 = 7;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET: u32 = 1148;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_LA_0_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET: u32 = 1152;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_LA_1_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET: u32 = 1156;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_LA_2_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET: u32 = 1160;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_LA_3_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET: u32 = 1164;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_LA_4_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET: u32 = 1168;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_LA_5_BIT: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET: u32 = 1172;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_LA_6_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET: u32 = 1176;
+pub const ALERT_HANDLER_CLASSA_REGWEN_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_CLASSA_REGWEN_CLASSA_REGWEN_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET: u32 = 1180;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_RESVAL: u32 = 14652;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT: u32 = 1;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT: u32 = 2;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT: u32 = 3;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT: u32 = 4;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT: u32 = 5;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET: u32 = 6;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET: u32 = 8;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12;
+pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET: u32 = 1184;
+pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_CLASSA_CLR_REGWEN_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET: u32 = 1188;
+pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_CLASSA_CLR_SHADOWED_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET: u32 = 1192;
+pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK: u32 = 65535;
+pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1196;
+pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535;
+pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1200;
+pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1204;
+pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK:
+ u32 = 3;
+pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ;
+pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1208;
+pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1212;
+pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1216;
+pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1220;
+pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET: u32 = 1224;
+pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_STATE_REG_OFFSET: u32 = 1228;
+pub const ALERT_HANDLER_CLASSA_STATE_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK: u32 = 7;
+pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_IDLE: u32 = 0;
+pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TIMEOUT: u32 = 1;
+pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_FSMERROR: u32 = 2;
+pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TERMINAL: u32 = 3;
+pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE0: u32 = 4;
+pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE1: u32 = 5;
+pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE2: u32 = 6;
+pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE3: u32 = 7;
+pub const ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET: u32 = 1232;
+pub const ALERT_HANDLER_CLASSB_REGWEN_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_CLASSB_REGWEN_CLASSB_REGWEN_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET: u32 = 1236;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_RESVAL: u32 = 14652;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_LOCK_BIT: u32 = 1;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E0_BIT: u32 = 2;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E1_BIT: u32 = 3;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E2_BIT: u32 = 4;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E3_BIT: u32 = 5;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_OFFSET: u32 = 6;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_OFFSET: u32 = 8;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12;
+pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET: u32 = 1240;
+pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_CLASSB_CLR_REGWEN_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET: u32 = 1244;
+pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_CLASSB_CLR_SHADOWED_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET: u32 = 1248;
+pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK: u32 = 65535;
+pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1252;
+pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535;
+pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1256;
+pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1260;
+pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK:
+ u32 = 3;
+pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ;
+pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1264;
+pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1268;
+pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1272;
+pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1276;
+pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET: u32 = 1280;
+pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_STATE_REG_OFFSET: u32 = 1284;
+pub const ALERT_HANDLER_CLASSB_STATE_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK: u32 = 7;
+pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_IDLE: u32 = 0;
+pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TIMEOUT: u32 = 1;
+pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_FSMERROR: u32 = 2;
+pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TERMINAL: u32 = 3;
+pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE0: u32 = 4;
+pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE1: u32 = 5;
+pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE2: u32 = 6;
+pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE3: u32 = 7;
+pub const ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET: u32 = 1288;
+pub const ALERT_HANDLER_CLASSC_REGWEN_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_CLASSC_REGWEN_CLASSC_REGWEN_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET: u32 = 1292;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_RESVAL: u32 = 14652;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_LOCK_BIT: u32 = 1;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E0_BIT: u32 = 2;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E1_BIT: u32 = 3;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E2_BIT: u32 = 4;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E3_BIT: u32 = 5;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_OFFSET: u32 = 6;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_OFFSET: u32 = 8;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12;
+pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET: u32 = 1296;
+pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_CLASSC_CLR_REGWEN_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET: u32 = 1300;
+pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_CLASSC_CLR_SHADOWED_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET: u32 = 1304;
+pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK: u32 = 65535;
+pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1308;
+pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535;
+pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1312;
+pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1316;
+pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK:
+ u32 = 3;
+pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ;
+pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1320;
+pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1324;
+pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1328;
+pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1332;
+pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET: u32 = 1336;
+pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_STATE_REG_OFFSET: u32 = 1340;
+pub const ALERT_HANDLER_CLASSC_STATE_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK: u32 = 7;
+pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_IDLE: u32 = 0;
+pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TIMEOUT: u32 = 1;
+pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_FSMERROR: u32 = 2;
+pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TERMINAL: u32 = 3;
+pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE0: u32 = 4;
+pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE1: u32 = 5;
+pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE2: u32 = 6;
+pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE3: u32 = 7;
+pub const ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET: u32 = 1344;
+pub const ALERT_HANDLER_CLASSD_REGWEN_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_CLASSD_REGWEN_CLASSD_REGWEN_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET: u32 = 1348;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_RESVAL: u32 = 14652;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_LOCK_BIT: u32 = 1;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E0_BIT: u32 = 2;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E1_BIT: u32 = 3;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E2_BIT: u32 = 4;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E3_BIT: u32 = 5;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_OFFSET: u32 = 6;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_OFFSET: u32 = 8;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3;
+pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12;
+pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET: u32 = 1352;
+pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_RESVAL: u32 = 1;
+pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_CLASSD_CLR_REGWEN_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET: u32 = 1356;
+pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_CLASSD_CLR_SHADOWED_BIT: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET: u32 = 1360;
+pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK: u32 = 65535;
+pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1364;
+pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535;
+pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1368;
+pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1372;
+pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK:
+ u32 = 3;
+pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ;
+pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1376;
+pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1380;
+pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1384;
+pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1388;
+pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET: u32 = 1392;
+pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_STATE_REG_OFFSET: u32 = 1396;
+pub const ALERT_HANDLER_CLASSD_STATE_REG_RESVAL: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK: u32 = 7;
+pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_IDLE: u32 = 0;
+pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TIMEOUT: u32 = 1;
+pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_FSMERROR: u32 = 2;
+pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TERMINAL: u32 = 3;
+pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE0: u32 = 4;
+pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE1: u32 = 5;
+pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE2: u32 = 6;
+pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE3: u32 = 7;
diff --git a/sw/host/opentitanlib/src/otp/lc_state.rs b/sw/host/opentitanlib/src/otp/lc_state.rs
index 0f45c90..73e80a7 100644
--- a/sw/host/opentitanlib/src/otp/lc_state.rs
+++ b/sw/host/opentitanlib/src/otp/lc_state.rs
@@ -24,6 +24,15 @@
secded: LcSecded,
}
+#[repr(u32)]
+pub enum LcStateVal {
+ Test = 0xb2865fbb,
+ Dev = 0x0b5a75e0,
+ Prod = 0x65f2520f,
+ ProdEnd = 0x91b9b68a,
+ Rma = 0xcf8cfaab,
+}
+
impl LcSecded {
pub fn new(in_file: &Path) -> Result<LcSecded> {
let json_text = fs::read_to_string(in_file)?;
diff --git a/sw/host/opentitanlib/src/otp/mod.rs b/sw/host/opentitanlib/src/otp/mod.rs
index 54b5aa8..8dcf001 100644
--- a/sw/host/opentitanlib/src/otp/mod.rs
+++ b/sw/host/opentitanlib/src/otp/mod.rs
@@ -2,6 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
+pub mod alert_handler;
+pub mod alert_handler_regs;
pub mod lc_state;
pub mod otp;
pub mod otp_img;
diff --git a/sw/host/opentitanlib/src/otp/otp_img.rs b/sw/host/opentitanlib/src/otp/otp_img.rs
index 40ea6bf..69d4963 100644
--- a/sw/host/opentitanlib/src/otp/otp_img.rs
+++ b/sw/host/opentitanlib/src/otp/otp_img.rs
@@ -31,6 +31,24 @@
pub partitions: Vec<OtpImgPartition>,
}
+pub trait OtpRead {
+ fn read32(&self, name: &str) -> Result<u32> {
+ self.read32_offset(Some(name), 0)
+ }
+
+ fn read32_offset(&self, name: Option<&str>, offset: usize) -> Result<u32>;
+}
+
+impl OtpRead for OtpImg {
+ fn read32_offset(&self, name: Option<&str>, offset: usize) -> Result<u32> {
+ let mut start_offset = 0;
+ if let Some(name) = name {
+
+ }
+ Ok(0)
+ }
+}
+
impl OtpImgPartition {
pub fn get_item(&mut self, name: &str) -> Option<&mut OtpImgItem> {
self.items
