[doc] Fix make commands in {fpga,sw} user guides
* Point to make -C sw/device, since this is where the device Make
scaffolding lives.
* Add explicit make boot_rom command in fpga getting started
instructions. Some users are running into problems due to the fact
that the boot_rom file dependency is not checked at FPGA bitstream
build time and the instructions don't explicitly call out the make
command for boot_rom.
Keeping instructions in Make format as requested by
lowrisc/opentitan#733.
diff --git a/doc/ug/getting_started_fpga.md b/doc/ug/getting_started_fpga.md
index d0c8100..fa0e921 100644
--- a/doc/ug/getting_started_fpga.md
+++ b/doc/ug/getting_started_fpga.md
@@ -34,6 +34,7 @@
```console
$ . /tools/xilinx/Vivado/2018.3/settings64.sh
$ cd $REPO_TOP
+$ make -C sw/device SW_DIR=boot_rom clean all
$ fusesoc --cores-root . build lowrisc:systems:top_earlgrey_nexysvideo
```
diff --git a/doc/ug/getting_started_sw.md b/doc/ug/getting_started_sw.md
index fe3a52b..3001978 100644
--- a/doc/ug/getting_started_sw.md
+++ b/doc/ug/getting_started_sw.md
@@ -6,9 +6,12 @@
## Building software
+The following commands build the `boot_rom` and `hello_world` binaries:
+
```console
-$ cd $REPO_TOP/sw
-$ make SW_DIR=examples/hello_world CC=/tools/riscv/bin/riscv32-unknown-elf-gcc
+$ cd $REPO_TOP
+$ make -C sw/device SW_DIR=boot_rom clean all
+$ make -C sw/device SW_DIR=examples/hello_world clean all
```
The build process produces a variety of output files.
@@ -18,4 +21,4 @@
* `.dis`: the disassembled program
* `.vmem`: a Verilog memory file which can be read by `$readmemh()` in Verilog code
-Please see [SW build flow]("/sw/doc/sw_build_flow.md") for more details.
+Please see [SW build flow]("/sw/device/doc/sw_build_flow.md") for more details.
