commit 38ea8d8d22e2777971c2ee1fff16095c7913aee5
author Weicai Yang <weicai@google.com> Wed Oct 12 12:21:17 2022 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Wed Oct 12 15:36:04 2022 -0700
tree bac462647a7e61b1ba8c7270b3790889b5c29f4a
parent d72d18807b0d07ab821aa1f36e328a2cb22a9c73

[chip, dv] Increase reseed for chip_tl_errors

The Tl_errors_cgs_wrap occasionally dropped below 100% in nightly
Increasing reseed should solve it.

Signed-off-by: Weicai Yang <weicai@google.com>

hw/top_earlgrey/dv/chip_sim_cfg.hjson

diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index bc2f2ac..4a5f5ed 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -1195,7 +1195,7 @@
       uvm_test_seq: "{name}_common_vseq"
       run_opts: ["+run_tl_errors"]
       en_run_modes: ["stub_cpu_mode"]
-      reseed: 20
+      reseed: 30
     }
     {
       name: chip_prim_tl_access