[dv/lint] Add new DV TB to lint batch script
1. Add newly developed modules to Lint batch script.
This includes: OTP_CTRL, KeyMgr, prim_presence, prim_lfsr, prim_prince,
csrng
2. Add the lint template to uvmgen core file
3. Update current DV lint target. Delete the not used verilator and
ascentlint.
Signed-off-by: Cindy Chen <chencindy@google.com>
diff --git a/hw/ip/aes/dv/aes_sim.core b/hw/ip/aes/dv/aes_sim.core
index 0c23aed..514746f 100644
--- a/hw/ip/aes/dv/aes_sim.core
+++ b/hw/ip/aes/dv/aes_sim.core
@@ -27,13 +27,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
diff --git a/hw/ip/alert_handler/dv/alert_handler_generic_sim.core b/hw/ip/alert_handler/dv/alert_handler_generic_sim.core
index 66892f9..93fc8b5 100644
--- a/hw/ip/alert_handler/dv/alert_handler_generic_sim.core
+++ b/hw/ip/alert_handler/dv/alert_handler_generic_sim.core
@@ -37,13 +37,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
diff --git a/hw/ip/csrng/dv/csrng_sim.core b/hw/ip/csrng/dv/csrng_sim.core
index 4040462..7a46f86 100644
--- a/hw/ip/csrng/dv/csrng_sim.core
+++ b/hw/ip/csrng/dv/csrng_sim.core
@@ -18,9 +18,12 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
diff --git a/hw/ip/entropy_src/dv/entropy_src_sim.core b/hw/ip/entropy_src/dv/entropy_src_sim.core
index 4082a35..bb92ea2 100644
--- a/hw/ip/entropy_src/dv/entropy_src_sim.core
+++ b/hw/ip/entropy_src/dv/entropy_src_sim.core
@@ -27,13 +27,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
diff --git a/hw/ip/flash_ctrl/dv/flash_ctrl_sim.core b/hw/ip/flash_ctrl/dv/flash_ctrl_sim.core
index 64b468b..0cccaa0 100644
--- a/hw/ip/flash_ctrl/dv/flash_ctrl_sim.core
+++ b/hw/ip/flash_ctrl/dv/flash_ctrl_sim.core
@@ -33,13 +33,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
diff --git a/hw/ip/gpio/dv/gpio_sim.core b/hw/ip/gpio/dv/gpio_sim.core
index 00e0718..9320ff9 100644
--- a/hw/ip/gpio/dv/gpio_sim.core
+++ b/hw/ip/gpio/dv/gpio_sim.core
@@ -27,14 +27,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
-
diff --git a/hw/ip/hmac/dv/hmac_sim.core b/hw/ip/hmac/dv/hmac_sim.core
index b0b4eea..c913f02 100644
--- a/hw/ip/hmac/dv/hmac_sim.core
+++ b/hw/ip/hmac/dv/hmac_sim.core
@@ -27,14 +27,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
-
diff --git a/hw/ip/i2c/dv/i2c_sim.core b/hw/ip/i2c/dv/i2c_sim.core
index ac0d849..c27523d 100644
--- a/hw/ip/i2c/dv/i2c_sim.core
+++ b/hw/ip/i2c/dv/i2c_sim.core
@@ -27,13 +27,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
diff --git a/hw/ip/keymgr/dv/keymgr_sim.core b/hw/ip/keymgr/dv/keymgr_sim.core
index 435e97d..3bd7d8f 100644
--- a/hw/ip/keymgr/dv/keymgr_sim.core
+++ b/hw/ip/keymgr/dv/keymgr_sim.core
@@ -18,9 +18,12 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
diff --git a/hw/ip/otp_ctrl/dv/otp_ctrl_sim.core b/hw/ip/otp_ctrl/dv/otp_ctrl_sim.core
index ff11a54..438ab03 100644
--- a/hw/ip/otp_ctrl/dv/otp_ctrl_sim.core
+++ b/hw/ip/otp_ctrl/dv/otp_ctrl_sim.core
@@ -18,9 +18,12 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
diff --git a/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core b/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core
index 2555492..c70bd3b 100644
--- a/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core
+++ b/hw/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core
@@ -19,9 +19,12 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: prim_lfsr_tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
diff --git a/hw/ip/prim/dv/prim_present/prim_present_sim.core b/hw/ip/prim/dv/prim_present/prim_present_sim.core
index b4c5c50..0356b78 100644
--- a/hw/ip/prim/dv/prim_present/prim_present_sim.core
+++ b/hw/ip/prim/dv/prim_present/prim_present_sim.core
@@ -18,9 +18,12 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: prim_present_tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
diff --git a/hw/ip/prim/dv/prim_prince/prim_prince_sim.core b/hw/ip/prim/dv/prim_prince/prim_prince_sim.core
index 120fee9..02c6e82 100644
--- a/hw/ip/prim/dv/prim_prince/prim_prince_sim.core
+++ b/hw/ip/prim/dv/prim_prince/prim_prince_sim.core
@@ -20,9 +20,12 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: prim_prince_tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
diff --git a/hw/ip/rv_timer/dv/rv_timer_sim.core b/hw/ip/rv_timer/dv/rv_timer_sim.core
index 0dfd67a..96b7001 100644
--- a/hw/ip/rv_timer/dv/rv_timer_sim.core
+++ b/hw/ip/rv_timer/dv/rv_timer_sim.core
@@ -27,14 +27,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
-
diff --git a/hw/ip/spi_device/dv/spi_device_sim.core b/hw/ip/spi_device/dv/spi_device_sim.core
index 5bebebc..54f39e5 100644
--- a/hw/ip/spi_device/dv/spi_device_sim.core
+++ b/hw/ip/spi_device/dv/spi_device_sim.core
@@ -27,13 +27,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
diff --git a/hw/ip/uart/dv/uart_sim.core b/hw/ip/uart/dv/uart_sim.core
index 19919ca..a279900 100644
--- a/hw/ip/uart/dv/uart_sim.core
+++ b/hw/ip/uart/dv/uart_sim.core
@@ -27,13 +27,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
diff --git a/hw/ip/usbdev/dv/usbdev_sim.core b/hw/ip/usbdev/dv/usbdev_sim.core
index 48dd2f5..8ddac77 100644
--- a/hw/ip/usbdev/dv/usbdev_sim.core
+++ b/hw/ip/usbdev/dv/usbdev_sim.core
@@ -27,13 +27,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
diff --git a/hw/top_earlgrey/dv/chip_sim.core b/hw/top_earlgrey/dv/chip_sim.core
index 07f994e..32a2cd6 100644
--- a/hw/top_earlgrey/dv/chip_sim.core
+++ b/hw/top_earlgrey/dv/chip_sim.core
@@ -38,14 +38,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
-
diff --git a/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_sim.core b/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_sim.core
index 76dd863..3e1ee9c 100644
--- a/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_sim.core
+++ b/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_sim.core
@@ -37,14 +37,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
-
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim.core b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim.core
index 3a266ad..23b4aab 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim.core
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_sim.core
@@ -28,14 +28,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
-
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim.core b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim.core
index 291faa8..c66744b 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim.core
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_sim.core
@@ -28,14 +28,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
-
diff --git a/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson
index 852eb6f..234e22e 100644
--- a/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson
+++ b/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson
@@ -26,6 +26,11 @@
import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
rel_path: "hw/top_earlgrey/ip/alert_handler/dv/lint/{tool}"
},
+ { name: csrng
+ fusesoc_core: lowrisc:dv:csrng_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/csrng/dv/lint/{tool}"
+ },
{ name: entropy_src
fusesoc_core: lowrisc:dv:entropy_src_sim
import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
@@ -51,6 +56,31 @@
import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
rel_path: "hw/ip/i2c/dv/lint/{tool}"
},
+ { name: keymgr
+ fusesoc_core: lowrisc:dv:keymgr_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/keymgr/dv/lint/{tool}"
+ },
+ { name: otp_ctrl
+ fusesoc_core: lowrisc:dv:otp_ctrl_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/otp_ctrl/dv/lint/{tool}"
+ },
+ { name: prim_lfsr
+ fusesoc_core: lowrisc:dv:prim_lfsr_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/dv/prim_lfsr/lint/{tool}"
+ },
+ { name: prim_present
+ fusesoc_core: lowrisc:dv:prim_present_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/dv/prim_present/lint/{tool}"
+ },
+ { name: prim_prince
+ fusesoc_core: lowrisc:dv:prim_prince_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/prim/dv/prim_prince/lint/{tool}"
+ },
{ name: rv_timer
fusesoc_core: lowrisc:dv:rv_timer_sim
import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
diff --git a/util/tlgen/xbar.sim.core.tpl b/util/tlgen/xbar.sim.core.tpl
index 3e4c389..98be033 100644
--- a/util/tlgen/xbar.sim.core.tpl
+++ b/util/tlgen/xbar.sim.core.tpl
@@ -28,14 +28,3 @@
lint:
<<: *sim_target
- default_tool: verilator
- tools:
- ascentlint:
- ascentlint_options:
- - "-wait_license"
- - "-stop_on_error"
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
-
diff --git a/util/uvmdvgen/sim.core.tpl b/util/uvmdvgen/sim.core.tpl
index 76c29c8..5cc9142 100644
--- a/util/uvmdvgen/sim.core.tpl
+++ b/util/uvmdvgen/sim.core.tpl
@@ -18,9 +18,22 @@
file_type: systemVerilogSource
targets:
- sim:
+ sim: &sim_target
toplevel: tb
filesets:
- files_rtl
- files_dv
default_tool: vcs
+
+ lint:
+ <<: *sim_target
+ default_tool: verilator
+ tools:
+ ascentlint:
+ ascentlint_options:
+ - "-wait_license"
+ - "-stop_on_error"
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
