| commit | 382f712428b28a8bf5b38af9d5366a4b5ddd8c13 | [log] [tgz] |
|---|---|---|
| author | Weicai Yang <weicai@google.com> | Tue Dec 07 14:51:08 2021 -0800 |
| committer | weicaiyang <49293026+weicaiyang@users.noreply.github.com> | Wed Dec 08 16:04:06 2021 -0800 |
| tree | 46a3f19dc374fa84d80e8d44d59053f7c86bab00 | |
| parent | 0cedb50033fcc5482628191df4c7a98253a42e19 [diff] |
[sram/dv] Add generic mem_bkdr_scb and enable it in sram scb The current sram mem scb can't handle a few corner cases like b2b write after write, write after read and read after partial write. Instead of hacking it to support them, I created a generic mem_bkdr_scb to compare read/write value with expected value from backdoor. For details, refer to README or [slides](https://docs.google.com/presentation/d/1jvE5RmzlL7eZLwgmQJQUlbnr3beb1KXypzxk9LblIyg/edit#slide=id.p) 2 more PRs will come soon to address 1. remove design hack for partial write 2. clean up the old sram mem backdoor check. Keep it for now as it may help to debug the new checks Signed-off-by: Weicai Yang <weicai@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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