commit 382709a4fb915c894bafaee9e1d3119d82633e7a
author Rupert Swarbrick <rswarbrick@lowrisc.org> Fri May 13 14:52:06 2022 +0100
committer Rupert Swarbrick <rswarbrick@gmail.com> Mon May 16 14:41:01 2022 +0100
tree 66daec7c559b2cbc0693ac94be4990b87ea4451c
parent cc9ff490d798a95d2d81fd5b3e9027445eb60563

[otbn,dv] Add missing explicit enum casts in otbn_scoreboard.sv

Missing them causes a *W,ENUMERR warning from Xcelium.

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>

hw/ip/otbn/dv/uvm/env/otbn_scoreboard.sv

diff --git a/hw/ip/otbn/dv/uvm/env/otbn_scoreboard.sv b/hw/ip/otbn/dv/uvm/env/otbn_scoreboard.sv
index 6d14116..45af266 100644
--- a/hw/ip/otbn/dv/uvm/env/otbn_scoreboard.sv
+++ b/hw/ip/otbn/dv/uvm/env/otbn_scoreboard.sv
@@ -140,7 +140,7 @@
     operational_state_e  state;
     otbn_exp_read_data_t exp_read_data = '{upd: 1'b0, chk: 'x, val: 'x};
 
-    state = get_operational_state(model_status);
+    state = get_operational_state(status_e'(model_status));
 
     aligned_addr = ral.get_word_aligned_addr(item.a_addr);
     masked_addr  = aligned_addr & ral.get_addr_mask();
@@ -293,7 +293,7 @@
     // Track coverage for read accesses through the bus to external CSRs.
     if (cfg.en_cov) begin
       cov.on_ext_csr_access(csr, otbn_env_pkg::AccessSoftwareRead, item.d_data,
-                            get_operational_state(model_status));
+                            get_operational_state(status_e'(model_status)));
     end
 
     // Look up the expected read data for item and then clear it (to get a quick error if something
@@ -358,7 +358,7 @@
               UVM_HIGH);
 
     if (cfg.en_cov) begin
-      cov.on_mem_write(mem, offset, item.a_data, get_operational_state(model_status));
+      cov.on_mem_write(mem, offset, item.a_data, get_operational_state(status_e'(model_status)));
     end
 
     // Predict the resulting value of LOAD_CHECKSUM