[top] generate top level files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 5b3b2c9..397e00a 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -22,36 +22,55 @@
name: main
aon: no
freq: "100000000"
+ derived: no
+ params: {}
}
{
name: io
aon: no
freq: "100000000"
+ derived: no
+ params: {}
}
{
name: usb
aon: no
freq: "48000000"
+ derived: no
+ params: {}
}
{
name: aon
aon: yes
freq: "200000"
+ derived: no
+ params: {}
+ }
+ ]
+ derived_srcs:
+ [
+ {
+ name: io_div2
+ aon: no
+ div: 2
+ src: io
+ freq: "50000000"
}
]
groups:
[
{
name: powerup
- src: ext
+ src: top
sw_cg: no
unique: no
clocks:
{
- clk_io_i: io
- clk_aon_i: aon
- clk_i: main
- clk_usb_i: usb
+ clk_io_powerup: io
+ clk_aon_powerup: aon
+ clk_main_powerup: main
+ clk_usb_powerup: usb
+ clk_io_div2_powerup: io_div2
}
}
{
@@ -146,6 +165,12 @@
clk: io
}
{
+ name: por_io_div2
+ type: top
+ root: por_aon
+ clk: io_div2
+ }
+ {
name: por_usb
type: top
root: por_aon
@@ -167,19 +192,19 @@
name: sys_io
type: top
root: sys
- clk: io
+ clk: io_div2
}
{
name: sys_aon
type: top
root: sys
- clk: io
+ clk: io_div2
}
{
name: spi_device
type: top
root: sys
- clk: io
+ clk: io_div2
sw: 1
}
{
@@ -1004,8 +1029,8 @@
generated: "true"
clock_connections:
{
- clk_i: clk_io_i
- clk_slow_i: clk_aon_i
+ clk_i: clkmgr_clocks.clk_io_powerup
+ clk_slow_i: clkmgr_clocks.clk_aon_powerup
}
size: 0x1000
bus_device: tlul
@@ -1137,6 +1162,7 @@
clk_main_i: main
clk_io_i: io
clk_usb_i: usb
+ clk_io_div2_i: io_div2
}
clock_group: powerup
reset_connections:
@@ -1146,11 +1172,12 @@
base_addr: 0x400B0000
clock_connections:
{
- clk_i: clk_io_i
- clk_aon_i: clk_aon_i
- clk_main_i: clk_i
- clk_io_i: clk_io_i
- clk_usb_i: clk_usb_i
+ clk_i: clkmgr_clocks.clk_io_powerup
+ clk_aon_i: clkmgr_clocks.clk_aon_powerup
+ clk_main_i: clkmgr_clocks.clk_main_powerup
+ clk_io_i: clkmgr_clocks.clk_io_powerup
+ clk_usb_i: clkmgr_clocks.clk_usb_powerup
+ clk_io_div2_i: clkmgr_clocks.clk_io_div2_powerup
}
size: 0x1000
bus_device: tlul
@@ -1224,10 +1251,6 @@
clock_srcs:
{
clk_i: io
- clk_main_i: main
- clk_io_i: io
- clk_usb_i: usb
- clk_aon_i: aon
}
clock_group: powerup
reset_connections:
@@ -1236,16 +1259,13 @@
rst_main_ni: por
rst_io_ni: por_io
rst_usb_ni: por_usb
+ rst_io_div2_ni: por_io_div2
}
base_addr: 0x400C0000
generated: "true"
clock_connections:
{
- clk_i: clk_io_i
- clk_main_i: clk_i
- clk_io_i: clk_io_i
- clk_usb_i: clk_usb_i
- clk_aon_i: clk_aon_i
+ clk_i: clkmgr_clocks.clk_io_powerup
}
size: 0x1000
bus_device: tlul
@@ -1272,6 +1292,50 @@
index: -1
}
{
+ struct: logic
+ type: uni
+ name: clk_main
+ act: rcv
+ package: ""
+ inst_name: clkmgr
+ width: 1
+ top_signame: clkmgr_clk_main
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: clk_io
+ act: rcv
+ package: ""
+ inst_name: clkmgr
+ width: 1
+ top_signame: clkmgr_clk_io
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: clk_usb
+ act: rcv
+ package: ""
+ inst_name: clkmgr
+ width: 1
+ top_signame: clkmgr_clk_usb
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: clk_aon
+ act: rcv
+ package: ""
+ inst_name: clkmgr
+ width: 1
+ top_signame: clkmgr_clk_aon
+ index: -1
+ }
+ {
struct: pwr_clk
type: req_rsp
name: pwr
@@ -1754,6 +1818,7 @@
]
wakeup_list: []
scan: "false"
+ scan_reset: "false"
inter_signal_list:
[
{
@@ -1891,7 +1956,13 @@
pwrmgr.pwr_cpu
clkmgr.clocks
]
- external: []
+ external:
+ [
+ clkmgr.clk_main
+ clkmgr.clk_io
+ clkmgr.clk_usb
+ clkmgr.clk_aon
+ ]
}
xbar:
[
@@ -3464,6 +3535,7 @@
por_aon: rstmgr_resets.rst_por_aon_n
por: rstmgr_resets.rst_por_n
por_io: rstmgr_resets.rst_por_io_n
+ por_io_div2: rstmgr_resets.rst_por_io_div2_n
por_usb: rstmgr_resets.rst_por_usb_n
lc: rstmgr_resets.rst_lc_n
sys: rstmgr_resets.rst_sys_n
@@ -3674,6 +3746,50 @@
index: -1
}
{
+ struct: logic
+ type: uni
+ name: clk_main
+ act: rcv
+ package: ""
+ inst_name: clkmgr
+ width: 1
+ top_signame: clkmgr_clk_main
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: clk_io
+ act: rcv
+ package: ""
+ inst_name: clkmgr
+ width: 1
+ top_signame: clkmgr_clk_io
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: clk_usb
+ act: rcv
+ package: ""
+ inst_name: clkmgr
+ width: 1
+ top_signame: clkmgr_clk_usb
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: clk_aon
+ act: rcv
+ package: ""
+ inst_name: clkmgr
+ width: 1
+ top_signame: clkmgr_clk_aon
+ index: -1
+ }
+ {
struct: pwr_clk
type: req_rsp
name: pwr
@@ -3743,7 +3859,41 @@
index: -1
}
]
- external: []
+ external:
+ [
+ {
+ package: ""
+ struct: logic
+ signame: clkmgr_clk_main
+ width: 1
+ type: uni
+ direction: in
+ }
+ {
+ package: ""
+ struct: logic
+ signame: clkmgr_clk_io
+ width: 1
+ type: uni
+ direction: in
+ }
+ {
+ package: ""
+ struct: logic
+ signame: clkmgr_clk_usb
+ width: 1
+ type: uni
+ direction: in
+ }
+ {
+ package: ""
+ struct: logic
+ signame: clkmgr_clk_aon
+ width: 1
+ type: uni
+ direction: in
+ }
+ ]
definitions:
[
{
diff --git a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
index a90b1af..28efddf 100644
--- a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
+++ b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
@@ -17,17 +17,13 @@
{
name: "CLKMGR",
clock_primary: "clk_i",
- other_clock_list: [
- "clk_main_i",
- "clk_io_i",
- "clk_usb_i",
- "clk_aon_i",
- ],
+ other_clock_list: [],
reset_primary: "rst_ni",
other_reset_list: [
"rst_main_ni"
"rst_io_ni"
"rst_usb_ni"
+ "rst_io_div2_ni"
]
bus_device: "tlul",
regwidth: "32",
@@ -40,7 +36,6 @@
},
],
- // Define rstmgr struct package
inter_signal_list: [
{ struct: "clkmgr_out",
type: "uni",
@@ -49,6 +44,32 @@
package: "clkmgr_pkg",
},
+ // All clock inputs
+ { struct: "logic",
+ type: "uni",
+ name: "clk_main",
+ act: "rcv",
+ package: "",
+ },
+ { struct: "logic",
+ type: "uni",
+ name: "clk_io",
+ act: "rcv",
+ package: "",
+ },
+ { struct: "logic",
+ type: "uni",
+ name: "clk_usb",
+ act: "rcv",
+ package: "",
+ },
+ { struct: "logic",
+ type: "uni",
+ name: "clk_aon",
+ act: "rcv",
+ package: "",
+ },
+
{ struct: "pwr_clk",
type: "req_rsp",
name: "pwr",
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
index debbd00..bfe0792 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -30,6 +30,10 @@
input rst_usb_ni,
input clk_aon_i,
+ // Resets for derived clocks
+ // clocks are derived locally
+ input rst_io_div2_ni,
+
// Bus Interface
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
@@ -66,6 +70,14 @@
.devmode_i(1'b1)
);
+ ////////////////////////////////////////////////////
+ // Divided clocks
+ ////////////////////////////////////////////////////
+ logic clk_io_div2_i;
+
+ assign clk_io_div2_i = clk_io_i;
+
+
////////////////////////////////////////////////////
// Feed through clocks
@@ -73,8 +85,11 @@
// completely untouched. The only reason they are here is for easier
// bundling management purposes through clocks_o
////////////////////////////////////////////////////
- assign clocks_o.clk_aon_i = clk_aon_i;
-
+ assign clocks_o.clk_io_powerup = clk_io_i;
+ assign clocks_o.clk_aon_powerup = clk_aon_i;
+ assign clocks_o.clk_main_powerup = clk_main_i;
+ assign clocks_o.clk_usb_powerup = clk_usb_i;
+ assign clocks_o.clk_io_div2_powerup = clk_io_div2_i;
////////////////////////////////////////////////////
// Root gating
@@ -88,6 +103,8 @@
logic clk_io_en;
logic clk_usb_root;
logic clk_usb_en;
+ logic clk_io_div2_root;
+ logic clk_io_div2_en;
prim_clock_gating_sync i_main_cg (
.clk_i(clk_main_i),
@@ -113,12 +130,21 @@
.en_o(clk_usb_en),
.clk_o(clk_usb_root)
);
+ prim_clock_gating_sync i_io_div2_cg (
+ .clk_i(clk_io_div2_i),
+ .rst_ni(rst_io_div2_ni),
+ .test_en_i(dft_i.test_en),
+ .async_en_i(pwr_i.ip_clk_en),
+ .en_o(clk_io_div2_en),
+ .clk_o(clk_io_div2_root)
+ );
// an async OR of all the synchronized enables
assign async_roots_en =
clk_main_en |
clk_io_en |
- clk_usb_en;
+ clk_usb_en |
+ clk_io_div2_en;
// Sync the OR back into clkmgr domain for feedback to pwrmgr.
// Since the signal is combo / converged on the other side, de-bounce
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
index d90a27f..f47427b 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
@@ -17,7 +17,11 @@
};
typedef struct packed {
- logic clk_aon_i;
+ logic clk_io_powerup;
+ logic clk_aon_powerup;
+ logic clk_main_powerup;
+ logic clk_usb_powerup;
+ logic clk_io_div2_powerup;
logic clk_main_aes;
logic clk_main_hmac;
logic clk_main_otbn;
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 4e0fc08..c23739f 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -6,19 +6,9 @@
parameter bit IbexPipeLine = 0,
parameter BootRomInitFile = ""
) (
- // Clock and Reset
- input clk_i,
+ // Reset, clocks defined as part of intermodule
input rst_ni,
- // Fixed io clock
- input clk_io_i,
-
- // USB clock
- input clk_usb_i,
-
- // aon clock
- input clk_aon_i,
-
// JTAG interface
input jtag_tck_i,
input jtag_tms_i,
@@ -41,6 +31,12 @@
output logic[padctrl_reg_pkg::NDioPads-1:0]
[padctrl_reg_pkg::AttrDw-1:0] dio_attr_o,
+
+ // Inter-module Signal External type
+ input logic clkmgr_clk_main,
+ input logic clkmgr_clk_io,
+ input logic clkmgr_clk_usb,
+ input logic clkmgr_clk_aon,
input scan_rst_ni, // reset used for test mode
input scanmode_i // 1 for Scan
);
@@ -758,8 +754,8 @@
.pwr_cpu_i(pwrmgr_pwr_cpu),
.wakeups_i(pwrmgr_wakeups),
.rstreqs_i('0),
- .clk_i (clk_io_i),
- .clk_slow_i (clk_aon_i),
+ .clk_i (clkmgr_clocks.clk_io_powerup),
+ .clk_slow_i (clkmgr_clocks.clk_aon_powerup),
.rst_ni (rstmgr_resets.rst_por_n),
.rst_slow_ni (rstmgr_resets.rst_por_aon_n)
);
@@ -777,11 +773,12 @@
.peri_i(rstmgr_pkg::RSTMGR_PERI_DEFAULT),
.scanmode_i (scanmode_i),
.scan_rst_ni (scan_rst_ni),
- .clk_i (clk_io_i),
- .clk_aon_i (clk_aon_i),
- .clk_main_i (clk_i),
- .clk_io_i (clk_io_i),
- .clk_usb_i (clk_usb_i),
+ .clk_i (clkmgr_clocks.clk_io_powerup),
+ .clk_aon_i (clkmgr_clocks.clk_aon_powerup),
+ .clk_main_i (clkmgr_clocks.clk_main_powerup),
+ .clk_io_i (clkmgr_clocks.clk_io_powerup),
+ .clk_usb_i (clkmgr_clocks.clk_usb_powerup),
+ .clk_io_div2_i (clkmgr_clocks.clk_io_div2_powerup),
.rst_ni (rst_ni)
);
@@ -791,19 +788,20 @@
// Inter-module signals
.clocks_o(clkmgr_clocks),
+ .clk_main_i(clkmgr_clk_main),
+ .clk_io_i(clkmgr_clk_io),
+ .clk_usb_i(clkmgr_clk_usb),
+ .clk_aon_i(clkmgr_clk_aon),
.pwr_i(pwrmgr_pwr_clk_req),
.pwr_o(pwrmgr_pwr_clk_rsp),
.dft_i(clkmgr_pkg::CLK_DFT_DEFAULT),
.status_i(clkmgr_pkg::CLK_HINT_STATUS_DEFAULT),
- .clk_i (clk_io_i),
- .clk_main_i (clk_i),
- .clk_io_i (clk_io_i),
- .clk_usb_i (clk_usb_i),
- .clk_aon_i (clk_aon_i),
+ .clk_i (clkmgr_clocks.clk_io_powerup),
.rst_ni (rstmgr_resets.rst_por_io_n),
.rst_main_ni (rstmgr_resets.rst_por_n),
.rst_io_ni (rstmgr_resets.rst_por_io_n),
- .rst_usb_ni (rstmgr_resets.rst_por_usb_n)
+ .rst_usb_ni (rstmgr_resets.rst_por_usb_n),
+ .rst_io_div2_ni (rstmgr_resets.rst_por_io_div2_n)
);
nmi_gen u_nmi_gen (
@@ -893,7 +891,6 @@
// Inter-module signals
.idle_o(),
-
.clk_i (clkmgr_clocks.clk_main_otbn),
.rst_ni (rstmgr_resets.rst_sys_n)
);
@@ -1091,6 +1088,6 @@
assign cio_usbdev_dn_p2d = dio_p2d[0]; // DIO0
// make sure scanmode_i is never X (including during reset)
- `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_i, 0)
+ `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clkmgr_clk_main, 0)
endmodule
