Remove abandoned auto-generated files
Once upon a time, two files in our source tree were autogenerated.
Unfortunately, the wizzard generating those files has lost interest in
them due to a configuration change. Let's clean up the forest and remove
them.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv
deleted file mode 100644
index 5a66857..0000000
--- a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv
+++ /dev/null
@@ -1,1802 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Register Top module auto-generated by `reggen`
-
-`include "prim_assert.sv"
-
-module otp_ctrl_reg_top (
- input clk_i,
- input rst_ni,
-
- input tlul_pkg::tl_h2d_t tl_i,
- output tlul_pkg::tl_d2h_t tl_o,
-
- // Output port for window
- output tlul_pkg::tl_h2d_t tl_win_o [2],
- input tlul_pkg::tl_d2h_t tl_win_i [2],
-
- // To HW
- output otp_ctrl_reg_pkg::otp_ctrl_reg2hw_t reg2hw, // Write
- input otp_ctrl_reg_pkg::otp_ctrl_hw2reg_t hw2reg, // Read
-
- // Integrity check errors
- output logic intg_err_o,
-
- // Config
- input devmode_i // If 1, explicit error return for unmapped register access
-);
-
- import otp_ctrl_reg_pkg::* ;
-
- localparam int AW = 14;
- localparam int DW = 32;
- localparam int DBW = DW/8; // Byte Width
-
- // register signals
- logic reg_we;
- logic reg_re;
- logic [AW-1:0] reg_addr;
- logic [DW-1:0] reg_wdata;
- logic [DBW-1:0] reg_be;
- logic [DW-1:0] reg_rdata;
- logic reg_error;
-
- logic addrmiss, wr_err;
-
- logic [DW-1:0] reg_rdata_next;
-
- tlul_pkg::tl_h2d_t tl_reg_h2d;
- tlul_pkg::tl_d2h_t tl_reg_d2h;
-
- // incoming payload check
- logic intg_err;
- tlul_cmd_intg_chk u_chk (
- .tl_i,
- .err_o(intg_err)
- );
-
- logic intg_err_q;
- always_ff @(posedge clk_i or negedge rst_ni) begin
- if (!rst_ni) begin
- intg_err_q <= '0;
- end else if (intg_err) begin
- intg_err_q <= 1'b1;
- end
- end
-
- // integrity error output is permanent and should be used for alert generation
- // register errors are transactional
- assign intg_err_o = intg_err_q | intg_err;
-
- // outgoing integrity generation
- tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_rsp_intg_gen #(
- .EnableRspIntgGen(1),
- .EnableDataIntgGen(1)
- ) u_rsp_intg_gen (
- .tl_i(tl_o_pre),
- .tl_o
- );
-
- tlul_pkg::tl_h2d_t tl_socket_h2d [3];
- tlul_pkg::tl_d2h_t tl_socket_d2h [3];
-
- logic [1:0] reg_steer;
-
- // socket_1n connection
- assign tl_reg_h2d = tl_socket_h2d[2];
- assign tl_socket_d2h[2] = tl_reg_d2h;
-
- assign tl_win_o[0] = tl_socket_h2d[0];
- assign tl_socket_d2h[0] = tl_win_i[0];
- assign tl_win_o[1] = tl_socket_h2d[1];
- assign tl_socket_d2h[1] = tl_win_i[1];
-
- // Create Socket_1n
- tlul_socket_1n #(
- .N (3),
- .HReqPass (1'b1),
- .HRspPass (1'b1),
- .DReqPass ({3{1'b1}}),
- .DRspPass ({3{1'b1}}),
- .HReqDepth (4'h0),
- .HRspDepth (4'h0),
- .DReqDepth ({3{4'h0}}),
- .DRspDepth ({3{4'h0}})
- ) u_socket (
- .clk_i,
- .rst_ni,
- .tl_h_i (tl_i),
- .tl_h_o (tl_o_pre),
- .tl_d_o (tl_socket_h2d),
- .tl_d_i (tl_socket_d2h),
- .dev_select_i (reg_steer)
- );
-
- // Create steering logic
- always_comb begin
- reg_steer = 2; // Default set to register
-
- // TODO: Can below codes be unique case () inside ?
- if (tl_i.a_address[AW-1:0] >= 4096 && tl_i.a_address[AW-1:0] < 6144) begin
- reg_steer = 0;
- end
- if (tl_i.a_address[AW-1:0] >= 8192 && tl_i.a_address[AW-1:0] < 8256) begin
- reg_steer = 1;
- end
- if (intg_err) begin
- reg_steer = 2;
- end
- end
-
- tlul_adapter_reg #(
- .RegAw(AW),
- .RegDw(DW),
- .EnableDataIntgGen(0)
- ) u_reg_if (
- .clk_i,
- .rst_ni,
-
- .tl_i (tl_reg_h2d),
- .tl_o (tl_reg_d2h),
-
- .we_o (reg_we),
- .re_o (reg_re),
- .addr_o (reg_addr),
- .wdata_o (reg_wdata),
- .be_o (reg_be),
- .rdata_i (reg_rdata),
- .error_i (reg_error)
- );
-
- assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
-
- // Define SW related signals
- // Format: <reg>_<field>_{wd|we|qs}
- // or <reg>_{wd|we|qs} if field == 1 or 0
- logic intr_state_we;
- logic intr_state_otp_operation_done_qs;
- logic intr_state_otp_operation_done_wd;
- logic intr_state_otp_error_qs;
- logic intr_state_otp_error_wd;
- logic intr_enable_we;
- logic intr_enable_otp_operation_done_qs;
- logic intr_enable_otp_operation_done_wd;
- logic intr_enable_otp_error_qs;
- logic intr_enable_otp_error_wd;
- logic intr_test_we;
- logic intr_test_otp_operation_done_wd;
- logic intr_test_otp_error_wd;
- logic alert_test_we;
- logic alert_test_fatal_macro_error_wd;
- logic alert_test_fatal_check_error_wd;
- logic alert_test_fatal_bus_integ_error_wd;
- logic status_re;
- logic status_creator_sw_cfg_error_qs;
- logic status_owner_sw_cfg_error_qs;
- logic status_hw_cfg_error_qs;
- logic status_secret0_error_qs;
- logic status_secret1_error_qs;
- logic status_secret2_error_qs;
- logic status_life_cycle_error_qs;
- logic status_dai_error_qs;
- logic status_lci_error_qs;
- logic status_timeout_error_qs;
- logic status_lfsr_fsm_error_qs;
- logic status_scrambling_fsm_error_qs;
- logic status_key_deriv_fsm_error_qs;
- logic status_bus_integ_error_qs;
- logic status_dai_idle_qs;
- logic status_check_pending_qs;
- logic err_code_re;
- logic [2:0] err_code_err_code_0_qs;
- logic [2:0] err_code_err_code_1_qs;
- logic [2:0] err_code_err_code_2_qs;
- logic [2:0] err_code_err_code_3_qs;
- logic [2:0] err_code_err_code_4_qs;
- logic [2:0] err_code_err_code_5_qs;
- logic [2:0] err_code_err_code_6_qs;
- logic [2:0] err_code_err_code_7_qs;
- logic [2:0] err_code_err_code_8_qs;
- logic direct_access_regwen_re;
- logic direct_access_regwen_qs;
- logic direct_access_cmd_we;
- logic direct_access_cmd_rd_wd;
- logic direct_access_cmd_wr_wd;
- logic direct_access_cmd_digest_wd;
- logic direct_access_address_we;
- logic [10:0] direct_access_address_qs;
- logic [10:0] direct_access_address_wd;
- logic direct_access_wdata_0_we;
- logic [31:0] direct_access_wdata_0_qs;
- logic [31:0] direct_access_wdata_0_wd;
- logic direct_access_wdata_1_we;
- logic [31:0] direct_access_wdata_1_qs;
- logic [31:0] direct_access_wdata_1_wd;
- logic direct_access_rdata_0_re;
- logic [31:0] direct_access_rdata_0_qs;
- logic direct_access_rdata_1_re;
- logic [31:0] direct_access_rdata_1_qs;
- logic check_trigger_regwen_we;
- logic check_trigger_regwen_qs;
- logic check_trigger_regwen_wd;
- logic check_trigger_we;
- logic check_trigger_integrity_wd;
- logic check_trigger_consistency_wd;
- logic check_regwen_we;
- logic check_regwen_qs;
- logic check_regwen_wd;
- logic check_timeout_we;
- logic [31:0] check_timeout_qs;
- logic [31:0] check_timeout_wd;
- logic integrity_check_period_we;
- logic [31:0] integrity_check_period_qs;
- logic [31:0] integrity_check_period_wd;
- logic consistency_check_period_we;
- logic [31:0] consistency_check_period_qs;
- logic [31:0] consistency_check_period_wd;
- logic creator_sw_cfg_read_lock_we;
- logic creator_sw_cfg_read_lock_qs;
- logic creator_sw_cfg_read_lock_wd;
- logic owner_sw_cfg_read_lock_we;
- logic owner_sw_cfg_read_lock_qs;
- logic owner_sw_cfg_read_lock_wd;
- logic creator_sw_cfg_digest_0_re;
- logic [31:0] creator_sw_cfg_digest_0_qs;
- logic creator_sw_cfg_digest_1_re;
- logic [31:0] creator_sw_cfg_digest_1_qs;
- logic owner_sw_cfg_digest_0_re;
- logic [31:0] owner_sw_cfg_digest_0_qs;
- logic owner_sw_cfg_digest_1_re;
- logic [31:0] owner_sw_cfg_digest_1_qs;
- logic hw_cfg_digest_0_re;
- logic [31:0] hw_cfg_digest_0_qs;
- logic hw_cfg_digest_1_re;
- logic [31:0] hw_cfg_digest_1_qs;
- logic secret0_digest_0_re;
- logic [31:0] secret0_digest_0_qs;
- logic secret0_digest_1_re;
- logic [31:0] secret0_digest_1_qs;
- logic secret1_digest_0_re;
- logic [31:0] secret1_digest_0_qs;
- logic secret1_digest_1_re;
- logic [31:0] secret1_digest_1_qs;
- logic secret2_digest_0_re;
- logic [31:0] secret2_digest_0_qs;
- logic secret2_digest_1_re;
- logic [31:0] secret2_digest_1_qs;
-
- // Register instances
- // R[intr_state]: V(False)
-
- // F[otp_operation_done]: 0:0
- prim_subreg #(
- .DW (1),
- .SWACCESS("W1C"),
- .RESVAL (1'h0)
- ) u_intr_state_otp_operation_done (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (intr_state_we),
- .wd (intr_state_otp_operation_done_wd),
-
- // from internal hardware
- .de (hw2reg.intr_state.otp_operation_done.de),
- .d (hw2reg.intr_state.otp_operation_done.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_state.otp_operation_done.q),
-
- // to register interface (read)
- .qs (intr_state_otp_operation_done_qs)
- );
-
-
- // F[otp_error]: 1:1
- prim_subreg #(
- .DW (1),
- .SWACCESS("W1C"),
- .RESVAL (1'h0)
- ) u_intr_state_otp_error (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (intr_state_we),
- .wd (intr_state_otp_error_wd),
-
- // from internal hardware
- .de (hw2reg.intr_state.otp_error.de),
- .d (hw2reg.intr_state.otp_error.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_state.otp_error.q),
-
- // to register interface (read)
- .qs (intr_state_otp_error_qs)
- );
-
-
- // R[intr_enable]: V(False)
-
- // F[otp_operation_done]: 0:0
- prim_subreg #(
- .DW (1),
- .SWACCESS("RW"),
- .RESVAL (1'h0)
- ) u_intr_enable_otp_operation_done (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (intr_enable_we),
- .wd (intr_enable_otp_operation_done_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_enable.otp_operation_done.q),
-
- // to register interface (read)
- .qs (intr_enable_otp_operation_done_qs)
- );
-
-
- // F[otp_error]: 1:1
- prim_subreg #(
- .DW (1),
- .SWACCESS("RW"),
- .RESVAL (1'h0)
- ) u_intr_enable_otp_error (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (intr_enable_we),
- .wd (intr_enable_otp_error_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_enable.otp_error.q),
-
- // to register interface (read)
- .qs (intr_enable_otp_error_qs)
- );
-
-
- // R[intr_test]: V(True)
-
- // F[otp_operation_done]: 0:0
- prim_subreg_ext #(
- .DW (1)
- ) u_intr_test_otp_operation_done (
- .re (1'b0),
- .we (intr_test_we),
- .wd (intr_test_otp_operation_done_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.intr_test.otp_operation_done.qe),
- .q (reg2hw.intr_test.otp_operation_done.q),
- .qs ()
- );
-
-
- // F[otp_error]: 1:1
- prim_subreg_ext #(
- .DW (1)
- ) u_intr_test_otp_error (
- .re (1'b0),
- .we (intr_test_we),
- .wd (intr_test_otp_error_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.intr_test.otp_error.qe),
- .q (reg2hw.intr_test.otp_error.q),
- .qs ()
- );
-
-
- // R[alert_test]: V(True)
-
- // F[fatal_macro_error]: 0:0
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_fatal_macro_error (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_fatal_macro_error_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.fatal_macro_error.qe),
- .q (reg2hw.alert_test.fatal_macro_error.q),
- .qs ()
- );
-
-
- // F[fatal_check_error]: 1:1
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_fatal_check_error (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_fatal_check_error_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.fatal_check_error.qe),
- .q (reg2hw.alert_test.fatal_check_error.q),
- .qs ()
- );
-
-
- // F[fatal_bus_integ_error]: 2:2
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_fatal_bus_integ_error (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_fatal_bus_integ_error_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.fatal_bus_integ_error.qe),
- .q (reg2hw.alert_test.fatal_bus_integ_error.q),
- .qs ()
- );
-
-
- // R[status]: V(True)
-
- // F[creator_sw_cfg_error]: 0:0
- prim_subreg_ext #(
- .DW (1)
- ) u_status_creator_sw_cfg_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.creator_sw_cfg_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_creator_sw_cfg_error_qs)
- );
-
-
- // F[owner_sw_cfg_error]: 1:1
- prim_subreg_ext #(
- .DW (1)
- ) u_status_owner_sw_cfg_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.owner_sw_cfg_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_owner_sw_cfg_error_qs)
- );
-
-
- // F[hw_cfg_error]: 2:2
- prim_subreg_ext #(
- .DW (1)
- ) u_status_hw_cfg_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.hw_cfg_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_hw_cfg_error_qs)
- );
-
-
- // F[secret0_error]: 3:3
- prim_subreg_ext #(
- .DW (1)
- ) u_status_secret0_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.secret0_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_secret0_error_qs)
- );
-
-
- // F[secret1_error]: 4:4
- prim_subreg_ext #(
- .DW (1)
- ) u_status_secret1_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.secret1_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_secret1_error_qs)
- );
-
-
- // F[secret2_error]: 5:5
- prim_subreg_ext #(
- .DW (1)
- ) u_status_secret2_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.secret2_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_secret2_error_qs)
- );
-
-
- // F[life_cycle_error]: 6:6
- prim_subreg_ext #(
- .DW (1)
- ) u_status_life_cycle_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.life_cycle_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_life_cycle_error_qs)
- );
-
-
- // F[dai_error]: 7:7
- prim_subreg_ext #(
- .DW (1)
- ) u_status_dai_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.dai_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_dai_error_qs)
- );
-
-
- // F[lci_error]: 8:8
- prim_subreg_ext #(
- .DW (1)
- ) u_status_lci_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.lci_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_lci_error_qs)
- );
-
-
- // F[timeout_error]: 9:9
- prim_subreg_ext #(
- .DW (1)
- ) u_status_timeout_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.timeout_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_timeout_error_qs)
- );
-
-
- // F[lfsr_fsm_error]: 10:10
- prim_subreg_ext #(
- .DW (1)
- ) u_status_lfsr_fsm_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.lfsr_fsm_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_lfsr_fsm_error_qs)
- );
-
-
- // F[scrambling_fsm_error]: 11:11
- prim_subreg_ext #(
- .DW (1)
- ) u_status_scrambling_fsm_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.scrambling_fsm_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_scrambling_fsm_error_qs)
- );
-
-
- // F[key_deriv_fsm_error]: 12:12
- prim_subreg_ext #(
- .DW (1)
- ) u_status_key_deriv_fsm_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.key_deriv_fsm_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_key_deriv_fsm_error_qs)
- );
-
-
- // F[bus_integ_error]: 13:13
- prim_subreg_ext #(
- .DW (1)
- ) u_status_bus_integ_error (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.bus_integ_error.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_bus_integ_error_qs)
- );
-
-
- // F[dai_idle]: 14:14
- prim_subreg_ext #(
- .DW (1)
- ) u_status_dai_idle (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.dai_idle.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_dai_idle_qs)
- );
-
-
- // F[check_pending]: 15:15
- prim_subreg_ext #(
- .DW (1)
- ) u_status_check_pending (
- .re (status_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.status.check_pending.d),
- .qre (),
- .qe (),
- .q (),
- .qs (status_check_pending_qs)
- );
-
-
-
- // Subregister 0 of Multireg err_code
- // R[err_code]: V(True)
-
- // F[err_code_0]: 2:0
- prim_subreg_ext #(
- .DW (3)
- ) u_err_code_err_code_0 (
- .re (err_code_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.err_code[0].d),
- .qre (),
- .qe (),
- .q (),
- .qs (err_code_err_code_0_qs)
- );
-
-
- // F[err_code_1]: 5:3
- prim_subreg_ext #(
- .DW (3)
- ) u_err_code_err_code_1 (
- .re (err_code_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.err_code[1].d),
- .qre (),
- .qe (),
- .q (),
- .qs (err_code_err_code_1_qs)
- );
-
-
- // F[err_code_2]: 8:6
- prim_subreg_ext #(
- .DW (3)
- ) u_err_code_err_code_2 (
- .re (err_code_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.err_code[2].d),
- .qre (),
- .qe (),
- .q (),
- .qs (err_code_err_code_2_qs)
- );
-
-
- // F[err_code_3]: 11:9
- prim_subreg_ext #(
- .DW (3)
- ) u_err_code_err_code_3 (
- .re (err_code_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.err_code[3].d),
- .qre (),
- .qe (),
- .q (),
- .qs (err_code_err_code_3_qs)
- );
-
-
- // F[err_code_4]: 14:12
- prim_subreg_ext #(
- .DW (3)
- ) u_err_code_err_code_4 (
- .re (err_code_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.err_code[4].d),
- .qre (),
- .qe (),
- .q (),
- .qs (err_code_err_code_4_qs)
- );
-
-
- // F[err_code_5]: 17:15
- prim_subreg_ext #(
- .DW (3)
- ) u_err_code_err_code_5 (
- .re (err_code_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.err_code[5].d),
- .qre (),
- .qe (),
- .q (),
- .qs (err_code_err_code_5_qs)
- );
-
-
- // F[err_code_6]: 20:18
- prim_subreg_ext #(
- .DW (3)
- ) u_err_code_err_code_6 (
- .re (err_code_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.err_code[6].d),
- .qre (),
- .qe (),
- .q (),
- .qs (err_code_err_code_6_qs)
- );
-
-
- // F[err_code_7]: 23:21
- prim_subreg_ext #(
- .DW (3)
- ) u_err_code_err_code_7 (
- .re (err_code_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.err_code[7].d),
- .qre (),
- .qe (),
- .q (),
- .qs (err_code_err_code_7_qs)
- );
-
-
- // F[err_code_8]: 26:24
- prim_subreg_ext #(
- .DW (3)
- ) u_err_code_err_code_8 (
- .re (err_code_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.err_code[8].d),
- .qre (),
- .qe (),
- .q (),
- .qs (err_code_err_code_8_qs)
- );
-
-
-
- // R[direct_access_regwen]: V(True)
-
- prim_subreg_ext #(
- .DW (1)
- ) u_direct_access_regwen (
- .re (direct_access_regwen_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.direct_access_regwen.d),
- .qre (),
- .qe (),
- .q (),
- .qs (direct_access_regwen_qs)
- );
-
-
- // R[direct_access_cmd]: V(True)
-
- // F[rd]: 0:0
- prim_subreg_ext #(
- .DW (1)
- ) u_direct_access_cmd_rd (
- .re (1'b0),
- .we (direct_access_cmd_we & direct_access_regwen_qs),
- .wd (direct_access_cmd_rd_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.direct_access_cmd.rd.qe),
- .q (reg2hw.direct_access_cmd.rd.q),
- .qs ()
- );
-
-
- // F[wr]: 1:1
- prim_subreg_ext #(
- .DW (1)
- ) u_direct_access_cmd_wr (
- .re (1'b0),
- .we (direct_access_cmd_we & direct_access_regwen_qs),
- .wd (direct_access_cmd_wr_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.direct_access_cmd.wr.qe),
- .q (reg2hw.direct_access_cmd.wr.q),
- .qs ()
- );
-
-
- // F[digest]: 2:2
- prim_subreg_ext #(
- .DW (1)
- ) u_direct_access_cmd_digest (
- .re (1'b0),
- .we (direct_access_cmd_we & direct_access_regwen_qs),
- .wd (direct_access_cmd_digest_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.direct_access_cmd.digest.qe),
- .q (reg2hw.direct_access_cmd.digest.q),
- .qs ()
- );
-
-
- // R[direct_access_address]: V(False)
-
- prim_subreg #(
- .DW (11),
- .SWACCESS("RW"),
- .RESVAL (11'h0)
- ) u_direct_access_address (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (direct_access_address_we & direct_access_regwen_qs),
- .wd (direct_access_address_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.direct_access_address.q),
-
- // to register interface (read)
- .qs (direct_access_address_qs)
- );
-
-
-
- // Subregister 0 of Multireg direct_access_wdata
- // R[direct_access_wdata_0]: V(False)
-
- prim_subreg #(
- .DW (32),
- .SWACCESS("RW"),
- .RESVAL (32'h0)
- ) u_direct_access_wdata_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (direct_access_wdata_0_we & direct_access_regwen_qs),
- .wd (direct_access_wdata_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.direct_access_wdata[0].q),
-
- // to register interface (read)
- .qs (direct_access_wdata_0_qs)
- );
-
- // Subregister 1 of Multireg direct_access_wdata
- // R[direct_access_wdata_1]: V(False)
-
- prim_subreg #(
- .DW (32),
- .SWACCESS("RW"),
- .RESVAL (32'h0)
- ) u_direct_access_wdata_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (direct_access_wdata_1_we & direct_access_regwen_qs),
- .wd (direct_access_wdata_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.direct_access_wdata[1].q),
-
- // to register interface (read)
- .qs (direct_access_wdata_1_qs)
- );
-
-
-
- // Subregister 0 of Multireg direct_access_rdata
- // R[direct_access_rdata_0]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_direct_access_rdata_0 (
- .re (direct_access_rdata_0_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.direct_access_rdata[0].d),
- .qre (),
- .qe (),
- .q (),
- .qs (direct_access_rdata_0_qs)
- );
-
- // Subregister 1 of Multireg direct_access_rdata
- // R[direct_access_rdata_1]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_direct_access_rdata_1 (
- .re (direct_access_rdata_1_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.direct_access_rdata[1].d),
- .qre (),
- .qe (),
- .q (),
- .qs (direct_access_rdata_1_qs)
- );
-
-
- // R[check_trigger_regwen]: V(False)
-
- prim_subreg #(
- .DW (1),
- .SWACCESS("W0C"),
- .RESVAL (1'h1)
- ) u_check_trigger_regwen (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (check_trigger_regwen_we),
- .wd (check_trigger_regwen_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (check_trigger_regwen_qs)
- );
-
-
- // R[check_trigger]: V(True)
-
- // F[integrity]: 0:0
- prim_subreg_ext #(
- .DW (1)
- ) u_check_trigger_integrity (
- .re (1'b0),
- .we (check_trigger_we & check_trigger_regwen_qs),
- .wd (check_trigger_integrity_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.check_trigger.integrity.qe),
- .q (reg2hw.check_trigger.integrity.q),
- .qs ()
- );
-
-
- // F[consistency]: 1:1
- prim_subreg_ext #(
- .DW (1)
- ) u_check_trigger_consistency (
- .re (1'b0),
- .we (check_trigger_we & check_trigger_regwen_qs),
- .wd (check_trigger_consistency_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.check_trigger.consistency.qe),
- .q (reg2hw.check_trigger.consistency.q),
- .qs ()
- );
-
-
- // R[check_regwen]: V(False)
-
- prim_subreg #(
- .DW (1),
- .SWACCESS("W0C"),
- .RESVAL (1'h1)
- ) u_check_regwen (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (check_regwen_we),
- .wd (check_regwen_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (check_regwen_qs)
- );
-
-
- // R[check_timeout]: V(False)
-
- prim_subreg #(
- .DW (32),
- .SWACCESS("RW"),
- .RESVAL (32'h0)
- ) u_check_timeout (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (check_timeout_we & check_regwen_qs),
- .wd (check_timeout_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.check_timeout.q),
-
- // to register interface (read)
- .qs (check_timeout_qs)
- );
-
-
- // R[integrity_check_period]: V(False)
-
- prim_subreg #(
- .DW (32),
- .SWACCESS("RW"),
- .RESVAL (32'h0)
- ) u_integrity_check_period (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (integrity_check_period_we & check_regwen_qs),
- .wd (integrity_check_period_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.integrity_check_period.q),
-
- // to register interface (read)
- .qs (integrity_check_period_qs)
- );
-
-
- // R[consistency_check_period]: V(False)
-
- prim_subreg #(
- .DW (32),
- .SWACCESS("RW"),
- .RESVAL (32'h0)
- ) u_consistency_check_period (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (consistency_check_period_we & check_regwen_qs),
- .wd (consistency_check_period_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.consistency_check_period.q),
-
- // to register interface (read)
- .qs (consistency_check_period_qs)
- );
-
-
- // R[creator_sw_cfg_read_lock]: V(False)
-
- prim_subreg #(
- .DW (1),
- .SWACCESS("W0C"),
- .RESVAL (1'h1)
- ) u_creator_sw_cfg_read_lock (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (creator_sw_cfg_read_lock_we & direct_access_regwen_qs),
- .wd (creator_sw_cfg_read_lock_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.creator_sw_cfg_read_lock.q),
-
- // to register interface (read)
- .qs (creator_sw_cfg_read_lock_qs)
- );
-
-
- // R[owner_sw_cfg_read_lock]: V(False)
-
- prim_subreg #(
- .DW (1),
- .SWACCESS("W0C"),
- .RESVAL (1'h1)
- ) u_owner_sw_cfg_read_lock (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (owner_sw_cfg_read_lock_we & direct_access_regwen_qs),
- .wd (owner_sw_cfg_read_lock_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.owner_sw_cfg_read_lock.q),
-
- // to register interface (read)
- .qs (owner_sw_cfg_read_lock_qs)
- );
-
-
-
- // Subregister 0 of Multireg creator_sw_cfg_digest
- // R[creator_sw_cfg_digest_0]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_creator_sw_cfg_digest_0 (
- .re (creator_sw_cfg_digest_0_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.creator_sw_cfg_digest[0].d),
- .qre (),
- .qe (),
- .q (),
- .qs (creator_sw_cfg_digest_0_qs)
- );
-
- // Subregister 1 of Multireg creator_sw_cfg_digest
- // R[creator_sw_cfg_digest_1]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_creator_sw_cfg_digest_1 (
- .re (creator_sw_cfg_digest_1_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.creator_sw_cfg_digest[1].d),
- .qre (),
- .qe (),
- .q (),
- .qs (creator_sw_cfg_digest_1_qs)
- );
-
-
-
- // Subregister 0 of Multireg owner_sw_cfg_digest
- // R[owner_sw_cfg_digest_0]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_owner_sw_cfg_digest_0 (
- .re (owner_sw_cfg_digest_0_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.owner_sw_cfg_digest[0].d),
- .qre (),
- .qe (),
- .q (),
- .qs (owner_sw_cfg_digest_0_qs)
- );
-
- // Subregister 1 of Multireg owner_sw_cfg_digest
- // R[owner_sw_cfg_digest_1]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_owner_sw_cfg_digest_1 (
- .re (owner_sw_cfg_digest_1_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.owner_sw_cfg_digest[1].d),
- .qre (),
- .qe (),
- .q (),
- .qs (owner_sw_cfg_digest_1_qs)
- );
-
-
-
- // Subregister 0 of Multireg hw_cfg_digest
- // R[hw_cfg_digest_0]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_hw_cfg_digest_0 (
- .re (hw_cfg_digest_0_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.hw_cfg_digest[0].d),
- .qre (),
- .qe (),
- .q (),
- .qs (hw_cfg_digest_0_qs)
- );
-
- // Subregister 1 of Multireg hw_cfg_digest
- // R[hw_cfg_digest_1]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_hw_cfg_digest_1 (
- .re (hw_cfg_digest_1_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.hw_cfg_digest[1].d),
- .qre (),
- .qe (),
- .q (),
- .qs (hw_cfg_digest_1_qs)
- );
-
-
-
- // Subregister 0 of Multireg secret0_digest
- // R[secret0_digest_0]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_secret0_digest_0 (
- .re (secret0_digest_0_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.secret0_digest[0].d),
- .qre (),
- .qe (),
- .q (),
- .qs (secret0_digest_0_qs)
- );
-
- // Subregister 1 of Multireg secret0_digest
- // R[secret0_digest_1]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_secret0_digest_1 (
- .re (secret0_digest_1_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.secret0_digest[1].d),
- .qre (),
- .qe (),
- .q (),
- .qs (secret0_digest_1_qs)
- );
-
-
-
- // Subregister 0 of Multireg secret1_digest
- // R[secret1_digest_0]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_secret1_digest_0 (
- .re (secret1_digest_0_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.secret1_digest[0].d),
- .qre (),
- .qe (),
- .q (),
- .qs (secret1_digest_0_qs)
- );
-
- // Subregister 1 of Multireg secret1_digest
- // R[secret1_digest_1]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_secret1_digest_1 (
- .re (secret1_digest_1_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.secret1_digest[1].d),
- .qre (),
- .qe (),
- .q (),
- .qs (secret1_digest_1_qs)
- );
-
-
-
- // Subregister 0 of Multireg secret2_digest
- // R[secret2_digest_0]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_secret2_digest_0 (
- .re (secret2_digest_0_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.secret2_digest[0].d),
- .qre (),
- .qe (),
- .q (),
- .qs (secret2_digest_0_qs)
- );
-
- // Subregister 1 of Multireg secret2_digest
- // R[secret2_digest_1]: V(True)
-
- prim_subreg_ext #(
- .DW (32)
- ) u_secret2_digest_1 (
- .re (secret2_digest_1_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.secret2_digest[1].d),
- .qre (),
- .qe (),
- .q (),
- .qs (secret2_digest_1_qs)
- );
-
-
-
-
- logic [32:0] addr_hit;
- always_comb begin
- addr_hit = '0;
- addr_hit[ 0] = (reg_addr == OTP_CTRL_INTR_STATE_OFFSET);
- addr_hit[ 1] = (reg_addr == OTP_CTRL_INTR_ENABLE_OFFSET);
- addr_hit[ 2] = (reg_addr == OTP_CTRL_INTR_TEST_OFFSET);
- addr_hit[ 3] = (reg_addr == OTP_CTRL_ALERT_TEST_OFFSET);
- addr_hit[ 4] = (reg_addr == OTP_CTRL_STATUS_OFFSET);
- addr_hit[ 5] = (reg_addr == OTP_CTRL_ERR_CODE_OFFSET);
- addr_hit[ 6] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET);
- addr_hit[ 7] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET);
- addr_hit[ 8] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET);
- addr_hit[ 9] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET);
- addr_hit[10] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET);
- addr_hit[11] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET);
- addr_hit[12] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET);
- addr_hit[13] = (reg_addr == OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET);
- addr_hit[14] = (reg_addr == OTP_CTRL_CHECK_TRIGGER_OFFSET);
- addr_hit[15] = (reg_addr == OTP_CTRL_CHECK_REGWEN_OFFSET);
- addr_hit[16] = (reg_addr == OTP_CTRL_CHECK_TIMEOUT_OFFSET);
- addr_hit[17] = (reg_addr == OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET);
- addr_hit[18] = (reg_addr == OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET);
- addr_hit[19] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET);
- addr_hit[20] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET);
- addr_hit[21] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET);
- addr_hit[22] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET);
- addr_hit[23] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET);
- addr_hit[24] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET);
- addr_hit[25] = (reg_addr == OTP_CTRL_HW_CFG_DIGEST_0_OFFSET);
- addr_hit[26] = (reg_addr == OTP_CTRL_HW_CFG_DIGEST_1_OFFSET);
- addr_hit[27] = (reg_addr == OTP_CTRL_SECRET0_DIGEST_0_OFFSET);
- addr_hit[28] = (reg_addr == OTP_CTRL_SECRET0_DIGEST_1_OFFSET);
- addr_hit[29] = (reg_addr == OTP_CTRL_SECRET1_DIGEST_0_OFFSET);
- addr_hit[30] = (reg_addr == OTP_CTRL_SECRET1_DIGEST_1_OFFSET);
- addr_hit[31] = (reg_addr == OTP_CTRL_SECRET2_DIGEST_0_OFFSET);
- addr_hit[32] = (reg_addr == OTP_CTRL_SECRET2_DIGEST_1_OFFSET);
- end
-
- assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-
- // Check sub-word write is permitted
- always_comb begin
- wr_err = (reg_we &
- ((addr_hit[ 0] & (|(OTP_CTRL_PERMIT[ 0] & ~reg_be))) |
- (addr_hit[ 1] & (|(OTP_CTRL_PERMIT[ 1] & ~reg_be))) |
- (addr_hit[ 2] & (|(OTP_CTRL_PERMIT[ 2] & ~reg_be))) |
- (addr_hit[ 3] & (|(OTP_CTRL_PERMIT[ 3] & ~reg_be))) |
- (addr_hit[ 4] & (|(OTP_CTRL_PERMIT[ 4] & ~reg_be))) |
- (addr_hit[ 5] & (|(OTP_CTRL_PERMIT[ 5] & ~reg_be))) |
- (addr_hit[ 6] & (|(OTP_CTRL_PERMIT[ 6] & ~reg_be))) |
- (addr_hit[ 7] & (|(OTP_CTRL_PERMIT[ 7] & ~reg_be))) |
- (addr_hit[ 8] & (|(OTP_CTRL_PERMIT[ 8] & ~reg_be))) |
- (addr_hit[ 9] & (|(OTP_CTRL_PERMIT[ 9] & ~reg_be))) |
- (addr_hit[10] & (|(OTP_CTRL_PERMIT[10] & ~reg_be))) |
- (addr_hit[11] & (|(OTP_CTRL_PERMIT[11] & ~reg_be))) |
- (addr_hit[12] & (|(OTP_CTRL_PERMIT[12] & ~reg_be))) |
- (addr_hit[13] & (|(OTP_CTRL_PERMIT[13] & ~reg_be))) |
- (addr_hit[14] & (|(OTP_CTRL_PERMIT[14] & ~reg_be))) |
- (addr_hit[15] & (|(OTP_CTRL_PERMIT[15] & ~reg_be))) |
- (addr_hit[16] & (|(OTP_CTRL_PERMIT[16] & ~reg_be))) |
- (addr_hit[17] & (|(OTP_CTRL_PERMIT[17] & ~reg_be))) |
- (addr_hit[18] & (|(OTP_CTRL_PERMIT[18] & ~reg_be))) |
- (addr_hit[19] & (|(OTP_CTRL_PERMIT[19] & ~reg_be))) |
- (addr_hit[20] & (|(OTP_CTRL_PERMIT[20] & ~reg_be))) |
- (addr_hit[21] & (|(OTP_CTRL_PERMIT[21] & ~reg_be))) |
- (addr_hit[22] & (|(OTP_CTRL_PERMIT[22] & ~reg_be))) |
- (addr_hit[23] & (|(OTP_CTRL_PERMIT[23] & ~reg_be))) |
- (addr_hit[24] & (|(OTP_CTRL_PERMIT[24] & ~reg_be))) |
- (addr_hit[25] & (|(OTP_CTRL_PERMIT[25] & ~reg_be))) |
- (addr_hit[26] & (|(OTP_CTRL_PERMIT[26] & ~reg_be))) |
- (addr_hit[27] & (|(OTP_CTRL_PERMIT[27] & ~reg_be))) |
- (addr_hit[28] & (|(OTP_CTRL_PERMIT[28] & ~reg_be))) |
- (addr_hit[29] & (|(OTP_CTRL_PERMIT[29] & ~reg_be))) |
- (addr_hit[30] & (|(OTP_CTRL_PERMIT[30] & ~reg_be))) |
- (addr_hit[31] & (|(OTP_CTRL_PERMIT[31] & ~reg_be))) |
- (addr_hit[32] & (|(OTP_CTRL_PERMIT[32] & ~reg_be)))));
- end
- assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
-
- assign intr_state_otp_operation_done_wd = reg_wdata[0];
-
- assign intr_state_otp_error_wd = reg_wdata[1];
- assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
-
- assign intr_enable_otp_operation_done_wd = reg_wdata[0];
-
- assign intr_enable_otp_error_wd = reg_wdata[1];
- assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
-
- assign intr_test_otp_operation_done_wd = reg_wdata[0];
-
- assign intr_test_otp_error_wd = reg_wdata[1];
- assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
-
- assign alert_test_fatal_macro_error_wd = reg_wdata[0];
-
- assign alert_test_fatal_check_error_wd = reg_wdata[1];
-
- assign alert_test_fatal_bus_integ_error_wd = reg_wdata[2];
- assign status_re = addr_hit[4] & reg_re & !reg_error;
- assign err_code_re = addr_hit[5] & reg_re & !reg_error;
- assign direct_access_regwen_re = addr_hit[6] & reg_re & !reg_error;
- assign direct_access_cmd_we = addr_hit[7] & reg_we & !reg_error;
-
- assign direct_access_cmd_rd_wd = reg_wdata[0];
-
- assign direct_access_cmd_wr_wd = reg_wdata[1];
-
- assign direct_access_cmd_digest_wd = reg_wdata[2];
- assign direct_access_address_we = addr_hit[8] & reg_we & !reg_error;
-
- assign direct_access_address_wd = reg_wdata[10:0];
- assign direct_access_wdata_0_we = addr_hit[9] & reg_we & !reg_error;
-
- assign direct_access_wdata_0_wd = reg_wdata[31:0];
- assign direct_access_wdata_1_we = addr_hit[10] & reg_we & !reg_error;
-
- assign direct_access_wdata_1_wd = reg_wdata[31:0];
- assign direct_access_rdata_0_re = addr_hit[11] & reg_re & !reg_error;
- assign direct_access_rdata_1_re = addr_hit[12] & reg_re & !reg_error;
- assign check_trigger_regwen_we = addr_hit[13] & reg_we & !reg_error;
-
- assign check_trigger_regwen_wd = reg_wdata[0];
- assign check_trigger_we = addr_hit[14] & reg_we & !reg_error;
-
- assign check_trigger_integrity_wd = reg_wdata[0];
-
- assign check_trigger_consistency_wd = reg_wdata[1];
- assign check_regwen_we = addr_hit[15] & reg_we & !reg_error;
-
- assign check_regwen_wd = reg_wdata[0];
- assign check_timeout_we = addr_hit[16] & reg_we & !reg_error;
-
- assign check_timeout_wd = reg_wdata[31:0];
- assign integrity_check_period_we = addr_hit[17] & reg_we & !reg_error;
-
- assign integrity_check_period_wd = reg_wdata[31:0];
- assign consistency_check_period_we = addr_hit[18] & reg_we & !reg_error;
-
- assign consistency_check_period_wd = reg_wdata[31:0];
- assign creator_sw_cfg_read_lock_we = addr_hit[19] & reg_we & !reg_error;
-
- assign creator_sw_cfg_read_lock_wd = reg_wdata[0];
- assign owner_sw_cfg_read_lock_we = addr_hit[20] & reg_we & !reg_error;
-
- assign owner_sw_cfg_read_lock_wd = reg_wdata[0];
- assign creator_sw_cfg_digest_0_re = addr_hit[21] & reg_re & !reg_error;
- assign creator_sw_cfg_digest_1_re = addr_hit[22] & reg_re & !reg_error;
- assign owner_sw_cfg_digest_0_re = addr_hit[23] & reg_re & !reg_error;
- assign owner_sw_cfg_digest_1_re = addr_hit[24] & reg_re & !reg_error;
- assign hw_cfg_digest_0_re = addr_hit[25] & reg_re & !reg_error;
- assign hw_cfg_digest_1_re = addr_hit[26] & reg_re & !reg_error;
- assign secret0_digest_0_re = addr_hit[27] & reg_re & !reg_error;
- assign secret0_digest_1_re = addr_hit[28] & reg_re & !reg_error;
- assign secret1_digest_0_re = addr_hit[29] & reg_re & !reg_error;
- assign secret1_digest_1_re = addr_hit[30] & reg_re & !reg_error;
- assign secret2_digest_0_re = addr_hit[31] & reg_re & !reg_error;
- assign secret2_digest_1_re = addr_hit[32] & reg_re & !reg_error;
-
- // Read data return
- always_comb begin
- reg_rdata_next = '0;
- unique case (1'b1)
- addr_hit[0]: begin
- reg_rdata_next[0] = intr_state_otp_operation_done_qs;
- reg_rdata_next[1] = intr_state_otp_error_qs;
- end
-
- addr_hit[1]: begin
- reg_rdata_next[0] = intr_enable_otp_operation_done_qs;
- reg_rdata_next[1] = intr_enable_otp_error_qs;
- end
-
- addr_hit[2]: begin
- reg_rdata_next[0] = '0;
- reg_rdata_next[1] = '0;
- end
-
- addr_hit[3]: begin
- reg_rdata_next[0] = '0;
- reg_rdata_next[1] = '0;
- reg_rdata_next[2] = '0;
- end
-
- addr_hit[4]: begin
- reg_rdata_next[0] = status_creator_sw_cfg_error_qs;
- reg_rdata_next[1] = status_owner_sw_cfg_error_qs;
- reg_rdata_next[2] = status_hw_cfg_error_qs;
- reg_rdata_next[3] = status_secret0_error_qs;
- reg_rdata_next[4] = status_secret1_error_qs;
- reg_rdata_next[5] = status_secret2_error_qs;
- reg_rdata_next[6] = status_life_cycle_error_qs;
- reg_rdata_next[7] = status_dai_error_qs;
- reg_rdata_next[8] = status_lci_error_qs;
- reg_rdata_next[9] = status_timeout_error_qs;
- reg_rdata_next[10] = status_lfsr_fsm_error_qs;
- reg_rdata_next[11] = status_scrambling_fsm_error_qs;
- reg_rdata_next[12] = status_key_deriv_fsm_error_qs;
- reg_rdata_next[13] = status_bus_integ_error_qs;
- reg_rdata_next[14] = status_dai_idle_qs;
- reg_rdata_next[15] = status_check_pending_qs;
- end
-
- addr_hit[5]: begin
- reg_rdata_next[2:0] = err_code_err_code_0_qs;
- reg_rdata_next[5:3] = err_code_err_code_1_qs;
- reg_rdata_next[8:6] = err_code_err_code_2_qs;
- reg_rdata_next[11:9] = err_code_err_code_3_qs;
- reg_rdata_next[14:12] = err_code_err_code_4_qs;
- reg_rdata_next[17:15] = err_code_err_code_5_qs;
- reg_rdata_next[20:18] = err_code_err_code_6_qs;
- reg_rdata_next[23:21] = err_code_err_code_7_qs;
- reg_rdata_next[26:24] = err_code_err_code_8_qs;
- end
-
- addr_hit[6]: begin
- reg_rdata_next[0] = direct_access_regwen_qs;
- end
-
- addr_hit[7]: begin
- reg_rdata_next[0] = '0;
- reg_rdata_next[1] = '0;
- reg_rdata_next[2] = '0;
- end
-
- addr_hit[8]: begin
- reg_rdata_next[10:0] = direct_access_address_qs;
- end
-
- addr_hit[9]: begin
- reg_rdata_next[31:0] = direct_access_wdata_0_qs;
- end
-
- addr_hit[10]: begin
- reg_rdata_next[31:0] = direct_access_wdata_1_qs;
- end
-
- addr_hit[11]: begin
- reg_rdata_next[31:0] = direct_access_rdata_0_qs;
- end
-
- addr_hit[12]: begin
- reg_rdata_next[31:0] = direct_access_rdata_1_qs;
- end
-
- addr_hit[13]: begin
- reg_rdata_next[0] = check_trigger_regwen_qs;
- end
-
- addr_hit[14]: begin
- reg_rdata_next[0] = '0;
- reg_rdata_next[1] = '0;
- end
-
- addr_hit[15]: begin
- reg_rdata_next[0] = check_regwen_qs;
- end
-
- addr_hit[16]: begin
- reg_rdata_next[31:0] = check_timeout_qs;
- end
-
- addr_hit[17]: begin
- reg_rdata_next[31:0] = integrity_check_period_qs;
- end
-
- addr_hit[18]: begin
- reg_rdata_next[31:0] = consistency_check_period_qs;
- end
-
- addr_hit[19]: begin
- reg_rdata_next[0] = creator_sw_cfg_read_lock_qs;
- end
-
- addr_hit[20]: begin
- reg_rdata_next[0] = owner_sw_cfg_read_lock_qs;
- end
-
- addr_hit[21]: begin
- reg_rdata_next[31:0] = creator_sw_cfg_digest_0_qs;
- end
-
- addr_hit[22]: begin
- reg_rdata_next[31:0] = creator_sw_cfg_digest_1_qs;
- end
-
- addr_hit[23]: begin
- reg_rdata_next[31:0] = owner_sw_cfg_digest_0_qs;
- end
-
- addr_hit[24]: begin
- reg_rdata_next[31:0] = owner_sw_cfg_digest_1_qs;
- end
-
- addr_hit[25]: begin
- reg_rdata_next[31:0] = hw_cfg_digest_0_qs;
- end
-
- addr_hit[26]: begin
- reg_rdata_next[31:0] = hw_cfg_digest_1_qs;
- end
-
- addr_hit[27]: begin
- reg_rdata_next[31:0] = secret0_digest_0_qs;
- end
-
- addr_hit[28]: begin
- reg_rdata_next[31:0] = secret0_digest_1_qs;
- end
-
- addr_hit[29]: begin
- reg_rdata_next[31:0] = secret1_digest_0_qs;
- end
-
- addr_hit[30]: begin
- reg_rdata_next[31:0] = secret1_digest_1_qs;
- end
-
- addr_hit[31]: begin
- reg_rdata_next[31:0] = secret2_digest_0_qs;
- end
-
- addr_hit[32]: begin
- reg_rdata_next[31:0] = secret2_digest_1_qs;
- end
-
- default: begin
- reg_rdata_next = '1;
- end
- endcase
- end
-
- // Unused signal tieoff
-
- // wdata / byte enable are not always fully used
- // add a blanket unused statement to handle lint waivers
- logic unused_wdata;
- logic unused_be;
- assign unused_wdata = ^reg_wdata;
- assign unused_be = ^reg_be;
-
- // Assertions for Register Interface
- `ASSERT_PULSE(wePulse, reg_we)
- `ASSERT_PULSE(rePulse, reg_re)
-
- `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
-
- `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
-
- // this is formulated as an assumption such that the FPV testbenches do disprove this
- // property by mistake
- //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
-
-endmodule
diff --git a/hw/top_earlgrey/ip/padctrl/rtl/autogen/padctrl_reg_top.sv b/hw/top_earlgrey/ip/padctrl/rtl/autogen/padctrl_reg_top.sv
deleted file mode 100644
index 9506659..0000000
--- a/hw/top_earlgrey/ip/padctrl/rtl/autogen/padctrl_reg_top.sv
+++ /dev/null
@@ -1,1956 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Register Top module auto-generated by `reggen`
-
-`include "prim_assert.sv"
-
-module padctrl_reg_top (
- input clk_i,
- input rst_ni,
-
- // Below Regster interface can be changed
- input tlul_pkg::tl_h2d_t tl_i,
- output tlul_pkg::tl_d2h_t tl_o,
- // To HW
- output padctrl_reg_pkg::padctrl_reg2hw_t reg2hw, // Write
- input padctrl_reg_pkg::padctrl_hw2reg_t hw2reg, // Read
-
- // Config
- input devmode_i // If 1, explicit error return for unmapped register access
-);
-
- import padctrl_reg_pkg::* ;
-
- localparam int AW = 7;
- localparam int DW = 32;
- localparam int DBW = DW/8; // Byte Width
-
- // register signals
- logic reg_we;
- logic reg_re;
- logic [AW-1:0] reg_addr;
- logic [DW-1:0] reg_wdata;
- logic [DBW-1:0] reg_be;
- logic [DW-1:0] reg_rdata;
- logic reg_error;
-
- logic addrmiss, wr_err;
-
- logic [DW-1:0] reg_rdata_next;
-
- tlul_pkg::tl_h2d_t tl_reg_h2d;
- tlul_pkg::tl_d2h_t tl_reg_d2h;
-
- assign tl_reg_h2d = tl_i;
- assign tl_o = tl_reg_d2h;
-
- tlul_adapter_reg #(
- .RegAw(AW),
- .RegDw(DW)
- ) u_reg_if (
- .clk_i,
- .rst_ni,
-
- .tl_i (tl_reg_h2d),
- .tl_o (tl_reg_d2h),
-
- .we_o (reg_we),
- .re_o (reg_re),
- .addr_o (reg_addr),
- .wdata_o (reg_wdata),
- .be_o (reg_be),
- .rdata_i (reg_rdata),
- .error_i (reg_error)
- );
-
- assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err ;
-
- // Define SW related signals
- // Format: <reg>_<field>_{wd|we|qs}
- // or <reg>_{wd|we|qs} if field == 1 or 0
- logic regwen_qs;
- logic regwen_wd;
- logic regwen_we;
- logic [9:0] dio_pads_0_attr_0_qs;
- logic [9:0] dio_pads_0_attr_0_wd;
- logic dio_pads_0_attr_0_we;
- logic dio_pads_0_attr_0_re;
- logic [9:0] dio_pads_0_attr_1_qs;
- logic [9:0] dio_pads_0_attr_1_wd;
- logic dio_pads_0_attr_1_we;
- logic dio_pads_0_attr_1_re;
- logic [9:0] dio_pads_0_attr_2_qs;
- logic [9:0] dio_pads_0_attr_2_wd;
- logic dio_pads_0_attr_2_we;
- logic dio_pads_0_attr_2_re;
- logic [9:0] dio_pads_1_attr_3_qs;
- logic [9:0] dio_pads_1_attr_3_wd;
- logic dio_pads_1_attr_3_we;
- logic dio_pads_1_attr_3_re;
- logic [9:0] dio_pads_1_attr_4_qs;
- logic [9:0] dio_pads_1_attr_4_wd;
- logic dio_pads_1_attr_4_we;
- logic dio_pads_1_attr_4_re;
- logic [9:0] dio_pads_1_attr_5_qs;
- logic [9:0] dio_pads_1_attr_5_wd;
- logic dio_pads_1_attr_5_we;
- logic dio_pads_1_attr_5_re;
- logic [9:0] dio_pads_2_attr_6_qs;
- logic [9:0] dio_pads_2_attr_6_wd;
- logic dio_pads_2_attr_6_we;
- logic dio_pads_2_attr_6_re;
- logic [9:0] dio_pads_2_attr_7_qs;
- logic [9:0] dio_pads_2_attr_7_wd;
- logic dio_pads_2_attr_7_we;
- logic dio_pads_2_attr_7_re;
- logic [9:0] dio_pads_2_attr_8_qs;
- logic [9:0] dio_pads_2_attr_8_wd;
- logic dio_pads_2_attr_8_we;
- logic dio_pads_2_attr_8_re;
- logic [9:0] dio_pads_3_attr_9_qs;
- logic [9:0] dio_pads_3_attr_9_wd;
- logic dio_pads_3_attr_9_we;
- logic dio_pads_3_attr_9_re;
- logic [9:0] dio_pads_3_attr_10_qs;
- logic [9:0] dio_pads_3_attr_10_wd;
- logic dio_pads_3_attr_10_we;
- logic dio_pads_3_attr_10_re;
- logic [9:0] dio_pads_3_attr_11_qs;
- logic [9:0] dio_pads_3_attr_11_wd;
- logic dio_pads_3_attr_11_we;
- logic dio_pads_3_attr_11_re;
- logic [9:0] dio_pads_4_attr_12_qs;
- logic [9:0] dio_pads_4_attr_12_wd;
- logic dio_pads_4_attr_12_we;
- logic dio_pads_4_attr_12_re;
- logic [9:0] dio_pads_4_attr_13_qs;
- logic [9:0] dio_pads_4_attr_13_wd;
- logic dio_pads_4_attr_13_we;
- logic dio_pads_4_attr_13_re;
- logic [9:0] dio_pads_4_attr_14_qs;
- logic [9:0] dio_pads_4_attr_14_wd;
- logic dio_pads_4_attr_14_we;
- logic dio_pads_4_attr_14_re;
- logic [9:0] dio_pads_5_attr_15_qs;
- logic [9:0] dio_pads_5_attr_15_wd;
- logic dio_pads_5_attr_15_we;
- logic dio_pads_5_attr_15_re;
- logic [9:0] dio_pads_5_attr_16_qs;
- logic [9:0] dio_pads_5_attr_16_wd;
- logic dio_pads_5_attr_16_we;
- logic dio_pads_5_attr_16_re;
- logic [9:0] dio_pads_5_attr_17_qs;
- logic [9:0] dio_pads_5_attr_17_wd;
- logic dio_pads_5_attr_17_we;
- logic dio_pads_5_attr_17_re;
- logic [9:0] dio_pads_6_attr_18_qs;
- logic [9:0] dio_pads_6_attr_18_wd;
- logic dio_pads_6_attr_18_we;
- logic dio_pads_6_attr_18_re;
- logic [9:0] dio_pads_6_attr_19_qs;
- logic [9:0] dio_pads_6_attr_19_wd;
- logic dio_pads_6_attr_19_we;
- logic dio_pads_6_attr_19_re;
- logic [9:0] dio_pads_6_attr_20_qs;
- logic [9:0] dio_pads_6_attr_20_wd;
- logic dio_pads_6_attr_20_we;
- logic dio_pads_6_attr_20_re;
- logic [9:0] mio_pads_0_attr_0_qs;
- logic [9:0] mio_pads_0_attr_0_wd;
- logic mio_pads_0_attr_0_we;
- logic mio_pads_0_attr_0_re;
- logic [9:0] mio_pads_0_attr_1_qs;
- logic [9:0] mio_pads_0_attr_1_wd;
- logic mio_pads_0_attr_1_we;
- logic mio_pads_0_attr_1_re;
- logic [9:0] mio_pads_0_attr_2_qs;
- logic [9:0] mio_pads_0_attr_2_wd;
- logic mio_pads_0_attr_2_we;
- logic mio_pads_0_attr_2_re;
- logic [9:0] mio_pads_1_attr_3_qs;
- logic [9:0] mio_pads_1_attr_3_wd;
- logic mio_pads_1_attr_3_we;
- logic mio_pads_1_attr_3_re;
- logic [9:0] mio_pads_1_attr_4_qs;
- logic [9:0] mio_pads_1_attr_4_wd;
- logic mio_pads_1_attr_4_we;
- logic mio_pads_1_attr_4_re;
- logic [9:0] mio_pads_1_attr_5_qs;
- logic [9:0] mio_pads_1_attr_5_wd;
- logic mio_pads_1_attr_5_we;
- logic mio_pads_1_attr_5_re;
- logic [9:0] mio_pads_2_attr_6_qs;
- logic [9:0] mio_pads_2_attr_6_wd;
- logic mio_pads_2_attr_6_we;
- logic mio_pads_2_attr_6_re;
- logic [9:0] mio_pads_2_attr_7_qs;
- logic [9:0] mio_pads_2_attr_7_wd;
- logic mio_pads_2_attr_7_we;
- logic mio_pads_2_attr_7_re;
- logic [9:0] mio_pads_2_attr_8_qs;
- logic [9:0] mio_pads_2_attr_8_wd;
- logic mio_pads_2_attr_8_we;
- logic mio_pads_2_attr_8_re;
- logic [9:0] mio_pads_3_attr_9_qs;
- logic [9:0] mio_pads_3_attr_9_wd;
- logic mio_pads_3_attr_9_we;
- logic mio_pads_3_attr_9_re;
- logic [9:0] mio_pads_3_attr_10_qs;
- logic [9:0] mio_pads_3_attr_10_wd;
- logic mio_pads_3_attr_10_we;
- logic mio_pads_3_attr_10_re;
- logic [9:0] mio_pads_3_attr_11_qs;
- logic [9:0] mio_pads_3_attr_11_wd;
- logic mio_pads_3_attr_11_we;
- logic mio_pads_3_attr_11_re;
- logic [9:0] mio_pads_4_attr_12_qs;
- logic [9:0] mio_pads_4_attr_12_wd;
- logic mio_pads_4_attr_12_we;
- logic mio_pads_4_attr_12_re;
- logic [9:0] mio_pads_4_attr_13_qs;
- logic [9:0] mio_pads_4_attr_13_wd;
- logic mio_pads_4_attr_13_we;
- logic mio_pads_4_attr_13_re;
- logic [9:0] mio_pads_4_attr_14_qs;
- logic [9:0] mio_pads_4_attr_14_wd;
- logic mio_pads_4_attr_14_we;
- logic mio_pads_4_attr_14_re;
- logic [9:0] mio_pads_5_attr_15_qs;
- logic [9:0] mio_pads_5_attr_15_wd;
- logic mio_pads_5_attr_15_we;
- logic mio_pads_5_attr_15_re;
- logic [9:0] mio_pads_5_attr_16_qs;
- logic [9:0] mio_pads_5_attr_16_wd;
- logic mio_pads_5_attr_16_we;
- logic mio_pads_5_attr_16_re;
- logic [9:0] mio_pads_5_attr_17_qs;
- logic [9:0] mio_pads_5_attr_17_wd;
- logic mio_pads_5_attr_17_we;
- logic mio_pads_5_attr_17_re;
- logic [9:0] mio_pads_6_attr_18_qs;
- logic [9:0] mio_pads_6_attr_18_wd;
- logic mio_pads_6_attr_18_we;
- logic mio_pads_6_attr_18_re;
- logic [9:0] mio_pads_6_attr_19_qs;
- logic [9:0] mio_pads_6_attr_19_wd;
- logic mio_pads_6_attr_19_we;
- logic mio_pads_6_attr_19_re;
- logic [9:0] mio_pads_6_attr_20_qs;
- logic [9:0] mio_pads_6_attr_20_wd;
- logic mio_pads_6_attr_20_we;
- logic mio_pads_6_attr_20_re;
- logic [9:0] mio_pads_7_attr_21_qs;
- logic [9:0] mio_pads_7_attr_21_wd;
- logic mio_pads_7_attr_21_we;
- logic mio_pads_7_attr_21_re;
- logic [9:0] mio_pads_7_attr_22_qs;
- logic [9:0] mio_pads_7_attr_22_wd;
- logic mio_pads_7_attr_22_we;
- logic mio_pads_7_attr_22_re;
- logic [9:0] mio_pads_7_attr_23_qs;
- logic [9:0] mio_pads_7_attr_23_wd;
- logic mio_pads_7_attr_23_we;
- logic mio_pads_7_attr_23_re;
- logic [9:0] mio_pads_8_attr_24_qs;
- logic [9:0] mio_pads_8_attr_24_wd;
- logic mio_pads_8_attr_24_we;
- logic mio_pads_8_attr_24_re;
- logic [9:0] mio_pads_8_attr_25_qs;
- logic [9:0] mio_pads_8_attr_25_wd;
- logic mio_pads_8_attr_25_we;
- logic mio_pads_8_attr_25_re;
- logic [9:0] mio_pads_8_attr_26_qs;
- logic [9:0] mio_pads_8_attr_26_wd;
- logic mio_pads_8_attr_26_we;
- logic mio_pads_8_attr_26_re;
- logic [9:0] mio_pads_9_attr_27_qs;
- logic [9:0] mio_pads_9_attr_27_wd;
- logic mio_pads_9_attr_27_we;
- logic mio_pads_9_attr_27_re;
- logic [9:0] mio_pads_9_attr_28_qs;
- logic [9:0] mio_pads_9_attr_28_wd;
- logic mio_pads_9_attr_28_we;
- logic mio_pads_9_attr_28_re;
- logic [9:0] mio_pads_9_attr_29_qs;
- logic [9:0] mio_pads_9_attr_29_wd;
- logic mio_pads_9_attr_29_we;
- logic mio_pads_9_attr_29_re;
- logic [9:0] mio_pads_10_attr_30_qs;
- logic [9:0] mio_pads_10_attr_30_wd;
- logic mio_pads_10_attr_30_we;
- logic mio_pads_10_attr_30_re;
- logic [9:0] mio_pads_10_attr_31_qs;
- logic [9:0] mio_pads_10_attr_31_wd;
- logic mio_pads_10_attr_31_we;
- logic mio_pads_10_attr_31_re;
- logic [9:0] mio_pads_10_attr_32_qs;
- logic [9:0] mio_pads_10_attr_32_wd;
- logic mio_pads_10_attr_32_we;
- logic mio_pads_10_attr_32_re;
- logic [9:0] mio_pads_11_attr_33_qs;
- logic [9:0] mio_pads_11_attr_33_wd;
- logic mio_pads_11_attr_33_we;
- logic mio_pads_11_attr_33_re;
- logic [9:0] mio_pads_11_attr_34_qs;
- logic [9:0] mio_pads_11_attr_34_wd;
- logic mio_pads_11_attr_34_we;
- logic mio_pads_11_attr_34_re;
- logic [9:0] mio_pads_11_attr_35_qs;
- logic [9:0] mio_pads_11_attr_35_wd;
- logic mio_pads_11_attr_35_we;
- logic mio_pads_11_attr_35_re;
- logic [9:0] mio_pads_12_attr_36_qs;
- logic [9:0] mio_pads_12_attr_36_wd;
- logic mio_pads_12_attr_36_we;
- logic mio_pads_12_attr_36_re;
- logic [9:0] mio_pads_12_attr_37_qs;
- logic [9:0] mio_pads_12_attr_37_wd;
- logic mio_pads_12_attr_37_we;
- logic mio_pads_12_attr_37_re;
- logic [9:0] mio_pads_12_attr_38_qs;
- logic [9:0] mio_pads_12_attr_38_wd;
- logic mio_pads_12_attr_38_we;
- logic mio_pads_12_attr_38_re;
- logic [9:0] mio_pads_13_attr_39_qs;
- logic [9:0] mio_pads_13_attr_39_wd;
- logic mio_pads_13_attr_39_we;
- logic mio_pads_13_attr_39_re;
- logic [9:0] mio_pads_13_attr_40_qs;
- logic [9:0] mio_pads_13_attr_40_wd;
- logic mio_pads_13_attr_40_we;
- logic mio_pads_13_attr_40_re;
- logic [9:0] mio_pads_13_attr_41_qs;
- logic [9:0] mio_pads_13_attr_41_wd;
- logic mio_pads_13_attr_41_we;
- logic mio_pads_13_attr_41_re;
- logic [9:0] mio_pads_14_attr_42_qs;
- logic [9:0] mio_pads_14_attr_42_wd;
- logic mio_pads_14_attr_42_we;
- logic mio_pads_14_attr_42_re;
- logic [9:0] mio_pads_14_attr_43_qs;
- logic [9:0] mio_pads_14_attr_43_wd;
- logic mio_pads_14_attr_43_we;
- logic mio_pads_14_attr_43_re;
-
- // Register instances
- // R[regwen]: V(False)
-
- prim_subreg #(
- .DW (1),
- .SWACCESS("W0C"),
- .RESVAL (1'h1)
- ) u_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (regwen_we),
- .wd (regwen_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (regwen_qs)
- );
-
-
-
- // Subregister 0 of Multireg dio_pads
- // R[dio_pads_0]: V(True)
-
- // F[attr_0]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_0_attr_0 (
- .re (dio_pads_0_attr_0_re),
- // qualified with register enable
- .we (dio_pads_0_attr_0_we & regwen_qs),
- .wd (dio_pads_0_attr_0_wd),
- .d (hw2reg.dio_pads[0].d),
- .qre (),
- .qe (reg2hw.dio_pads[0].qe),
- .q (reg2hw.dio_pads[0].q ),
- .qs (dio_pads_0_attr_0_qs)
- );
-
-
- // F[attr_1]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_0_attr_1 (
- .re (dio_pads_0_attr_1_re),
- // qualified with register enable
- .we (dio_pads_0_attr_1_we & regwen_qs),
- .wd (dio_pads_0_attr_1_wd),
- .d (hw2reg.dio_pads[1].d),
- .qre (),
- .qe (reg2hw.dio_pads[1].qe),
- .q (reg2hw.dio_pads[1].q ),
- .qs (dio_pads_0_attr_1_qs)
- );
-
-
- // F[attr_2]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_0_attr_2 (
- .re (dio_pads_0_attr_2_re),
- // qualified with register enable
- .we (dio_pads_0_attr_2_we & regwen_qs),
- .wd (dio_pads_0_attr_2_wd),
- .d (hw2reg.dio_pads[2].d),
- .qre (),
- .qe (reg2hw.dio_pads[2].qe),
- .q (reg2hw.dio_pads[2].q ),
- .qs (dio_pads_0_attr_2_qs)
- );
-
-
- // Subregister 3 of Multireg dio_pads
- // R[dio_pads_1]: V(True)
-
- // F[attr_3]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_1_attr_3 (
- .re (dio_pads_1_attr_3_re),
- // qualified with register enable
- .we (dio_pads_1_attr_3_we & regwen_qs),
- .wd (dio_pads_1_attr_3_wd),
- .d (hw2reg.dio_pads[3].d),
- .qre (),
- .qe (reg2hw.dio_pads[3].qe),
- .q (reg2hw.dio_pads[3].q ),
- .qs (dio_pads_1_attr_3_qs)
- );
-
-
- // F[attr_4]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_1_attr_4 (
- .re (dio_pads_1_attr_4_re),
- // qualified with register enable
- .we (dio_pads_1_attr_4_we & regwen_qs),
- .wd (dio_pads_1_attr_4_wd),
- .d (hw2reg.dio_pads[4].d),
- .qre (),
- .qe (reg2hw.dio_pads[4].qe),
- .q (reg2hw.dio_pads[4].q ),
- .qs (dio_pads_1_attr_4_qs)
- );
-
-
- // F[attr_5]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_1_attr_5 (
- .re (dio_pads_1_attr_5_re),
- // qualified with register enable
- .we (dio_pads_1_attr_5_we & regwen_qs),
- .wd (dio_pads_1_attr_5_wd),
- .d (hw2reg.dio_pads[5].d),
- .qre (),
- .qe (reg2hw.dio_pads[5].qe),
- .q (reg2hw.dio_pads[5].q ),
- .qs (dio_pads_1_attr_5_qs)
- );
-
-
- // Subregister 6 of Multireg dio_pads
- // R[dio_pads_2]: V(True)
-
- // F[attr_6]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_2_attr_6 (
- .re (dio_pads_2_attr_6_re),
- // qualified with register enable
- .we (dio_pads_2_attr_6_we & regwen_qs),
- .wd (dio_pads_2_attr_6_wd),
- .d (hw2reg.dio_pads[6].d),
- .qre (),
- .qe (reg2hw.dio_pads[6].qe),
- .q (reg2hw.dio_pads[6].q ),
- .qs (dio_pads_2_attr_6_qs)
- );
-
-
- // F[attr_7]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_2_attr_7 (
- .re (dio_pads_2_attr_7_re),
- // qualified with register enable
- .we (dio_pads_2_attr_7_we & regwen_qs),
- .wd (dio_pads_2_attr_7_wd),
- .d (hw2reg.dio_pads[7].d),
- .qre (),
- .qe (reg2hw.dio_pads[7].qe),
- .q (reg2hw.dio_pads[7].q ),
- .qs (dio_pads_2_attr_7_qs)
- );
-
-
- // F[attr_8]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_2_attr_8 (
- .re (dio_pads_2_attr_8_re),
- // qualified with register enable
- .we (dio_pads_2_attr_8_we & regwen_qs),
- .wd (dio_pads_2_attr_8_wd),
- .d (hw2reg.dio_pads[8].d),
- .qre (),
- .qe (reg2hw.dio_pads[8].qe),
- .q (reg2hw.dio_pads[8].q ),
- .qs (dio_pads_2_attr_8_qs)
- );
-
-
- // Subregister 9 of Multireg dio_pads
- // R[dio_pads_3]: V(True)
-
- // F[attr_9]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_3_attr_9 (
- .re (dio_pads_3_attr_9_re),
- // qualified with register enable
- .we (dio_pads_3_attr_9_we & regwen_qs),
- .wd (dio_pads_3_attr_9_wd),
- .d (hw2reg.dio_pads[9].d),
- .qre (),
- .qe (reg2hw.dio_pads[9].qe),
- .q (reg2hw.dio_pads[9].q ),
- .qs (dio_pads_3_attr_9_qs)
- );
-
-
- // F[attr_10]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_3_attr_10 (
- .re (dio_pads_3_attr_10_re),
- // qualified with register enable
- .we (dio_pads_3_attr_10_we & regwen_qs),
- .wd (dio_pads_3_attr_10_wd),
- .d (hw2reg.dio_pads[10].d),
- .qre (),
- .qe (reg2hw.dio_pads[10].qe),
- .q (reg2hw.dio_pads[10].q ),
- .qs (dio_pads_3_attr_10_qs)
- );
-
-
- // F[attr_11]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_3_attr_11 (
- .re (dio_pads_3_attr_11_re),
- // qualified with register enable
- .we (dio_pads_3_attr_11_we & regwen_qs),
- .wd (dio_pads_3_attr_11_wd),
- .d (hw2reg.dio_pads[11].d),
- .qre (),
- .qe (reg2hw.dio_pads[11].qe),
- .q (reg2hw.dio_pads[11].q ),
- .qs (dio_pads_3_attr_11_qs)
- );
-
-
- // Subregister 12 of Multireg dio_pads
- // R[dio_pads_4]: V(True)
-
- // F[attr_12]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_4_attr_12 (
- .re (dio_pads_4_attr_12_re),
- // qualified with register enable
- .we (dio_pads_4_attr_12_we & regwen_qs),
- .wd (dio_pads_4_attr_12_wd),
- .d (hw2reg.dio_pads[12].d),
- .qre (),
- .qe (reg2hw.dio_pads[12].qe),
- .q (reg2hw.dio_pads[12].q ),
- .qs (dio_pads_4_attr_12_qs)
- );
-
-
- // F[attr_13]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_4_attr_13 (
- .re (dio_pads_4_attr_13_re),
- // qualified with register enable
- .we (dio_pads_4_attr_13_we & regwen_qs),
- .wd (dio_pads_4_attr_13_wd),
- .d (hw2reg.dio_pads[13].d),
- .qre (),
- .qe (reg2hw.dio_pads[13].qe),
- .q (reg2hw.dio_pads[13].q ),
- .qs (dio_pads_4_attr_13_qs)
- );
-
-
- // F[attr_14]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_4_attr_14 (
- .re (dio_pads_4_attr_14_re),
- // qualified with register enable
- .we (dio_pads_4_attr_14_we & regwen_qs),
- .wd (dio_pads_4_attr_14_wd),
- .d (hw2reg.dio_pads[14].d),
- .qre (),
- .qe (reg2hw.dio_pads[14].qe),
- .q (reg2hw.dio_pads[14].q ),
- .qs (dio_pads_4_attr_14_qs)
- );
-
-
- // Subregister 15 of Multireg dio_pads
- // R[dio_pads_5]: V(True)
-
- // F[attr_15]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_5_attr_15 (
- .re (dio_pads_5_attr_15_re),
- // qualified with register enable
- .we (dio_pads_5_attr_15_we & regwen_qs),
- .wd (dio_pads_5_attr_15_wd),
- .d (hw2reg.dio_pads[15].d),
- .qre (),
- .qe (reg2hw.dio_pads[15].qe),
- .q (reg2hw.dio_pads[15].q ),
- .qs (dio_pads_5_attr_15_qs)
- );
-
-
- // F[attr_16]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_5_attr_16 (
- .re (dio_pads_5_attr_16_re),
- // qualified with register enable
- .we (dio_pads_5_attr_16_we & regwen_qs),
- .wd (dio_pads_5_attr_16_wd),
- .d (hw2reg.dio_pads[16].d),
- .qre (),
- .qe (reg2hw.dio_pads[16].qe),
- .q (reg2hw.dio_pads[16].q ),
- .qs (dio_pads_5_attr_16_qs)
- );
-
-
- // F[attr_17]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_5_attr_17 (
- .re (dio_pads_5_attr_17_re),
- // qualified with register enable
- .we (dio_pads_5_attr_17_we & regwen_qs),
- .wd (dio_pads_5_attr_17_wd),
- .d (hw2reg.dio_pads[17].d),
- .qre (),
- .qe (reg2hw.dio_pads[17].qe),
- .q (reg2hw.dio_pads[17].q ),
- .qs (dio_pads_5_attr_17_qs)
- );
-
-
- // Subregister 18 of Multireg dio_pads
- // R[dio_pads_6]: V(True)
-
- // F[attr_18]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_6_attr_18 (
- .re (dio_pads_6_attr_18_re),
- // qualified with register enable
- .we (dio_pads_6_attr_18_we & regwen_qs),
- .wd (dio_pads_6_attr_18_wd),
- .d (hw2reg.dio_pads[18].d),
- .qre (),
- .qe (reg2hw.dio_pads[18].qe),
- .q (reg2hw.dio_pads[18].q ),
- .qs (dio_pads_6_attr_18_qs)
- );
-
-
- // F[attr_19]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_6_attr_19 (
- .re (dio_pads_6_attr_19_re),
- // qualified with register enable
- .we (dio_pads_6_attr_19_we & regwen_qs),
- .wd (dio_pads_6_attr_19_wd),
- .d (hw2reg.dio_pads[19].d),
- .qre (),
- .qe (reg2hw.dio_pads[19].qe),
- .q (reg2hw.dio_pads[19].q ),
- .qs (dio_pads_6_attr_19_qs)
- );
-
-
- // F[attr_20]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_dio_pads_6_attr_20 (
- .re (dio_pads_6_attr_20_re),
- // qualified with register enable
- .we (dio_pads_6_attr_20_we & regwen_qs),
- .wd (dio_pads_6_attr_20_wd),
- .d (hw2reg.dio_pads[20].d),
- .qre (),
- .qe (reg2hw.dio_pads[20].qe),
- .q (reg2hw.dio_pads[20].q ),
- .qs (dio_pads_6_attr_20_qs)
- );
-
-
-
-
- // Subregister 0 of Multireg mio_pads
- // R[mio_pads_0]: V(True)
-
- // F[attr_0]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_0_attr_0 (
- .re (mio_pads_0_attr_0_re),
- // qualified with register enable
- .we (mio_pads_0_attr_0_we & regwen_qs),
- .wd (mio_pads_0_attr_0_wd),
- .d (hw2reg.mio_pads[0].d),
- .qre (),
- .qe (reg2hw.mio_pads[0].qe),
- .q (reg2hw.mio_pads[0].q ),
- .qs (mio_pads_0_attr_0_qs)
- );
-
-
- // F[attr_1]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_0_attr_1 (
- .re (mio_pads_0_attr_1_re),
- // qualified with register enable
- .we (mio_pads_0_attr_1_we & regwen_qs),
- .wd (mio_pads_0_attr_1_wd),
- .d (hw2reg.mio_pads[1].d),
- .qre (),
- .qe (reg2hw.mio_pads[1].qe),
- .q (reg2hw.mio_pads[1].q ),
- .qs (mio_pads_0_attr_1_qs)
- );
-
-
- // F[attr_2]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_0_attr_2 (
- .re (mio_pads_0_attr_2_re),
- // qualified with register enable
- .we (mio_pads_0_attr_2_we & regwen_qs),
- .wd (mio_pads_0_attr_2_wd),
- .d (hw2reg.mio_pads[2].d),
- .qre (),
- .qe (reg2hw.mio_pads[2].qe),
- .q (reg2hw.mio_pads[2].q ),
- .qs (mio_pads_0_attr_2_qs)
- );
-
-
- // Subregister 3 of Multireg mio_pads
- // R[mio_pads_1]: V(True)
-
- // F[attr_3]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_1_attr_3 (
- .re (mio_pads_1_attr_3_re),
- // qualified with register enable
- .we (mio_pads_1_attr_3_we & regwen_qs),
- .wd (mio_pads_1_attr_3_wd),
- .d (hw2reg.mio_pads[3].d),
- .qre (),
- .qe (reg2hw.mio_pads[3].qe),
- .q (reg2hw.mio_pads[3].q ),
- .qs (mio_pads_1_attr_3_qs)
- );
-
-
- // F[attr_4]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_1_attr_4 (
- .re (mio_pads_1_attr_4_re),
- // qualified with register enable
- .we (mio_pads_1_attr_4_we & regwen_qs),
- .wd (mio_pads_1_attr_4_wd),
- .d (hw2reg.mio_pads[4].d),
- .qre (),
- .qe (reg2hw.mio_pads[4].qe),
- .q (reg2hw.mio_pads[4].q ),
- .qs (mio_pads_1_attr_4_qs)
- );
-
-
- // F[attr_5]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_1_attr_5 (
- .re (mio_pads_1_attr_5_re),
- // qualified with register enable
- .we (mio_pads_1_attr_5_we & regwen_qs),
- .wd (mio_pads_1_attr_5_wd),
- .d (hw2reg.mio_pads[5].d),
- .qre (),
- .qe (reg2hw.mio_pads[5].qe),
- .q (reg2hw.mio_pads[5].q ),
- .qs (mio_pads_1_attr_5_qs)
- );
-
-
- // Subregister 6 of Multireg mio_pads
- // R[mio_pads_2]: V(True)
-
- // F[attr_6]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_2_attr_6 (
- .re (mio_pads_2_attr_6_re),
- // qualified with register enable
- .we (mio_pads_2_attr_6_we & regwen_qs),
- .wd (mio_pads_2_attr_6_wd),
- .d (hw2reg.mio_pads[6].d),
- .qre (),
- .qe (reg2hw.mio_pads[6].qe),
- .q (reg2hw.mio_pads[6].q ),
- .qs (mio_pads_2_attr_6_qs)
- );
-
-
- // F[attr_7]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_2_attr_7 (
- .re (mio_pads_2_attr_7_re),
- // qualified with register enable
- .we (mio_pads_2_attr_7_we & regwen_qs),
- .wd (mio_pads_2_attr_7_wd),
- .d (hw2reg.mio_pads[7].d),
- .qre (),
- .qe (reg2hw.mio_pads[7].qe),
- .q (reg2hw.mio_pads[7].q ),
- .qs (mio_pads_2_attr_7_qs)
- );
-
-
- // F[attr_8]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_2_attr_8 (
- .re (mio_pads_2_attr_8_re),
- // qualified with register enable
- .we (mio_pads_2_attr_8_we & regwen_qs),
- .wd (mio_pads_2_attr_8_wd),
- .d (hw2reg.mio_pads[8].d),
- .qre (),
- .qe (reg2hw.mio_pads[8].qe),
- .q (reg2hw.mio_pads[8].q ),
- .qs (mio_pads_2_attr_8_qs)
- );
-
-
- // Subregister 9 of Multireg mio_pads
- // R[mio_pads_3]: V(True)
-
- // F[attr_9]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_3_attr_9 (
- .re (mio_pads_3_attr_9_re),
- // qualified with register enable
- .we (mio_pads_3_attr_9_we & regwen_qs),
- .wd (mio_pads_3_attr_9_wd),
- .d (hw2reg.mio_pads[9].d),
- .qre (),
- .qe (reg2hw.mio_pads[9].qe),
- .q (reg2hw.mio_pads[9].q ),
- .qs (mio_pads_3_attr_9_qs)
- );
-
-
- // F[attr_10]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_3_attr_10 (
- .re (mio_pads_3_attr_10_re),
- // qualified with register enable
- .we (mio_pads_3_attr_10_we & regwen_qs),
- .wd (mio_pads_3_attr_10_wd),
- .d (hw2reg.mio_pads[10].d),
- .qre (),
- .qe (reg2hw.mio_pads[10].qe),
- .q (reg2hw.mio_pads[10].q ),
- .qs (mio_pads_3_attr_10_qs)
- );
-
-
- // F[attr_11]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_3_attr_11 (
- .re (mio_pads_3_attr_11_re),
- // qualified with register enable
- .we (mio_pads_3_attr_11_we & regwen_qs),
- .wd (mio_pads_3_attr_11_wd),
- .d (hw2reg.mio_pads[11].d),
- .qre (),
- .qe (reg2hw.mio_pads[11].qe),
- .q (reg2hw.mio_pads[11].q ),
- .qs (mio_pads_3_attr_11_qs)
- );
-
-
- // Subregister 12 of Multireg mio_pads
- // R[mio_pads_4]: V(True)
-
- // F[attr_12]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_4_attr_12 (
- .re (mio_pads_4_attr_12_re),
- // qualified with register enable
- .we (mio_pads_4_attr_12_we & regwen_qs),
- .wd (mio_pads_4_attr_12_wd),
- .d (hw2reg.mio_pads[12].d),
- .qre (),
- .qe (reg2hw.mio_pads[12].qe),
- .q (reg2hw.mio_pads[12].q ),
- .qs (mio_pads_4_attr_12_qs)
- );
-
-
- // F[attr_13]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_4_attr_13 (
- .re (mio_pads_4_attr_13_re),
- // qualified with register enable
- .we (mio_pads_4_attr_13_we & regwen_qs),
- .wd (mio_pads_4_attr_13_wd),
- .d (hw2reg.mio_pads[13].d),
- .qre (),
- .qe (reg2hw.mio_pads[13].qe),
- .q (reg2hw.mio_pads[13].q ),
- .qs (mio_pads_4_attr_13_qs)
- );
-
-
- // F[attr_14]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_4_attr_14 (
- .re (mio_pads_4_attr_14_re),
- // qualified with register enable
- .we (mio_pads_4_attr_14_we & regwen_qs),
- .wd (mio_pads_4_attr_14_wd),
- .d (hw2reg.mio_pads[14].d),
- .qre (),
- .qe (reg2hw.mio_pads[14].qe),
- .q (reg2hw.mio_pads[14].q ),
- .qs (mio_pads_4_attr_14_qs)
- );
-
-
- // Subregister 15 of Multireg mio_pads
- // R[mio_pads_5]: V(True)
-
- // F[attr_15]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_5_attr_15 (
- .re (mio_pads_5_attr_15_re),
- // qualified with register enable
- .we (mio_pads_5_attr_15_we & regwen_qs),
- .wd (mio_pads_5_attr_15_wd),
- .d (hw2reg.mio_pads[15].d),
- .qre (),
- .qe (reg2hw.mio_pads[15].qe),
- .q (reg2hw.mio_pads[15].q ),
- .qs (mio_pads_5_attr_15_qs)
- );
-
-
- // F[attr_16]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_5_attr_16 (
- .re (mio_pads_5_attr_16_re),
- // qualified with register enable
- .we (mio_pads_5_attr_16_we & regwen_qs),
- .wd (mio_pads_5_attr_16_wd),
- .d (hw2reg.mio_pads[16].d),
- .qre (),
- .qe (reg2hw.mio_pads[16].qe),
- .q (reg2hw.mio_pads[16].q ),
- .qs (mio_pads_5_attr_16_qs)
- );
-
-
- // F[attr_17]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_5_attr_17 (
- .re (mio_pads_5_attr_17_re),
- // qualified with register enable
- .we (mio_pads_5_attr_17_we & regwen_qs),
- .wd (mio_pads_5_attr_17_wd),
- .d (hw2reg.mio_pads[17].d),
- .qre (),
- .qe (reg2hw.mio_pads[17].qe),
- .q (reg2hw.mio_pads[17].q ),
- .qs (mio_pads_5_attr_17_qs)
- );
-
-
- // Subregister 18 of Multireg mio_pads
- // R[mio_pads_6]: V(True)
-
- // F[attr_18]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_6_attr_18 (
- .re (mio_pads_6_attr_18_re),
- // qualified with register enable
- .we (mio_pads_6_attr_18_we & regwen_qs),
- .wd (mio_pads_6_attr_18_wd),
- .d (hw2reg.mio_pads[18].d),
- .qre (),
- .qe (reg2hw.mio_pads[18].qe),
- .q (reg2hw.mio_pads[18].q ),
- .qs (mio_pads_6_attr_18_qs)
- );
-
-
- // F[attr_19]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_6_attr_19 (
- .re (mio_pads_6_attr_19_re),
- // qualified with register enable
- .we (mio_pads_6_attr_19_we & regwen_qs),
- .wd (mio_pads_6_attr_19_wd),
- .d (hw2reg.mio_pads[19].d),
- .qre (),
- .qe (reg2hw.mio_pads[19].qe),
- .q (reg2hw.mio_pads[19].q ),
- .qs (mio_pads_6_attr_19_qs)
- );
-
-
- // F[attr_20]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_6_attr_20 (
- .re (mio_pads_6_attr_20_re),
- // qualified with register enable
- .we (mio_pads_6_attr_20_we & regwen_qs),
- .wd (mio_pads_6_attr_20_wd),
- .d (hw2reg.mio_pads[20].d),
- .qre (),
- .qe (reg2hw.mio_pads[20].qe),
- .q (reg2hw.mio_pads[20].q ),
- .qs (mio_pads_6_attr_20_qs)
- );
-
-
- // Subregister 21 of Multireg mio_pads
- // R[mio_pads_7]: V(True)
-
- // F[attr_21]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_7_attr_21 (
- .re (mio_pads_7_attr_21_re),
- // qualified with register enable
- .we (mio_pads_7_attr_21_we & regwen_qs),
- .wd (mio_pads_7_attr_21_wd),
- .d (hw2reg.mio_pads[21].d),
- .qre (),
- .qe (reg2hw.mio_pads[21].qe),
- .q (reg2hw.mio_pads[21].q ),
- .qs (mio_pads_7_attr_21_qs)
- );
-
-
- // F[attr_22]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_7_attr_22 (
- .re (mio_pads_7_attr_22_re),
- // qualified with register enable
- .we (mio_pads_7_attr_22_we & regwen_qs),
- .wd (mio_pads_7_attr_22_wd),
- .d (hw2reg.mio_pads[22].d),
- .qre (),
- .qe (reg2hw.mio_pads[22].qe),
- .q (reg2hw.mio_pads[22].q ),
- .qs (mio_pads_7_attr_22_qs)
- );
-
-
- // F[attr_23]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_7_attr_23 (
- .re (mio_pads_7_attr_23_re),
- // qualified with register enable
- .we (mio_pads_7_attr_23_we & regwen_qs),
- .wd (mio_pads_7_attr_23_wd),
- .d (hw2reg.mio_pads[23].d),
- .qre (),
- .qe (reg2hw.mio_pads[23].qe),
- .q (reg2hw.mio_pads[23].q ),
- .qs (mio_pads_7_attr_23_qs)
- );
-
-
- // Subregister 24 of Multireg mio_pads
- // R[mio_pads_8]: V(True)
-
- // F[attr_24]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_8_attr_24 (
- .re (mio_pads_8_attr_24_re),
- // qualified with register enable
- .we (mio_pads_8_attr_24_we & regwen_qs),
- .wd (mio_pads_8_attr_24_wd),
- .d (hw2reg.mio_pads[24].d),
- .qre (),
- .qe (reg2hw.mio_pads[24].qe),
- .q (reg2hw.mio_pads[24].q ),
- .qs (mio_pads_8_attr_24_qs)
- );
-
-
- // F[attr_25]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_8_attr_25 (
- .re (mio_pads_8_attr_25_re),
- // qualified with register enable
- .we (mio_pads_8_attr_25_we & regwen_qs),
- .wd (mio_pads_8_attr_25_wd),
- .d (hw2reg.mio_pads[25].d),
- .qre (),
- .qe (reg2hw.mio_pads[25].qe),
- .q (reg2hw.mio_pads[25].q ),
- .qs (mio_pads_8_attr_25_qs)
- );
-
-
- // F[attr_26]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_8_attr_26 (
- .re (mio_pads_8_attr_26_re),
- // qualified with register enable
- .we (mio_pads_8_attr_26_we & regwen_qs),
- .wd (mio_pads_8_attr_26_wd),
- .d (hw2reg.mio_pads[26].d),
- .qre (),
- .qe (reg2hw.mio_pads[26].qe),
- .q (reg2hw.mio_pads[26].q ),
- .qs (mio_pads_8_attr_26_qs)
- );
-
-
- // Subregister 27 of Multireg mio_pads
- // R[mio_pads_9]: V(True)
-
- // F[attr_27]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_9_attr_27 (
- .re (mio_pads_9_attr_27_re),
- // qualified with register enable
- .we (mio_pads_9_attr_27_we & regwen_qs),
- .wd (mio_pads_9_attr_27_wd),
- .d (hw2reg.mio_pads[27].d),
- .qre (),
- .qe (reg2hw.mio_pads[27].qe),
- .q (reg2hw.mio_pads[27].q ),
- .qs (mio_pads_9_attr_27_qs)
- );
-
-
- // F[attr_28]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_9_attr_28 (
- .re (mio_pads_9_attr_28_re),
- // qualified with register enable
- .we (mio_pads_9_attr_28_we & regwen_qs),
- .wd (mio_pads_9_attr_28_wd),
- .d (hw2reg.mio_pads[28].d),
- .qre (),
- .qe (reg2hw.mio_pads[28].qe),
- .q (reg2hw.mio_pads[28].q ),
- .qs (mio_pads_9_attr_28_qs)
- );
-
-
- // F[attr_29]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_9_attr_29 (
- .re (mio_pads_9_attr_29_re),
- // qualified with register enable
- .we (mio_pads_9_attr_29_we & regwen_qs),
- .wd (mio_pads_9_attr_29_wd),
- .d (hw2reg.mio_pads[29].d),
- .qre (),
- .qe (reg2hw.mio_pads[29].qe),
- .q (reg2hw.mio_pads[29].q ),
- .qs (mio_pads_9_attr_29_qs)
- );
-
-
- // Subregister 30 of Multireg mio_pads
- // R[mio_pads_10]: V(True)
-
- // F[attr_30]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_10_attr_30 (
- .re (mio_pads_10_attr_30_re),
- // qualified with register enable
- .we (mio_pads_10_attr_30_we & regwen_qs),
- .wd (mio_pads_10_attr_30_wd),
- .d (hw2reg.mio_pads[30].d),
- .qre (),
- .qe (reg2hw.mio_pads[30].qe),
- .q (reg2hw.mio_pads[30].q ),
- .qs (mio_pads_10_attr_30_qs)
- );
-
-
- // F[attr_31]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_10_attr_31 (
- .re (mio_pads_10_attr_31_re),
- // qualified with register enable
- .we (mio_pads_10_attr_31_we & regwen_qs),
- .wd (mio_pads_10_attr_31_wd),
- .d (hw2reg.mio_pads[31].d),
- .qre (),
- .qe (reg2hw.mio_pads[31].qe),
- .q (reg2hw.mio_pads[31].q ),
- .qs (mio_pads_10_attr_31_qs)
- );
-
-
- // F[attr_32]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_10_attr_32 (
- .re (mio_pads_10_attr_32_re),
- // qualified with register enable
- .we (mio_pads_10_attr_32_we & regwen_qs),
- .wd (mio_pads_10_attr_32_wd),
- .d (hw2reg.mio_pads[32].d),
- .qre (),
- .qe (reg2hw.mio_pads[32].qe),
- .q (reg2hw.mio_pads[32].q ),
- .qs (mio_pads_10_attr_32_qs)
- );
-
-
- // Subregister 33 of Multireg mio_pads
- // R[mio_pads_11]: V(True)
-
- // F[attr_33]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_11_attr_33 (
- .re (mio_pads_11_attr_33_re),
- // qualified with register enable
- .we (mio_pads_11_attr_33_we & regwen_qs),
- .wd (mio_pads_11_attr_33_wd),
- .d (hw2reg.mio_pads[33].d),
- .qre (),
- .qe (reg2hw.mio_pads[33].qe),
- .q (reg2hw.mio_pads[33].q ),
- .qs (mio_pads_11_attr_33_qs)
- );
-
-
- // F[attr_34]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_11_attr_34 (
- .re (mio_pads_11_attr_34_re),
- // qualified with register enable
- .we (mio_pads_11_attr_34_we & regwen_qs),
- .wd (mio_pads_11_attr_34_wd),
- .d (hw2reg.mio_pads[34].d),
- .qre (),
- .qe (reg2hw.mio_pads[34].qe),
- .q (reg2hw.mio_pads[34].q ),
- .qs (mio_pads_11_attr_34_qs)
- );
-
-
- // F[attr_35]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_11_attr_35 (
- .re (mio_pads_11_attr_35_re),
- // qualified with register enable
- .we (mio_pads_11_attr_35_we & regwen_qs),
- .wd (mio_pads_11_attr_35_wd),
- .d (hw2reg.mio_pads[35].d),
- .qre (),
- .qe (reg2hw.mio_pads[35].qe),
- .q (reg2hw.mio_pads[35].q ),
- .qs (mio_pads_11_attr_35_qs)
- );
-
-
- // Subregister 36 of Multireg mio_pads
- // R[mio_pads_12]: V(True)
-
- // F[attr_36]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_12_attr_36 (
- .re (mio_pads_12_attr_36_re),
- // qualified with register enable
- .we (mio_pads_12_attr_36_we & regwen_qs),
- .wd (mio_pads_12_attr_36_wd),
- .d (hw2reg.mio_pads[36].d),
- .qre (),
- .qe (reg2hw.mio_pads[36].qe),
- .q (reg2hw.mio_pads[36].q ),
- .qs (mio_pads_12_attr_36_qs)
- );
-
-
- // F[attr_37]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_12_attr_37 (
- .re (mio_pads_12_attr_37_re),
- // qualified with register enable
- .we (mio_pads_12_attr_37_we & regwen_qs),
- .wd (mio_pads_12_attr_37_wd),
- .d (hw2reg.mio_pads[37].d),
- .qre (),
- .qe (reg2hw.mio_pads[37].qe),
- .q (reg2hw.mio_pads[37].q ),
- .qs (mio_pads_12_attr_37_qs)
- );
-
-
- // F[attr_38]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_12_attr_38 (
- .re (mio_pads_12_attr_38_re),
- // qualified with register enable
- .we (mio_pads_12_attr_38_we & regwen_qs),
- .wd (mio_pads_12_attr_38_wd),
- .d (hw2reg.mio_pads[38].d),
- .qre (),
- .qe (reg2hw.mio_pads[38].qe),
- .q (reg2hw.mio_pads[38].q ),
- .qs (mio_pads_12_attr_38_qs)
- );
-
-
- // Subregister 39 of Multireg mio_pads
- // R[mio_pads_13]: V(True)
-
- // F[attr_39]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_13_attr_39 (
- .re (mio_pads_13_attr_39_re),
- // qualified with register enable
- .we (mio_pads_13_attr_39_we & regwen_qs),
- .wd (mio_pads_13_attr_39_wd),
- .d (hw2reg.mio_pads[39].d),
- .qre (),
- .qe (reg2hw.mio_pads[39].qe),
- .q (reg2hw.mio_pads[39].q ),
- .qs (mio_pads_13_attr_39_qs)
- );
-
-
- // F[attr_40]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_13_attr_40 (
- .re (mio_pads_13_attr_40_re),
- // qualified with register enable
- .we (mio_pads_13_attr_40_we & regwen_qs),
- .wd (mio_pads_13_attr_40_wd),
- .d (hw2reg.mio_pads[40].d),
- .qre (),
- .qe (reg2hw.mio_pads[40].qe),
- .q (reg2hw.mio_pads[40].q ),
- .qs (mio_pads_13_attr_40_qs)
- );
-
-
- // F[attr_41]: 29:20
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_13_attr_41 (
- .re (mio_pads_13_attr_41_re),
- // qualified with register enable
- .we (mio_pads_13_attr_41_we & regwen_qs),
- .wd (mio_pads_13_attr_41_wd),
- .d (hw2reg.mio_pads[41].d),
- .qre (),
- .qe (reg2hw.mio_pads[41].qe),
- .q (reg2hw.mio_pads[41].q ),
- .qs (mio_pads_13_attr_41_qs)
- );
-
-
- // Subregister 42 of Multireg mio_pads
- // R[mio_pads_14]: V(True)
-
- // F[attr_42]: 9:0
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_14_attr_42 (
- .re (mio_pads_14_attr_42_re),
- // qualified with register enable
- .we (mio_pads_14_attr_42_we & regwen_qs),
- .wd (mio_pads_14_attr_42_wd),
- .d (hw2reg.mio_pads[42].d),
- .qre (),
- .qe (reg2hw.mio_pads[42].qe),
- .q (reg2hw.mio_pads[42].q ),
- .qs (mio_pads_14_attr_42_qs)
- );
-
-
- // F[attr_43]: 19:10
- prim_subreg_ext #(
- .DW (10)
- ) u_mio_pads_14_attr_43 (
- .re (mio_pads_14_attr_43_re),
- // qualified with register enable
- .we (mio_pads_14_attr_43_we & regwen_qs),
- .wd (mio_pads_14_attr_43_wd),
- .d (hw2reg.mio_pads[43].d),
- .qre (),
- .qe (reg2hw.mio_pads[43].qe),
- .q (reg2hw.mio_pads[43].q ),
- .qs (mio_pads_14_attr_43_qs)
- );
-
-
-
-
-
- logic [22:0] addr_hit;
- always_comb begin
- addr_hit = '0;
- addr_hit[ 0] = (reg_addr == PADCTRL_REGWEN_OFFSET);
- addr_hit[ 1] = (reg_addr == PADCTRL_DIO_PADS_0_OFFSET);
- addr_hit[ 2] = (reg_addr == PADCTRL_DIO_PADS_1_OFFSET);
- addr_hit[ 3] = (reg_addr == PADCTRL_DIO_PADS_2_OFFSET);
- addr_hit[ 4] = (reg_addr == PADCTRL_DIO_PADS_3_OFFSET);
- addr_hit[ 5] = (reg_addr == PADCTRL_DIO_PADS_4_OFFSET);
- addr_hit[ 6] = (reg_addr == PADCTRL_DIO_PADS_5_OFFSET);
- addr_hit[ 7] = (reg_addr == PADCTRL_DIO_PADS_6_OFFSET);
- addr_hit[ 8] = (reg_addr == PADCTRL_MIO_PADS_0_OFFSET);
- addr_hit[ 9] = (reg_addr == PADCTRL_MIO_PADS_1_OFFSET);
- addr_hit[10] = (reg_addr == PADCTRL_MIO_PADS_2_OFFSET);
- addr_hit[11] = (reg_addr == PADCTRL_MIO_PADS_3_OFFSET);
- addr_hit[12] = (reg_addr == PADCTRL_MIO_PADS_4_OFFSET);
- addr_hit[13] = (reg_addr == PADCTRL_MIO_PADS_5_OFFSET);
- addr_hit[14] = (reg_addr == PADCTRL_MIO_PADS_6_OFFSET);
- addr_hit[15] = (reg_addr == PADCTRL_MIO_PADS_7_OFFSET);
- addr_hit[16] = (reg_addr == PADCTRL_MIO_PADS_8_OFFSET);
- addr_hit[17] = (reg_addr == PADCTRL_MIO_PADS_9_OFFSET);
- addr_hit[18] = (reg_addr == PADCTRL_MIO_PADS_10_OFFSET);
- addr_hit[19] = (reg_addr == PADCTRL_MIO_PADS_11_OFFSET);
- addr_hit[20] = (reg_addr == PADCTRL_MIO_PADS_12_OFFSET);
- addr_hit[21] = (reg_addr == PADCTRL_MIO_PADS_13_OFFSET);
- addr_hit[22] = (reg_addr == PADCTRL_MIO_PADS_14_OFFSET);
- end
-
- assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-
- // Check sub-word write is permitted
- always_comb begin
- wr_err = 1'b0;
- if (addr_hit[ 0] && reg_we && (PADCTRL_PERMIT[ 0] != (PADCTRL_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 1] && reg_we && (PADCTRL_PERMIT[ 1] != (PADCTRL_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 2] && reg_we && (PADCTRL_PERMIT[ 2] != (PADCTRL_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 3] && reg_we && (PADCTRL_PERMIT[ 3] != (PADCTRL_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 4] && reg_we && (PADCTRL_PERMIT[ 4] != (PADCTRL_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 5] && reg_we && (PADCTRL_PERMIT[ 5] != (PADCTRL_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 6] && reg_we && (PADCTRL_PERMIT[ 6] != (PADCTRL_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 7] && reg_we && (PADCTRL_PERMIT[ 7] != (PADCTRL_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 8] && reg_we && (PADCTRL_PERMIT[ 8] != (PADCTRL_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[ 9] && reg_we && (PADCTRL_PERMIT[ 9] != (PADCTRL_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[10] && reg_we && (PADCTRL_PERMIT[10] != (PADCTRL_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[11] && reg_we && (PADCTRL_PERMIT[11] != (PADCTRL_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[12] && reg_we && (PADCTRL_PERMIT[12] != (PADCTRL_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[13] && reg_we && (PADCTRL_PERMIT[13] != (PADCTRL_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[14] && reg_we && (PADCTRL_PERMIT[14] != (PADCTRL_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[15] && reg_we && (PADCTRL_PERMIT[15] != (PADCTRL_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[16] && reg_we && (PADCTRL_PERMIT[16] != (PADCTRL_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[17] && reg_we && (PADCTRL_PERMIT[17] != (PADCTRL_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[18] && reg_we && (PADCTRL_PERMIT[18] != (PADCTRL_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[19] && reg_we && (PADCTRL_PERMIT[19] != (PADCTRL_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[20] && reg_we && (PADCTRL_PERMIT[20] != (PADCTRL_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[21] && reg_we && (PADCTRL_PERMIT[21] != (PADCTRL_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[22] && reg_we && (PADCTRL_PERMIT[22] != (PADCTRL_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
- end
-
- assign regwen_we = addr_hit[0] & reg_we & ~wr_err;
- assign regwen_wd = reg_wdata[0];
-
- assign dio_pads_0_attr_0_we = addr_hit[1] & reg_we & ~wr_err;
- assign dio_pads_0_attr_0_wd = reg_wdata[9:0];
- assign dio_pads_0_attr_0_re = addr_hit[1] && reg_re;
-
- assign dio_pads_0_attr_1_we = addr_hit[1] & reg_we & ~wr_err;
- assign dio_pads_0_attr_1_wd = reg_wdata[19:10];
- assign dio_pads_0_attr_1_re = addr_hit[1] && reg_re;
-
- assign dio_pads_0_attr_2_we = addr_hit[1] & reg_we & ~wr_err;
- assign dio_pads_0_attr_2_wd = reg_wdata[29:20];
- assign dio_pads_0_attr_2_re = addr_hit[1] && reg_re;
-
- assign dio_pads_1_attr_3_we = addr_hit[2] & reg_we & ~wr_err;
- assign dio_pads_1_attr_3_wd = reg_wdata[9:0];
- assign dio_pads_1_attr_3_re = addr_hit[2] && reg_re;
-
- assign dio_pads_1_attr_4_we = addr_hit[2] & reg_we & ~wr_err;
- assign dio_pads_1_attr_4_wd = reg_wdata[19:10];
- assign dio_pads_1_attr_4_re = addr_hit[2] && reg_re;
-
- assign dio_pads_1_attr_5_we = addr_hit[2] & reg_we & ~wr_err;
- assign dio_pads_1_attr_5_wd = reg_wdata[29:20];
- assign dio_pads_1_attr_5_re = addr_hit[2] && reg_re;
-
- assign dio_pads_2_attr_6_we = addr_hit[3] & reg_we & ~wr_err;
- assign dio_pads_2_attr_6_wd = reg_wdata[9:0];
- assign dio_pads_2_attr_6_re = addr_hit[3] && reg_re;
-
- assign dio_pads_2_attr_7_we = addr_hit[3] & reg_we & ~wr_err;
- assign dio_pads_2_attr_7_wd = reg_wdata[19:10];
- assign dio_pads_2_attr_7_re = addr_hit[3] && reg_re;
-
- assign dio_pads_2_attr_8_we = addr_hit[3] & reg_we & ~wr_err;
- assign dio_pads_2_attr_8_wd = reg_wdata[29:20];
- assign dio_pads_2_attr_8_re = addr_hit[3] && reg_re;
-
- assign dio_pads_3_attr_9_we = addr_hit[4] & reg_we & ~wr_err;
- assign dio_pads_3_attr_9_wd = reg_wdata[9:0];
- assign dio_pads_3_attr_9_re = addr_hit[4] && reg_re;
-
- assign dio_pads_3_attr_10_we = addr_hit[4] & reg_we & ~wr_err;
- assign dio_pads_3_attr_10_wd = reg_wdata[19:10];
- assign dio_pads_3_attr_10_re = addr_hit[4] && reg_re;
-
- assign dio_pads_3_attr_11_we = addr_hit[4] & reg_we & ~wr_err;
- assign dio_pads_3_attr_11_wd = reg_wdata[29:20];
- assign dio_pads_3_attr_11_re = addr_hit[4] && reg_re;
-
- assign dio_pads_4_attr_12_we = addr_hit[5] & reg_we & ~wr_err;
- assign dio_pads_4_attr_12_wd = reg_wdata[9:0];
- assign dio_pads_4_attr_12_re = addr_hit[5] && reg_re;
-
- assign dio_pads_4_attr_13_we = addr_hit[5] & reg_we & ~wr_err;
- assign dio_pads_4_attr_13_wd = reg_wdata[19:10];
- assign dio_pads_4_attr_13_re = addr_hit[5] && reg_re;
-
- assign dio_pads_4_attr_14_we = addr_hit[5] & reg_we & ~wr_err;
- assign dio_pads_4_attr_14_wd = reg_wdata[29:20];
- assign dio_pads_4_attr_14_re = addr_hit[5] && reg_re;
-
- assign dio_pads_5_attr_15_we = addr_hit[6] & reg_we & ~wr_err;
- assign dio_pads_5_attr_15_wd = reg_wdata[9:0];
- assign dio_pads_5_attr_15_re = addr_hit[6] && reg_re;
-
- assign dio_pads_5_attr_16_we = addr_hit[6] & reg_we & ~wr_err;
- assign dio_pads_5_attr_16_wd = reg_wdata[19:10];
- assign dio_pads_5_attr_16_re = addr_hit[6] && reg_re;
-
- assign dio_pads_5_attr_17_we = addr_hit[6] & reg_we & ~wr_err;
- assign dio_pads_5_attr_17_wd = reg_wdata[29:20];
- assign dio_pads_5_attr_17_re = addr_hit[6] && reg_re;
-
- assign dio_pads_6_attr_18_we = addr_hit[7] & reg_we & ~wr_err;
- assign dio_pads_6_attr_18_wd = reg_wdata[9:0];
- assign dio_pads_6_attr_18_re = addr_hit[7] && reg_re;
-
- assign dio_pads_6_attr_19_we = addr_hit[7] & reg_we & ~wr_err;
- assign dio_pads_6_attr_19_wd = reg_wdata[19:10];
- assign dio_pads_6_attr_19_re = addr_hit[7] && reg_re;
-
- assign dio_pads_6_attr_20_we = addr_hit[7] & reg_we & ~wr_err;
- assign dio_pads_6_attr_20_wd = reg_wdata[29:20];
- assign dio_pads_6_attr_20_re = addr_hit[7] && reg_re;
-
- assign mio_pads_0_attr_0_we = addr_hit[8] & reg_we & ~wr_err;
- assign mio_pads_0_attr_0_wd = reg_wdata[9:0];
- assign mio_pads_0_attr_0_re = addr_hit[8] && reg_re;
-
- assign mio_pads_0_attr_1_we = addr_hit[8] & reg_we & ~wr_err;
- assign mio_pads_0_attr_1_wd = reg_wdata[19:10];
- assign mio_pads_0_attr_1_re = addr_hit[8] && reg_re;
-
- assign mio_pads_0_attr_2_we = addr_hit[8] & reg_we & ~wr_err;
- assign mio_pads_0_attr_2_wd = reg_wdata[29:20];
- assign mio_pads_0_attr_2_re = addr_hit[8] && reg_re;
-
- assign mio_pads_1_attr_3_we = addr_hit[9] & reg_we & ~wr_err;
- assign mio_pads_1_attr_3_wd = reg_wdata[9:0];
- assign mio_pads_1_attr_3_re = addr_hit[9] && reg_re;
-
- assign mio_pads_1_attr_4_we = addr_hit[9] & reg_we & ~wr_err;
- assign mio_pads_1_attr_4_wd = reg_wdata[19:10];
- assign mio_pads_1_attr_4_re = addr_hit[9] && reg_re;
-
- assign mio_pads_1_attr_5_we = addr_hit[9] & reg_we & ~wr_err;
- assign mio_pads_1_attr_5_wd = reg_wdata[29:20];
- assign mio_pads_1_attr_5_re = addr_hit[9] && reg_re;
-
- assign mio_pads_2_attr_6_we = addr_hit[10] & reg_we & ~wr_err;
- assign mio_pads_2_attr_6_wd = reg_wdata[9:0];
- assign mio_pads_2_attr_6_re = addr_hit[10] && reg_re;
-
- assign mio_pads_2_attr_7_we = addr_hit[10] & reg_we & ~wr_err;
- assign mio_pads_2_attr_7_wd = reg_wdata[19:10];
- assign mio_pads_2_attr_7_re = addr_hit[10] && reg_re;
-
- assign mio_pads_2_attr_8_we = addr_hit[10] & reg_we & ~wr_err;
- assign mio_pads_2_attr_8_wd = reg_wdata[29:20];
- assign mio_pads_2_attr_8_re = addr_hit[10] && reg_re;
-
- assign mio_pads_3_attr_9_we = addr_hit[11] & reg_we & ~wr_err;
- assign mio_pads_3_attr_9_wd = reg_wdata[9:0];
- assign mio_pads_3_attr_9_re = addr_hit[11] && reg_re;
-
- assign mio_pads_3_attr_10_we = addr_hit[11] & reg_we & ~wr_err;
- assign mio_pads_3_attr_10_wd = reg_wdata[19:10];
- assign mio_pads_3_attr_10_re = addr_hit[11] && reg_re;
-
- assign mio_pads_3_attr_11_we = addr_hit[11] & reg_we & ~wr_err;
- assign mio_pads_3_attr_11_wd = reg_wdata[29:20];
- assign mio_pads_3_attr_11_re = addr_hit[11] && reg_re;
-
- assign mio_pads_4_attr_12_we = addr_hit[12] & reg_we & ~wr_err;
- assign mio_pads_4_attr_12_wd = reg_wdata[9:0];
- assign mio_pads_4_attr_12_re = addr_hit[12] && reg_re;
-
- assign mio_pads_4_attr_13_we = addr_hit[12] & reg_we & ~wr_err;
- assign mio_pads_4_attr_13_wd = reg_wdata[19:10];
- assign mio_pads_4_attr_13_re = addr_hit[12] && reg_re;
-
- assign mio_pads_4_attr_14_we = addr_hit[12] & reg_we & ~wr_err;
- assign mio_pads_4_attr_14_wd = reg_wdata[29:20];
- assign mio_pads_4_attr_14_re = addr_hit[12] && reg_re;
-
- assign mio_pads_5_attr_15_we = addr_hit[13] & reg_we & ~wr_err;
- assign mio_pads_5_attr_15_wd = reg_wdata[9:0];
- assign mio_pads_5_attr_15_re = addr_hit[13] && reg_re;
-
- assign mio_pads_5_attr_16_we = addr_hit[13] & reg_we & ~wr_err;
- assign mio_pads_5_attr_16_wd = reg_wdata[19:10];
- assign mio_pads_5_attr_16_re = addr_hit[13] && reg_re;
-
- assign mio_pads_5_attr_17_we = addr_hit[13] & reg_we & ~wr_err;
- assign mio_pads_5_attr_17_wd = reg_wdata[29:20];
- assign mio_pads_5_attr_17_re = addr_hit[13] && reg_re;
-
- assign mio_pads_6_attr_18_we = addr_hit[14] & reg_we & ~wr_err;
- assign mio_pads_6_attr_18_wd = reg_wdata[9:0];
- assign mio_pads_6_attr_18_re = addr_hit[14] && reg_re;
-
- assign mio_pads_6_attr_19_we = addr_hit[14] & reg_we & ~wr_err;
- assign mio_pads_6_attr_19_wd = reg_wdata[19:10];
- assign mio_pads_6_attr_19_re = addr_hit[14] && reg_re;
-
- assign mio_pads_6_attr_20_we = addr_hit[14] & reg_we & ~wr_err;
- assign mio_pads_6_attr_20_wd = reg_wdata[29:20];
- assign mio_pads_6_attr_20_re = addr_hit[14] && reg_re;
-
- assign mio_pads_7_attr_21_we = addr_hit[15] & reg_we & ~wr_err;
- assign mio_pads_7_attr_21_wd = reg_wdata[9:0];
- assign mio_pads_7_attr_21_re = addr_hit[15] && reg_re;
-
- assign mio_pads_7_attr_22_we = addr_hit[15] & reg_we & ~wr_err;
- assign mio_pads_7_attr_22_wd = reg_wdata[19:10];
- assign mio_pads_7_attr_22_re = addr_hit[15] && reg_re;
-
- assign mio_pads_7_attr_23_we = addr_hit[15] & reg_we & ~wr_err;
- assign mio_pads_7_attr_23_wd = reg_wdata[29:20];
- assign mio_pads_7_attr_23_re = addr_hit[15] && reg_re;
-
- assign mio_pads_8_attr_24_we = addr_hit[16] & reg_we & ~wr_err;
- assign mio_pads_8_attr_24_wd = reg_wdata[9:0];
- assign mio_pads_8_attr_24_re = addr_hit[16] && reg_re;
-
- assign mio_pads_8_attr_25_we = addr_hit[16] & reg_we & ~wr_err;
- assign mio_pads_8_attr_25_wd = reg_wdata[19:10];
- assign mio_pads_8_attr_25_re = addr_hit[16] && reg_re;
-
- assign mio_pads_8_attr_26_we = addr_hit[16] & reg_we & ~wr_err;
- assign mio_pads_8_attr_26_wd = reg_wdata[29:20];
- assign mio_pads_8_attr_26_re = addr_hit[16] && reg_re;
-
- assign mio_pads_9_attr_27_we = addr_hit[17] & reg_we & ~wr_err;
- assign mio_pads_9_attr_27_wd = reg_wdata[9:0];
- assign mio_pads_9_attr_27_re = addr_hit[17] && reg_re;
-
- assign mio_pads_9_attr_28_we = addr_hit[17] & reg_we & ~wr_err;
- assign mio_pads_9_attr_28_wd = reg_wdata[19:10];
- assign mio_pads_9_attr_28_re = addr_hit[17] && reg_re;
-
- assign mio_pads_9_attr_29_we = addr_hit[17] & reg_we & ~wr_err;
- assign mio_pads_9_attr_29_wd = reg_wdata[29:20];
- assign mio_pads_9_attr_29_re = addr_hit[17] && reg_re;
-
- assign mio_pads_10_attr_30_we = addr_hit[18] & reg_we & ~wr_err;
- assign mio_pads_10_attr_30_wd = reg_wdata[9:0];
- assign mio_pads_10_attr_30_re = addr_hit[18] && reg_re;
-
- assign mio_pads_10_attr_31_we = addr_hit[18] & reg_we & ~wr_err;
- assign mio_pads_10_attr_31_wd = reg_wdata[19:10];
- assign mio_pads_10_attr_31_re = addr_hit[18] && reg_re;
-
- assign mio_pads_10_attr_32_we = addr_hit[18] & reg_we & ~wr_err;
- assign mio_pads_10_attr_32_wd = reg_wdata[29:20];
- assign mio_pads_10_attr_32_re = addr_hit[18] && reg_re;
-
- assign mio_pads_11_attr_33_we = addr_hit[19] & reg_we & ~wr_err;
- assign mio_pads_11_attr_33_wd = reg_wdata[9:0];
- assign mio_pads_11_attr_33_re = addr_hit[19] && reg_re;
-
- assign mio_pads_11_attr_34_we = addr_hit[19] & reg_we & ~wr_err;
- assign mio_pads_11_attr_34_wd = reg_wdata[19:10];
- assign mio_pads_11_attr_34_re = addr_hit[19] && reg_re;
-
- assign mio_pads_11_attr_35_we = addr_hit[19] & reg_we & ~wr_err;
- assign mio_pads_11_attr_35_wd = reg_wdata[29:20];
- assign mio_pads_11_attr_35_re = addr_hit[19] && reg_re;
-
- assign mio_pads_12_attr_36_we = addr_hit[20] & reg_we & ~wr_err;
- assign mio_pads_12_attr_36_wd = reg_wdata[9:0];
- assign mio_pads_12_attr_36_re = addr_hit[20] && reg_re;
-
- assign mio_pads_12_attr_37_we = addr_hit[20] & reg_we & ~wr_err;
- assign mio_pads_12_attr_37_wd = reg_wdata[19:10];
- assign mio_pads_12_attr_37_re = addr_hit[20] && reg_re;
-
- assign mio_pads_12_attr_38_we = addr_hit[20] & reg_we & ~wr_err;
- assign mio_pads_12_attr_38_wd = reg_wdata[29:20];
- assign mio_pads_12_attr_38_re = addr_hit[20] && reg_re;
-
- assign mio_pads_13_attr_39_we = addr_hit[21] & reg_we & ~wr_err;
- assign mio_pads_13_attr_39_wd = reg_wdata[9:0];
- assign mio_pads_13_attr_39_re = addr_hit[21] && reg_re;
-
- assign mio_pads_13_attr_40_we = addr_hit[21] & reg_we & ~wr_err;
- assign mio_pads_13_attr_40_wd = reg_wdata[19:10];
- assign mio_pads_13_attr_40_re = addr_hit[21] && reg_re;
-
- assign mio_pads_13_attr_41_we = addr_hit[21] & reg_we & ~wr_err;
- assign mio_pads_13_attr_41_wd = reg_wdata[29:20];
- assign mio_pads_13_attr_41_re = addr_hit[21] && reg_re;
-
- assign mio_pads_14_attr_42_we = addr_hit[22] & reg_we & ~wr_err;
- assign mio_pads_14_attr_42_wd = reg_wdata[9:0];
- assign mio_pads_14_attr_42_re = addr_hit[22] && reg_re;
-
- assign mio_pads_14_attr_43_we = addr_hit[22] & reg_we & ~wr_err;
- assign mio_pads_14_attr_43_wd = reg_wdata[19:10];
- assign mio_pads_14_attr_43_re = addr_hit[22] && reg_re;
-
- // Read data return
- always_comb begin
- reg_rdata_next = '0;
- unique case (1'b1)
- addr_hit[0]: begin
- reg_rdata_next[0] = regwen_qs;
- end
-
- addr_hit[1]: begin
- reg_rdata_next[9:0] = dio_pads_0_attr_0_qs;
- reg_rdata_next[19:10] = dio_pads_0_attr_1_qs;
- reg_rdata_next[29:20] = dio_pads_0_attr_2_qs;
- end
-
- addr_hit[2]: begin
- reg_rdata_next[9:0] = dio_pads_1_attr_3_qs;
- reg_rdata_next[19:10] = dio_pads_1_attr_4_qs;
- reg_rdata_next[29:20] = dio_pads_1_attr_5_qs;
- end
-
- addr_hit[3]: begin
- reg_rdata_next[9:0] = dio_pads_2_attr_6_qs;
- reg_rdata_next[19:10] = dio_pads_2_attr_7_qs;
- reg_rdata_next[29:20] = dio_pads_2_attr_8_qs;
- end
-
- addr_hit[4]: begin
- reg_rdata_next[9:0] = dio_pads_3_attr_9_qs;
- reg_rdata_next[19:10] = dio_pads_3_attr_10_qs;
- reg_rdata_next[29:20] = dio_pads_3_attr_11_qs;
- end
-
- addr_hit[5]: begin
- reg_rdata_next[9:0] = dio_pads_4_attr_12_qs;
- reg_rdata_next[19:10] = dio_pads_4_attr_13_qs;
- reg_rdata_next[29:20] = dio_pads_4_attr_14_qs;
- end
-
- addr_hit[6]: begin
- reg_rdata_next[9:0] = dio_pads_5_attr_15_qs;
- reg_rdata_next[19:10] = dio_pads_5_attr_16_qs;
- reg_rdata_next[29:20] = dio_pads_5_attr_17_qs;
- end
-
- addr_hit[7]: begin
- reg_rdata_next[9:0] = dio_pads_6_attr_18_qs;
- reg_rdata_next[19:10] = dio_pads_6_attr_19_qs;
- reg_rdata_next[29:20] = dio_pads_6_attr_20_qs;
- end
-
- addr_hit[8]: begin
- reg_rdata_next[9:0] = mio_pads_0_attr_0_qs;
- reg_rdata_next[19:10] = mio_pads_0_attr_1_qs;
- reg_rdata_next[29:20] = mio_pads_0_attr_2_qs;
- end
-
- addr_hit[9]: begin
- reg_rdata_next[9:0] = mio_pads_1_attr_3_qs;
- reg_rdata_next[19:10] = mio_pads_1_attr_4_qs;
- reg_rdata_next[29:20] = mio_pads_1_attr_5_qs;
- end
-
- addr_hit[10]: begin
- reg_rdata_next[9:0] = mio_pads_2_attr_6_qs;
- reg_rdata_next[19:10] = mio_pads_2_attr_7_qs;
- reg_rdata_next[29:20] = mio_pads_2_attr_8_qs;
- end
-
- addr_hit[11]: begin
- reg_rdata_next[9:0] = mio_pads_3_attr_9_qs;
- reg_rdata_next[19:10] = mio_pads_3_attr_10_qs;
- reg_rdata_next[29:20] = mio_pads_3_attr_11_qs;
- end
-
- addr_hit[12]: begin
- reg_rdata_next[9:0] = mio_pads_4_attr_12_qs;
- reg_rdata_next[19:10] = mio_pads_4_attr_13_qs;
- reg_rdata_next[29:20] = mio_pads_4_attr_14_qs;
- end
-
- addr_hit[13]: begin
- reg_rdata_next[9:0] = mio_pads_5_attr_15_qs;
- reg_rdata_next[19:10] = mio_pads_5_attr_16_qs;
- reg_rdata_next[29:20] = mio_pads_5_attr_17_qs;
- end
-
- addr_hit[14]: begin
- reg_rdata_next[9:0] = mio_pads_6_attr_18_qs;
- reg_rdata_next[19:10] = mio_pads_6_attr_19_qs;
- reg_rdata_next[29:20] = mio_pads_6_attr_20_qs;
- end
-
- addr_hit[15]: begin
- reg_rdata_next[9:0] = mio_pads_7_attr_21_qs;
- reg_rdata_next[19:10] = mio_pads_7_attr_22_qs;
- reg_rdata_next[29:20] = mio_pads_7_attr_23_qs;
- end
-
- addr_hit[16]: begin
- reg_rdata_next[9:0] = mio_pads_8_attr_24_qs;
- reg_rdata_next[19:10] = mio_pads_8_attr_25_qs;
- reg_rdata_next[29:20] = mio_pads_8_attr_26_qs;
- end
-
- addr_hit[17]: begin
- reg_rdata_next[9:0] = mio_pads_9_attr_27_qs;
- reg_rdata_next[19:10] = mio_pads_9_attr_28_qs;
- reg_rdata_next[29:20] = mio_pads_9_attr_29_qs;
- end
-
- addr_hit[18]: begin
- reg_rdata_next[9:0] = mio_pads_10_attr_30_qs;
- reg_rdata_next[19:10] = mio_pads_10_attr_31_qs;
- reg_rdata_next[29:20] = mio_pads_10_attr_32_qs;
- end
-
- addr_hit[19]: begin
- reg_rdata_next[9:0] = mio_pads_11_attr_33_qs;
- reg_rdata_next[19:10] = mio_pads_11_attr_34_qs;
- reg_rdata_next[29:20] = mio_pads_11_attr_35_qs;
- end
-
- addr_hit[20]: begin
- reg_rdata_next[9:0] = mio_pads_12_attr_36_qs;
- reg_rdata_next[19:10] = mio_pads_12_attr_37_qs;
- reg_rdata_next[29:20] = mio_pads_12_attr_38_qs;
- end
-
- addr_hit[21]: begin
- reg_rdata_next[9:0] = mio_pads_13_attr_39_qs;
- reg_rdata_next[19:10] = mio_pads_13_attr_40_qs;
- reg_rdata_next[29:20] = mio_pads_13_attr_41_qs;
- end
-
- addr_hit[22]: begin
- reg_rdata_next[9:0] = mio_pads_14_attr_42_qs;
- reg_rdata_next[19:10] = mio_pads_14_attr_43_qs;
- end
-
- default: begin
- reg_rdata_next = '1;
- end
- endcase
- end
-
- // Assertions for Register Interface
- `ASSERT_PULSE(wePulse, reg_we)
- `ASSERT_PULSE(rePulse, reg_re)
-
- `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
-
- `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
-
- // this is formulated as an assumption such that the FPV testbenches do disprove this
- // property by mistake
- `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
-
-endmodule
