[alert_handler] Add generated files
diff --git a/hw/ip/alert_handler/doc/alert_handler.hjson b/hw/ip/alert_handler/doc/alert_handler.hjson
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+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+# ALERT_HANDLER register template
+#
+# Parameter (given by python tool)
+# - n_alerts: Number of alert sources
+# - esc_cnt_dw: Width of escalation counter
+# - accu_cnt_dw: Width of accumulator
+{
+ name: "ALERT_HANDLER",
+ clock_primary: "clk_fixed",
+ bus_device: "tlul",
+ regwidth: "32",
+
+# interrupt registers for the classes
+ interrupt_list: [
+ { name: "CLASSA",
+ desc: '''
+ Interrupt state bit of Class A. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
+ ''',
+ },
+ { name: "CLASSB",
+ desc: '''
+ Interrupt state bit of Class B. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
+ ''',
+ },
+ { name: "CLASSC",
+ desc: '''
+ Interrupt state bit of Class C. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
+ ''',
+ },
+ { name: "CLASSD",
+ desc: '''
+ Interrupt state bit of Class D. Set by HW in case an alert within this class triggered. Defaults true, write one to clear.
+ ''',
+ },
+ ],
+
+ registers: [
+# register locks for alerts and class configs
+ { name: "REGEN",
+ desc: '''
+ Register write enable for all control registers.
+ ''',
+ swaccess: "rw1c",
+ hwaccess: "hro",
+ fields: [
+ {
+ bits: "0",
+ desc: ''' When true, the alert enable and escalation configuration registers can be modified.
+ When false, they become read-only. Defaults true, write one to clear. Note that this needs to be
+ cleared after initial configuration at boot in order to lock in the configuration and activate
+ the ping testing.
+ '''
+ resval: 1,
+ },
+ ]
+ },
+ { name: "PING_TIMEOUT_CYC",
+ desc: '''
+ Ping timeout cycle count.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "23:0",
+ resval: 32,
+ desc: '''Timeout value in cycles. If an alert receiver or an escalation sender does not
+ respond to a ping within this timeout window, a pingfail alert will be raised.
+ '''
+ }
+ ]
+ }
+# all alerts
+ { multireg: { name: "ALERT_EN",
+ desc: '''Enable register for alerts.
+ ''',
+ count: 4,
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ cname: "alert",
+ fields: [
+ { bits: "0",
+ name: "EN_A",
+ desc: "Alert enable "
+ }
+ ]
+ }
+ },
+ { multireg: { name: "ALERT_CLASS",
+ desc: '''Class assignment of alerts.
+ ''',
+ count: 4,
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ cname: "alert",
+ fields: [
+ {
+ bits: "1:0",
+ name: "CLASS_A",
+ desc: "Classification ",
+ enum: [
+ { value: "0", name: "ClassA", desc: "" },
+ { value: "1", name: "ClassB", desc: "" },
+ { value: "2", name: "ClassC", desc: "" },
+ { value: "3", name: "ClassD", desc: "" }
+ ]
+ }
+ ]
+ }
+ },
+ { multireg: {
+ name: "ALERT_CAUSE",
+ desc: "Alert Cause Register",
+ count: 4,
+ cname: "ALERT",
+ swaccess: "rw1c",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0", name: "A", desc: "Cause bit " }
+ ]
+ }
+ },
+# local alerts
+ { multireg: { name: "LOC_ALERT_EN",
+ desc: '''Enable register for the aggregated local alerts "alert
+ pingfail" (0), "escalation pingfail" (1), "alert integfail" (2) and "escalation integfail" (3).
+ ''',
+ count: 4,
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ cname: "local alert",
+ fields: [
+ { bits: "0",
+ name: "EN_LA",
+ desc: "Alert enable "
+ }
+ ]
+ }
+ },
+ { multireg: { name: "LOC_ALERT_CLASS",
+ desc: '''Class assignment of local alerts. "alert
+ pingfail" (0), "escalation pingfail" (1), "alert integfail" (2) and "escalation integfail" (3).
+ ''',
+ count: 4,
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ cname: "local alert",
+ fields: [
+ {
+ # reduce range to 2:1 once above TODO has been fixed
+ bits: "1:0",
+ name: "CLASS_LA",
+ desc: "Classification ",
+ enum: [
+ { value: "0", name: "ClassA", desc: "" },
+ { value: "1", name: "ClassB", desc: "" },
+ { value: "2", name: "ClassC", desc: "" },
+ { value: "3", name: "ClassD", desc: "" }
+ ]
+ }
+ ]
+ }
+ },
+ { name: "LOC_ALERT_CAUSE",
+ desc: "Alert Cause Register for Local Alerts",
+ swaccess: "rw1c",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ name: "LA0",
+ desc: "True when pingfail alert has been detected on an alert receiver. Cleared with write"
+ }
+ { bits: "1",
+ name: "LA1",
+ desc: "True when pingfail alert has been detected on an escalation sender. Cleared with write"
+ }
+ { bits: "2",
+ name: "LA2",
+ desc: "True when integfail alert has been detected on an alert receiver. Cleared with write"
+ }
+ { bits: "3",
+ name: "LA3",
+ desc: "True when integfail alert has been detected on an escalation sender. Cleared with write"
+ }
+ ]
+ },
+# classes
+ { name: "CLASSA_CTRL",
+ desc: "Escalation control register for alert Class A. Can not be modified if !!REGEN is false."
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Enable escalation mechanisms (accumulation and
+ interrupt timeout) for Class A. Note that interrupts can fire
+ regardless of whether the escalation mechanisms are enabled for
+ this class or not.
+ ''',
+ }
+ { bits: "1",
+ name: "LOCK",
+ desc: '''
+ Enable automatic locking of escalation counter for class A.
+ If true, there is no way to stop the escalation protocol for class A
+ once it has been triggered.
+ '''
+ }
+ { bits: "2",
+ name: "EN_E0",
+ resval: 1,
+ desc: "Enable escalation signal 0 for class A",
+ }
+ { bits: "3",
+ name: "EN_E1",
+ resval: 1,
+ desc: "Enable escalation signal 1 for class A",
+ }
+ { bits: "4",
+ name: "EN_E2",
+ resval: 1,
+ desc: "Enable escalation signal 2 for class A",
+ }
+ { bits: "5",
+ name: "EN_E3",
+ resval: 1,
+ desc: "Enable escalation signal 3 for class A",
+ }
+ { bits: "7:6",
+ name: "MAP_E0",
+ resval: 0,
+ desc: "Determines in which escalation phase escalation signal 0 shall be asserted.",
+ }
+ { bits: "9:8",
+ name: "MAP_E1",
+ resval: 1,
+ desc: "Determines in which escalation phase escalation signal 1 shall be asserted.",
+ }
+ { bits: "11:10",
+ name: "MAP_E2",
+ resval: 2,
+ desc: "Determine sin which escalation phase escalation signal 2 shall be asserted.",
+ }
+ { bits: "13:12",
+ name: "MAP_E3",
+ resval: 3,
+ desc: "Determines in which escalation phase escalation signal 3 shall be asserted.",
+ }
+ ]
+ },
+ { name: "CLASSA_CLREN",
+ desc: '''
+ Clear enable for escalation protocol of class A alerts.
+ '''
+ swaccess: "rw1c",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ desc: '''Register defaults to true, can only be cleared. This register is set
+ to false by the hardware if the escalation protocol has been triggered and the bit
+ !!CLASSA_CTRL.LOCK is true.
+ ''',
+ resval: 1,
+ }
+ ]
+ },
+ { name: "CLASSA_CLR",
+ desc: '''
+ Clear for esclation protocol of class A.
+ '''
+ swaccess: "wo",
+ hwaccess: "hro",
+ hwqe: "true",
+ regwen: "CLASSA_CLREN",
+ fields: [
+ { bits: "0",
+ desc: '''Writing to this register clears the accumulator and aborts escalation
+ (if it has been triggered). This clear is disabled if !!CLASSA_CLREN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSA_ACCUM_CNT",
+ desc: '''
+ Current accumulation value for alert Class A. Software can clear this register
+ with a write to !!CLASSA_CLR register unless !!CLASSA_CLREN is false.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "15:0" }
+ ]
+ },
+ { name: "CLASSA_ACCUM_THRESH",
+ desc: '''
+ Accumulation threshold value for alert Class A.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "15:0",
+ desc: '''Once the accumulation value register is equal to the threshold escalation will
+ be triggered on the next alert occurrence within this class A begins. Note that this
+ register can not be modified if !!REGEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSA_TIMEOUT_CYC",
+ desc: '''
+ Interrupt timeout in cycles.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0",
+ desc: '''If the interrupt corresponding to this class is not
+ handled within the specified amount of cycles, escalation will be triggered.
+ Set to a positive value to enable the interrupt timeout for Class A. The timeout is set to zero
+ by default, which disables this feature. Note that this register can not be modified if
+ !!REGEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSA_PHASE0_CYC",
+ desc: '''
+ Duration of escalation phase 0 for class A.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSA_PHASE1_CYC",
+ desc: '''
+ Duration of escalation phase 1 for class A.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSA_PHASE2_CYC",
+ desc: '''
+ Duration of escalation phase 2 for class A.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSA_PHASE3_CYC",
+ desc: '''
+ Duration of escalation phase 3 for class A.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSA_ESC_CNT",
+ desc: '''
+ Escalation counter in cycles for class A.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ desc: '''Returns the current timeout or escalation count (depending on !!CLASSA_STATE).
+ This register can not be directly cleared. However, SW can indirectly clear as follows.
+
+ If the class is in the Timeout state, the timeout can be aborted by clearing the
+ corresponding interrupt bit.
+
+ If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be
+ aborted by writing to !!CLASSA_CLR. Note however that has no effect if !!CLASSA_CLREN
+ is set to false (either by SW or by HW via the !!CLASSA_CTRL.LOCK feature).
+ '''
+ }
+ ]
+ },
+ { name: "CLASSA_STATE",
+ desc: '''
+ Current escalation state of Class A. See also !!CLASSA_ESC_CNT.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "2:0",
+ enum: [
+ { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." },
+ { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." },
+ { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." },
+ { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." },
+ { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." },
+ { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." },
+ { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." }
+ ]
+ }
+ ]
+ },
+ { name: "CLASSB_CTRL",
+ desc: "Escalation control register for alert Class B. Can not be modified if !!REGEN is false."
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Enable escalation mechanisms (accumulation and
+ interrupt timeout) for Class B. Note that interrupts can fire
+ regardless of whether the escalation mechanisms are enabled for
+ this class or not.
+ ''',
+ }
+ { bits: "1",
+ name: "LOCK",
+ desc: '''
+ Enable automatic locking of escalation counter for class B.
+ If true, there is no way to stop the escalation protocol for class B
+ once it has been triggered.
+ '''
+ }
+ { bits: "2",
+ name: "EN_E0",
+ resval: 1,
+ desc: "Enable escalation signal 0 for class B",
+ }
+ { bits: "3",
+ name: "EN_E1",
+ resval: 1,
+ desc: "Enable escalation signal 1 for class B",
+ }
+ { bits: "4",
+ name: "EN_E2",
+ resval: 1,
+ desc: "Enable escalation signal 2 for class B",
+ }
+ { bits: "5",
+ name: "EN_E3",
+ resval: 1,
+ desc: "Enable escalation signal 3 for class B",
+ }
+ { bits: "7:6",
+ name: "MAP_E0",
+ resval: 0,
+ desc: "Determines in which escalation phase escalation signal 0 shall be asserted.",
+ }
+ { bits: "9:8",
+ name: "MAP_E1",
+ resval: 1,
+ desc: "Determines in which escalation phase escalation signal 1 shall be asserted.",
+ }
+ { bits: "11:10",
+ name: "MAP_E2",
+ resval: 2,
+ desc: "Determine sin which escalation phase escalation signal 2 shall be asserted.",
+ }
+ { bits: "13:12",
+ name: "MAP_E3",
+ resval: 3,
+ desc: "Determines in which escalation phase escalation signal 3 shall be asserted.",
+ }
+ ]
+ },
+ { name: "CLASSB_CLREN",
+ desc: '''
+ Clear enable for escalation protocol of class B alerts.
+ '''
+ swaccess: "rw1c",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ desc: '''Register defaults to true, can only be cleared. This register is set
+ to false by the hardware if the escalation protocol has been triggered and the bit
+ !!CLASSB_CTRL.LOCK is true.
+ ''',
+ resval: 1,
+ }
+ ]
+ },
+ { name: "CLASSB_CLR",
+ desc: '''
+ Clear for esclation protocol of class B.
+ '''
+ swaccess: "wo",
+ hwaccess: "hro",
+ hwqe: "true",
+ regwen: "CLASSB_CLREN",
+ fields: [
+ { bits: "0",
+ desc: '''Writing to this register clears the accumulator and aborts escalation
+ (if it has been triggered). This clear is disabled if !!CLASSB_CLREN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSB_ACCUM_CNT",
+ desc: '''
+ Current accumulation value for alert Class B. Software can clear this register
+ with a write to !!CLASSB_CLR register unless !!CLASSB_CLREN is false.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "15:0" }
+ ]
+ },
+ { name: "CLASSB_ACCUM_THRESH",
+ desc: '''
+ Accumulation threshold value for alert Class B.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "15:0",
+ desc: '''Once the accumulation value register is equal to the threshold escalation will
+ be triggered on the next alert occurrence within this class B begins. Note that this
+ register can not be modified if !!REGEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSB_TIMEOUT_CYC",
+ desc: '''
+ Interrupt timeout in cycles.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0",
+ desc: '''If the interrupt corresponding to this class is not
+ handled within the specified amount of cycles, escalation will be triggered.
+ Set to a positive value to enable the interrupt timeout for Class B. The timeout is set to zero
+ by default, which disables this feature. Note that this register can not be modified if
+ !!REGEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSB_PHASE0_CYC",
+ desc: '''
+ Duration of escalation phase 0 for class B.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSB_PHASE1_CYC",
+ desc: '''
+ Duration of escalation phase 1 for class B.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSB_PHASE2_CYC",
+ desc: '''
+ Duration of escalation phase 2 for class B.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSB_PHASE3_CYC",
+ desc: '''
+ Duration of escalation phase 3 for class B.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSB_ESC_CNT",
+ desc: '''
+ Escalation counter in cycles for class B.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ desc: '''Returns the current timeout or escalation count (depending on !!CLASSB_STATE).
+ This register can not be directly cleared. However, SW can indirectly clear as follows.
+
+ If the class is in the Timeout state, the timeout can be aborted by clearing the
+ corresponding interrupt bit.
+
+ If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be
+ aborted by writing to !!CLASSB_CLR. Note however that has no effect if !!CLASSB_CLREN
+ is set to false (either by SW or by HW via the !!CLASSB_CTRL.LOCK feature).
+ '''
+ }
+ ]
+ },
+ { name: "CLASSB_STATE",
+ desc: '''
+ Current escalation state of Class B. See also !!CLASSB_ESC_CNT.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "2:0",
+ enum: [
+ { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." },
+ { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." },
+ { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." },
+ { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." },
+ { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." },
+ { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." },
+ { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." }
+ ]
+ }
+ ]
+ },
+ { name: "CLASSC_CTRL",
+ desc: "Escalation control register for alert Class C. Can not be modified if !!REGEN is false."
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Enable escalation mechanisms (accumulation and
+ interrupt timeout) for Class C. Note that interrupts can fire
+ regardless of whether the escalation mechanisms are enabled for
+ this class or not.
+ ''',
+ }
+ { bits: "1",
+ name: "LOCK",
+ desc: '''
+ Enable automatic locking of escalation counter for class C.
+ If true, there is no way to stop the escalation protocol for class C
+ once it has been triggered.
+ '''
+ }
+ { bits: "2",
+ name: "EN_E0",
+ resval: 1,
+ desc: "Enable escalation signal 0 for class C",
+ }
+ { bits: "3",
+ name: "EN_E1",
+ resval: 1,
+ desc: "Enable escalation signal 1 for class C",
+ }
+ { bits: "4",
+ name: "EN_E2",
+ resval: 1,
+ desc: "Enable escalation signal 2 for class C",
+ }
+ { bits: "5",
+ name: "EN_E3",
+ resval: 1,
+ desc: "Enable escalation signal 3 for class C",
+ }
+ { bits: "7:6",
+ name: "MAP_E0",
+ resval: 0,
+ desc: "Determines in which escalation phase escalation signal 0 shall be asserted.",
+ }
+ { bits: "9:8",
+ name: "MAP_E1",
+ resval: 1,
+ desc: "Determines in which escalation phase escalation signal 1 shall be asserted.",
+ }
+ { bits: "11:10",
+ name: "MAP_E2",
+ resval: 2,
+ desc: "Determine sin which escalation phase escalation signal 2 shall be asserted.",
+ }
+ { bits: "13:12",
+ name: "MAP_E3",
+ resval: 3,
+ desc: "Determines in which escalation phase escalation signal 3 shall be asserted.",
+ }
+ ]
+ },
+ { name: "CLASSC_CLREN",
+ desc: '''
+ Clear enable for escalation protocol of class C alerts.
+ '''
+ swaccess: "rw1c",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ desc: '''Register defaults to true, can only be cleared. This register is set
+ to false by the hardware if the escalation protocol has been triggered and the bit
+ !!CLASSC_CTRL.LOCK is true.
+ ''',
+ resval: 1,
+ }
+ ]
+ },
+ { name: "CLASSC_CLR",
+ desc: '''
+ Clear for esclation protocol of class C.
+ '''
+ swaccess: "wo",
+ hwaccess: "hro",
+ hwqe: "true",
+ regwen: "CLASSC_CLREN",
+ fields: [
+ { bits: "0",
+ desc: '''Writing to this register clears the accumulator and aborts escalation
+ (if it has been triggered). This clear is disabled if !!CLASSC_CLREN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSC_ACCUM_CNT",
+ desc: '''
+ Current accumulation value for alert Class C. Software can clear this register
+ with a write to !!CLASSC_CLR register unless !!CLASSC_CLREN is false.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "15:0" }
+ ]
+ },
+ { name: "CLASSC_ACCUM_THRESH",
+ desc: '''
+ Accumulation threshold value for alert Class C.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "15:0",
+ desc: '''Once the accumulation value register is equal to the threshold escalation will
+ be triggered on the next alert occurrence within this class C begins. Note that this
+ register can not be modified if !!REGEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSC_TIMEOUT_CYC",
+ desc: '''
+ Interrupt timeout in cycles.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0",
+ desc: '''If the interrupt corresponding to this class is not
+ handled within the specified amount of cycles, escalation will be triggered.
+ Set to a positive value to enable the interrupt timeout for Class C. The timeout is set to zero
+ by default, which disables this feature. Note that this register can not be modified if
+ !!REGEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSC_PHASE0_CYC",
+ desc: '''
+ Duration of escalation phase 0 for class C.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSC_PHASE1_CYC",
+ desc: '''
+ Duration of escalation phase 1 for class C.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSC_PHASE2_CYC",
+ desc: '''
+ Duration of escalation phase 2 for class C.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSC_PHASE3_CYC",
+ desc: '''
+ Duration of escalation phase 3 for class C.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSC_ESC_CNT",
+ desc: '''
+ Escalation counter in cycles for class C.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ desc: '''Returns the current timeout or escalation count (depending on !!CLASSC_STATE).
+ This register can not be directly cleared. However, SW can indirectly clear as follows.
+
+ If the class is in the Timeout state, the timeout can be aborted by clearing the
+ corresponding interrupt bit.
+
+ If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be
+ aborted by writing to !!CLASSC_CLR. Note however that has no effect if !!CLASSC_CLREN
+ is set to false (either by SW or by HW via the !!CLASSC_CTRL.LOCK feature).
+ '''
+ }
+ ]
+ },
+ { name: "CLASSC_STATE",
+ desc: '''
+ Current escalation state of Class C. See also !!CLASSC_ESC_CNT.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "2:0",
+ enum: [
+ { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." },
+ { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." },
+ { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." },
+ { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." },
+ { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." },
+ { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." },
+ { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." }
+ ]
+ }
+ ]
+ },
+ { name: "CLASSD_CTRL",
+ desc: "Escalation control register for alert Class D. Can not be modified if !!REGEN is false."
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Enable escalation mechanisms (accumulation and
+ interrupt timeout) for Class D. Note that interrupts can fire
+ regardless of whether the escalation mechanisms are enabled for
+ this class or not.
+ ''',
+ }
+ { bits: "1",
+ name: "LOCK",
+ desc: '''
+ Enable automatic locking of escalation counter for class D.
+ If true, there is no way to stop the escalation protocol for class D
+ once it has been triggered.
+ '''
+ }
+ { bits: "2",
+ name: "EN_E0",
+ resval: 1,
+ desc: "Enable escalation signal 0 for class D",
+ }
+ { bits: "3",
+ name: "EN_E1",
+ resval: 1,
+ desc: "Enable escalation signal 1 for class D",
+ }
+ { bits: "4",
+ name: "EN_E2",
+ resval: 1,
+ desc: "Enable escalation signal 2 for class D",
+ }
+ { bits: "5",
+ name: "EN_E3",
+ resval: 1,
+ desc: "Enable escalation signal 3 for class D",
+ }
+ { bits: "7:6",
+ name: "MAP_E0",
+ resval: 0,
+ desc: "Determines in which escalation phase escalation signal 0 shall be asserted.",
+ }
+ { bits: "9:8",
+ name: "MAP_E1",
+ resval: 1,
+ desc: "Determines in which escalation phase escalation signal 1 shall be asserted.",
+ }
+ { bits: "11:10",
+ name: "MAP_E2",
+ resval: 2,
+ desc: "Determine sin which escalation phase escalation signal 2 shall be asserted.",
+ }
+ { bits: "13:12",
+ name: "MAP_E3",
+ resval: 3,
+ desc: "Determines in which escalation phase escalation signal 3 shall be asserted.",
+ }
+ ]
+ },
+ { name: "CLASSD_CLREN",
+ desc: '''
+ Clear enable for escalation protocol of class D alerts.
+ '''
+ swaccess: "rw1c",
+ hwaccess: "hwo",
+ fields: [
+ { bits: "0",
+ desc: '''Register defaults to true, can only be cleared. This register is set
+ to false by the hardware if the escalation protocol has been triggered and the bit
+ !!CLASSD_CTRL.LOCK is true.
+ ''',
+ resval: 1,
+ }
+ ]
+ },
+ { name: "CLASSD_CLR",
+ desc: '''
+ Clear for esclation protocol of class D.
+ '''
+ swaccess: "wo",
+ hwaccess: "hro",
+ hwqe: "true",
+ regwen: "CLASSD_CLREN",
+ fields: [
+ { bits: "0",
+ desc: '''Writing to this register clears the accumulator and aborts escalation
+ (if it has been triggered). This clear is disabled if !!CLASSD_CLREN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSD_ACCUM_CNT",
+ desc: '''
+ Current accumulation value for alert Class D. Software can clear this register
+ with a write to !!CLASSD_CLR register unless !!CLASSD_CLREN is false.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "15:0" }
+ ]
+ },
+ { name: "CLASSD_ACCUM_THRESH",
+ desc: '''
+ Accumulation threshold value for alert Class D.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "15:0",
+ desc: '''Once the accumulation value register is equal to the threshold escalation will
+ be triggered on the next alert occurrence within this class D begins. Note that this
+ register can not be modified if !!REGEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSD_TIMEOUT_CYC",
+ desc: '''
+ Interrupt timeout in cycles.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0",
+ desc: '''If the interrupt corresponding to this class is not
+ handled within the specified amount of cycles, escalation will be triggered.
+ Set to a positive value to enable the interrupt timeout for Class D. The timeout is set to zero
+ by default, which disables this feature. Note that this register can not be modified if
+ !!REGEN is false.
+ '''
+ }
+ ]
+ },
+ { name: "CLASSD_PHASE0_CYC",
+ desc: '''
+ Duration of escalation phase 0 for class D.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSD_PHASE1_CYC",
+ desc: '''
+ Duration of escalation phase 1 for class D.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSD_PHASE2_CYC",
+ desc: '''
+ Duration of escalation phase 2 for class D.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSD_PHASE3_CYC",
+ desc: '''
+ Duration of escalation phase 3 for class D.
+ '''
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ fields: [
+ { bits: "31:0" ,
+ desc: '''Escalation phase duration in cycles. Note that this register can not be
+ modified if !!REGEN is false.'''
+ }
+ ]
+ }
+ { name: "CLASSD_ESC_CNT",
+ desc: '''
+ Escalation counter in cycles for class D.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "31:0",
+ desc: '''Returns the current timeout or escalation count (depending on !!CLASSD_STATE).
+ This register can not be directly cleared. However, SW can indirectly clear as follows.
+
+ If the class is in the Timeout state, the timeout can be aborted by clearing the
+ corresponding interrupt bit.
+
+ If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be
+ aborted by writing to !!CLASSD_CLR. Note however that has no effect if !!CLASSD_CLREN
+ is set to false (either by SW or by HW via the !!CLASSD_CTRL.LOCK feature).
+ '''
+ }
+ ]
+ },
+ { name: "CLASSD_STATE",
+ desc: '''
+ Current escalation state of Class D. See also !!CLASSD_ESC_CNT.
+ '''
+ swaccess: "ro",
+ hwaccess: "hwo",
+ hwext: "true",
+ fields: [
+ { bits: "2:0",
+ enum: [
+ { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." },
+ { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." },
+ { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." },
+ { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." },
+ { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." },
+ { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." },
+ { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." }
+ ]
+ }
+ ]
+ },
+ ],
+}
+
diff --git a/hw/ip/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/ip/alert_handler/rtl/alert_handler_reg_pkg.sv
new file mode 100644
index 0000000..df0bdc2
--- /dev/null
+++ b/hw/ip/alert_handler/rtl/alert_handler_reg_pkg.sv
@@ -0,0 +1,539 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package alert_handler_reg_pkg;
+
+// Register to internal design logic
+typedef struct packed {
+
+ struct packed {
+ struct packed {
+ logic q; // [840]
+ } classa;
+ struct packed {
+ logic q; // [839]
+ } classb;
+ struct packed {
+ logic q; // [838]
+ } classc;
+ struct packed {
+ logic q; // [837]
+ } classd;
+ } intr_state;
+ struct packed {
+ struct packed {
+ logic q; // [836]
+ } classa;
+ struct packed {
+ logic q; // [835]
+ } classb;
+ struct packed {
+ logic q; // [834]
+ } classc;
+ struct packed {
+ logic q; // [833]
+ } classd;
+ } intr_enable;
+ struct packed {
+ struct packed {
+ logic q; // [832]
+ logic qe; // [831]
+ } classa;
+ struct packed {
+ logic q; // [830]
+ logic qe; // [829]
+ } classb;
+ struct packed {
+ logic q; // [828]
+ logic qe; // [827]
+ } classc;
+ struct packed {
+ logic q; // [826]
+ logic qe; // [825]
+ } classd;
+ } intr_test;
+ struct packed {
+ logic [0:0] q; // [824:824]
+ } regen;
+ struct packed {
+ logic [23:0] q; // [823:800]
+ } ping_timeout_cyc;
+ struct packed {
+ struct packed {
+ logic q; // [799]
+ } en_a0;
+ struct packed {
+ logic q; // [798]
+ } en_a1;
+ struct packed {
+ logic q; // [797]
+ } en_a2;
+ struct packed {
+ logic q; // [796]
+ } en_a3;
+ } alert_en;
+ struct packed {
+ struct packed {
+ logic [1:0] q; // [795:794]
+ } class_a0;
+ struct packed {
+ logic [1:0] q; // [793:792]
+ } class_a1;
+ struct packed {
+ logic [1:0] q; // [791:790]
+ } class_a2;
+ struct packed {
+ logic [1:0] q; // [789:788]
+ } class_a3;
+ } alert_class;
+ struct packed {
+ struct packed {
+ logic q; // [787]
+ } a0;
+ struct packed {
+ logic q; // [786]
+ } a1;
+ struct packed {
+ logic q; // [785]
+ } a2;
+ struct packed {
+ logic q; // [784]
+ } a3;
+ } alert_cause;
+ struct packed {
+ struct packed {
+ logic q; // [783]
+ } en_la0;
+ struct packed {
+ logic q; // [782]
+ } en_la1;
+ struct packed {
+ logic q; // [781]
+ } en_la2;
+ struct packed {
+ logic q; // [780]
+ } en_la3;
+ } loc_alert_en;
+ struct packed {
+ struct packed {
+ logic [1:0] q; // [779:778]
+ } class_la0;
+ struct packed {
+ logic [1:0] q; // [777:776]
+ } class_la1;
+ struct packed {
+ logic [1:0] q; // [775:774]
+ } class_la2;
+ struct packed {
+ logic [1:0] q; // [773:772]
+ } class_la3;
+ } loc_alert_class;
+ struct packed {
+ struct packed {
+ logic q; // [771]
+ } la0;
+ struct packed {
+ logic q; // [770]
+ } la1;
+ struct packed {
+ logic q; // [769]
+ } la2;
+ struct packed {
+ logic q; // [768]
+ } la3;
+ } loc_alert_cause;
+ struct packed {
+ struct packed {
+ logic q; // [767]
+ } en;
+ struct packed {
+ logic q; // [766]
+ } lock;
+ struct packed {
+ logic q; // [765]
+ } en_e0;
+ struct packed {
+ logic q; // [764]
+ } en_e1;
+ struct packed {
+ logic q; // [763]
+ } en_e2;
+ struct packed {
+ logic q; // [762]
+ } en_e3;
+ struct packed {
+ logic [1:0] q; // [761:760]
+ } map_e0;
+ struct packed {
+ logic [1:0] q; // [759:758]
+ } map_e1;
+ struct packed {
+ logic [1:0] q; // [757:756]
+ } map_e2;
+ struct packed {
+ logic [1:0] q; // [755:754]
+ } map_e3;
+ } classa_ctrl;
+ struct packed {
+ logic [0:0] q; // [753:753]
+ logic qe; // [752]
+ } classa_clr;
+ struct packed {
+ logic [15:0] q; // [751:736]
+ } classa_accum_thresh;
+ struct packed {
+ logic [31:0] q; // [735:704]
+ } classa_timeout_cyc;
+ struct packed {
+ logic [31:0] q; // [703:672]
+ } classa_phase0_cyc;
+ struct packed {
+ logic [31:0] q; // [671:640]
+ } classa_phase1_cyc;
+ struct packed {
+ logic [31:0] q; // [639:608]
+ } classa_phase2_cyc;
+ struct packed {
+ logic [31:0] q; // [607:576]
+ } classa_phase3_cyc;
+ struct packed {
+ struct packed {
+ logic q; // [575]
+ } en;
+ struct packed {
+ logic q; // [574]
+ } lock;
+ struct packed {
+ logic q; // [573]
+ } en_e0;
+ struct packed {
+ logic q; // [572]
+ } en_e1;
+ struct packed {
+ logic q; // [571]
+ } en_e2;
+ struct packed {
+ logic q; // [570]
+ } en_e3;
+ struct packed {
+ logic [1:0] q; // [569:568]
+ } map_e0;
+ struct packed {
+ logic [1:0] q; // [567:566]
+ } map_e1;
+ struct packed {
+ logic [1:0] q; // [565:564]
+ } map_e2;
+ struct packed {
+ logic [1:0] q; // [563:562]
+ } map_e3;
+ } classb_ctrl;
+ struct packed {
+ logic [0:0] q; // [561:561]
+ logic qe; // [560]
+ } classb_clr;
+ struct packed {
+ logic [15:0] q; // [559:544]
+ } classb_accum_thresh;
+ struct packed {
+ logic [31:0] q; // [543:512]
+ } classb_timeout_cyc;
+ struct packed {
+ logic [31:0] q; // [511:480]
+ } classb_phase0_cyc;
+ struct packed {
+ logic [31:0] q; // [479:448]
+ } classb_phase1_cyc;
+ struct packed {
+ logic [31:0] q; // [447:416]
+ } classb_phase2_cyc;
+ struct packed {
+ logic [31:0] q; // [415:384]
+ } classb_phase3_cyc;
+ struct packed {
+ struct packed {
+ logic q; // [383]
+ } en;
+ struct packed {
+ logic q; // [382]
+ } lock;
+ struct packed {
+ logic q; // [381]
+ } en_e0;
+ struct packed {
+ logic q; // [380]
+ } en_e1;
+ struct packed {
+ logic q; // [379]
+ } en_e2;
+ struct packed {
+ logic q; // [378]
+ } en_e3;
+ struct packed {
+ logic [1:0] q; // [377:376]
+ } map_e0;
+ struct packed {
+ logic [1:0] q; // [375:374]
+ } map_e1;
+ struct packed {
+ logic [1:0] q; // [373:372]
+ } map_e2;
+ struct packed {
+ logic [1:0] q; // [371:370]
+ } map_e3;
+ } classc_ctrl;
+ struct packed {
+ logic [0:0] q; // [369:369]
+ logic qe; // [368]
+ } classc_clr;
+ struct packed {
+ logic [15:0] q; // [367:352]
+ } classc_accum_thresh;
+ struct packed {
+ logic [31:0] q; // [351:320]
+ } classc_timeout_cyc;
+ struct packed {
+ logic [31:0] q; // [319:288]
+ } classc_phase0_cyc;
+ struct packed {
+ logic [31:0] q; // [287:256]
+ } classc_phase1_cyc;
+ struct packed {
+ logic [31:0] q; // [255:224]
+ } classc_phase2_cyc;
+ struct packed {
+ logic [31:0] q; // [223:192]
+ } classc_phase3_cyc;
+ struct packed {
+ struct packed {
+ logic q; // [191]
+ } en;
+ struct packed {
+ logic q; // [190]
+ } lock;
+ struct packed {
+ logic q; // [189]
+ } en_e0;
+ struct packed {
+ logic q; // [188]
+ } en_e1;
+ struct packed {
+ logic q; // [187]
+ } en_e2;
+ struct packed {
+ logic q; // [186]
+ } en_e3;
+ struct packed {
+ logic [1:0] q; // [185:184]
+ } map_e0;
+ struct packed {
+ logic [1:0] q; // [183:182]
+ } map_e1;
+ struct packed {
+ logic [1:0] q; // [181:180]
+ } map_e2;
+ struct packed {
+ logic [1:0] q; // [179:178]
+ } map_e3;
+ } classd_ctrl;
+ struct packed {
+ logic [0:0] q; // [177:177]
+ logic qe; // [176]
+ } classd_clr;
+ struct packed {
+ logic [15:0] q; // [175:160]
+ } classd_accum_thresh;
+ struct packed {
+ logic [31:0] q; // [159:128]
+ } classd_timeout_cyc;
+ struct packed {
+ logic [31:0] q; // [127:96]
+ } classd_phase0_cyc;
+ struct packed {
+ logic [31:0] q; // [95:64]
+ } classd_phase1_cyc;
+ struct packed {
+ logic [31:0] q; // [63:32]
+ } classd_phase2_cyc;
+ struct packed {
+ logic [31:0] q; // [31:0]
+ } classd_phase3_cyc;
+} alert_handler_reg2hw_t;
+
+// Internal design logic to register
+typedef struct packed {
+
+ struct packed {
+ struct packed {
+ logic d; // [235]
+ logic de; // [234]
+ } classa;
+ struct packed {
+ logic d; // [233]
+ logic de; // [232]
+ } classb;
+ struct packed {
+ logic d; // [231]
+ logic de; // [230]
+ } classc;
+ struct packed {
+ logic d; // [229]
+ logic de; // [228]
+ } classd;
+ } intr_state;
+ struct packed {
+ struct packed {
+ logic d; // [227]
+ logic de; // [226]
+ } a0;
+ struct packed {
+ logic d; // [225]
+ logic de; // [224]
+ } a1;
+ struct packed {
+ logic d; // [223]
+ logic de; // [222]
+ } a2;
+ struct packed {
+ logic d; // [221]
+ logic de; // [220]
+ } a3;
+ } alert_cause;
+ struct packed {
+ struct packed {
+ logic d; // [219]
+ logic de; // [218]
+ } la0;
+ struct packed {
+ logic d; // [217]
+ logic de; // [216]
+ } la1;
+ struct packed {
+ logic d; // [215]
+ logic de; // [214]
+ } la2;
+ struct packed {
+ logic d; // [213]
+ logic de; // [212]
+ } la3;
+ } loc_alert_cause;
+ struct packed {
+ logic [0:0] d; // [211:211]
+ logic de; // [210]
+ } classa_clren;
+ struct packed {
+ logic [15:0] d; // [209:194]
+ } classa_accum_cnt;
+ struct packed {
+ logic [31:0] d; // [193:162]
+ } classa_esc_cnt;
+ struct packed {
+ logic [2:0] d; // [161:159]
+ } classa_state;
+ struct packed {
+ logic [0:0] d; // [158:158]
+ logic de; // [157]
+ } classb_clren;
+ struct packed {
+ logic [15:0] d; // [156:141]
+ } classb_accum_cnt;
+ struct packed {
+ logic [31:0] d; // [140:109]
+ } classb_esc_cnt;
+ struct packed {
+ logic [2:0] d; // [108:106]
+ } classb_state;
+ struct packed {
+ logic [0:0] d; // [105:105]
+ logic de; // [104]
+ } classc_clren;
+ struct packed {
+ logic [15:0] d; // [103:88]
+ } classc_accum_cnt;
+ struct packed {
+ logic [31:0] d; // [87:56]
+ } classc_esc_cnt;
+ struct packed {
+ logic [2:0] d; // [55:53]
+ } classc_state;
+ struct packed {
+ logic [0:0] d; // [52:52]
+ logic de; // [51]
+ } classd_clren;
+ struct packed {
+ logic [15:0] d; // [50:35]
+ } classd_accum_cnt;
+ struct packed {
+ logic [31:0] d; // [34:3]
+ } classd_esc_cnt;
+ struct packed {
+ logic [2:0] d; // [2:0]
+ } classd_state;
+} alert_handler_hw2reg_t;
+
+ // Register Address
+ parameter ALERT_HANDLER_INTR_STATE_OFFSET = 8'h 0;
+ parameter ALERT_HANDLER_INTR_ENABLE_OFFSET = 8'h 4;
+ parameter ALERT_HANDLER_INTR_TEST_OFFSET = 8'h 8;
+ parameter ALERT_HANDLER_REGEN_OFFSET = 8'h c;
+ parameter ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET = 8'h 10;
+ parameter ALERT_HANDLER_ALERT_EN_OFFSET = 8'h 14;
+ parameter ALERT_HANDLER_ALERT_CLASS_OFFSET = 8'h 18;
+ parameter ALERT_HANDLER_ALERT_CAUSE_OFFSET = 8'h 1c;
+ parameter ALERT_HANDLER_LOC_ALERT_EN_OFFSET = 8'h 20;
+ parameter ALERT_HANDLER_LOC_ALERT_CLASS_OFFSET = 8'h 24;
+ parameter ALERT_HANDLER_LOC_ALERT_CAUSE_OFFSET = 8'h 28;
+ parameter ALERT_HANDLER_CLASSA_CTRL_OFFSET = 8'h 2c;
+ parameter ALERT_HANDLER_CLASSA_CLREN_OFFSET = 8'h 30;
+ parameter ALERT_HANDLER_CLASSA_CLR_OFFSET = 8'h 34;
+ parameter ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 8'h 38;
+ parameter ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 8'h 3c;
+ parameter ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 8'h 40;
+ parameter ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 8'h 44;
+ parameter ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 8'h 48;
+ parameter ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 8'h 4c;
+ parameter ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 8'h 50;
+ parameter ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 8'h 54;
+ parameter ALERT_HANDLER_CLASSA_STATE_OFFSET = 8'h 58;
+ parameter ALERT_HANDLER_CLASSB_CTRL_OFFSET = 8'h 5c;
+ parameter ALERT_HANDLER_CLASSB_CLREN_OFFSET = 8'h 60;
+ parameter ALERT_HANDLER_CLASSB_CLR_OFFSET = 8'h 64;
+ parameter ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 8'h 68;
+ parameter ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 8'h 6c;
+ parameter ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 8'h 70;
+ parameter ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 8'h 74;
+ parameter ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 8'h 78;
+ parameter ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 8'h 7c;
+ parameter ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 8'h 80;
+ parameter ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 8'h 84;
+ parameter ALERT_HANDLER_CLASSB_STATE_OFFSET = 8'h 88;
+ parameter ALERT_HANDLER_CLASSC_CTRL_OFFSET = 8'h 8c;
+ parameter ALERT_HANDLER_CLASSC_CLREN_OFFSET = 8'h 90;
+ parameter ALERT_HANDLER_CLASSC_CLR_OFFSET = 8'h 94;
+ parameter ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 8'h 98;
+ parameter ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 8'h 9c;
+ parameter ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 8'h a0;
+ parameter ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 8'h a4;
+ parameter ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 8'h a8;
+ parameter ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 8'h ac;
+ parameter ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 8'h b0;
+ parameter ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 8'h b4;
+ parameter ALERT_HANDLER_CLASSC_STATE_OFFSET = 8'h b8;
+ parameter ALERT_HANDLER_CLASSD_CTRL_OFFSET = 8'h bc;
+ parameter ALERT_HANDLER_CLASSD_CLREN_OFFSET = 8'h c0;
+ parameter ALERT_HANDLER_CLASSD_CLR_OFFSET = 8'h c4;
+ parameter ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 8'h c8;
+ parameter ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 8'h cc;
+ parameter ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 8'h d0;
+ parameter ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 8'h d4;
+ parameter ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 8'h d8;
+ parameter ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 8'h dc;
+ parameter ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 8'h e0;
+ parameter ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 8'h e4;
+ parameter ALERT_HANDLER_CLASSD_STATE_OFFSET = 8'h e8;
+
+
+endpackage
diff --git a/hw/ip/alert_handler/rtl/alert_handler_reg_top.sv b/hw/ip/alert_handler/rtl/alert_handler_reg_top.sv
new file mode 100644
index 0000000..a7fc63b
--- /dev/null
+++ b/hw/ip/alert_handler/rtl/alert_handler_reg_top.sv
@@ -0,0 +1,4255 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+
+module alert_handler_reg_top (
+ input clk_i,
+ input rst_ni,
+
+ // Below Regster interface can be changed
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw, // Write
+ input alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg // Read
+);
+
+ import alert_handler_reg_pkg::* ;
+
+ localparam AW = 8;
+ localparam DW = 32;
+ localparam DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic malformed, addrmiss;
+
+ logic [DW-1:0] reg_rdata_next;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW)
+ ) u_reg_if (
+ .clk_i,
+ .rst_ni,
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = malformed | addrmiss ;
+
+ // Malformed request check only affects to the write access
+ always_comb begin : malformed_check
+ if (reg_we && (reg_be != '1)) begin
+ malformed = 1'b1;
+ end else begin
+ malformed = 1'b0;
+ end
+ end
+
+ // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
+ // TODO(eunchan): Make concrete scenario
+ // 1. Write: No response, so that it can guarantee a request completes a clock after we
+ // It means, bus_reg_ready doesn't have to be lowered.
+ // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
+ // _____ _____
+ // a_valid _____/ \_______/ \______
+ // ___________ _____
+ // a_ready \_______/ \______ <- ERR though no logic malfunction
+ // _____________
+ // d_valid ___________/ \______
+ // _____
+ // d_ready ___________________/ \______
+ //
+ // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic intr_state_classa_qs;
+ logic intr_state_classa_wd;
+ logic intr_state_classa_we;
+ logic intr_state_classb_qs;
+ logic intr_state_classb_wd;
+ logic intr_state_classb_we;
+ logic intr_state_classc_qs;
+ logic intr_state_classc_wd;
+ logic intr_state_classc_we;
+ logic intr_state_classd_qs;
+ logic intr_state_classd_wd;
+ logic intr_state_classd_we;
+ logic intr_enable_classa_qs;
+ logic intr_enable_classa_wd;
+ logic intr_enable_classa_we;
+ logic intr_enable_classb_qs;
+ logic intr_enable_classb_wd;
+ logic intr_enable_classb_we;
+ logic intr_enable_classc_qs;
+ logic intr_enable_classc_wd;
+ logic intr_enable_classc_we;
+ logic intr_enable_classd_qs;
+ logic intr_enable_classd_wd;
+ logic intr_enable_classd_we;
+ logic intr_test_classa_wd;
+ logic intr_test_classa_we;
+ logic intr_test_classb_wd;
+ logic intr_test_classb_we;
+ logic intr_test_classc_wd;
+ logic intr_test_classc_we;
+ logic intr_test_classd_wd;
+ logic intr_test_classd_we;
+ logic regen_qs;
+ logic regen_wd;
+ logic regen_we;
+ logic [23:0] ping_timeout_cyc_qs;
+ logic [23:0] ping_timeout_cyc_wd;
+ logic ping_timeout_cyc_we;
+ logic alert_en_en_a0_qs;
+ logic alert_en_en_a0_wd;
+ logic alert_en_en_a0_we;
+ logic alert_en_en_a1_qs;
+ logic alert_en_en_a1_wd;
+ logic alert_en_en_a1_we;
+ logic alert_en_en_a2_qs;
+ logic alert_en_en_a2_wd;
+ logic alert_en_en_a2_we;
+ logic alert_en_en_a3_qs;
+ logic alert_en_en_a3_wd;
+ logic alert_en_en_a3_we;
+ logic [1:0] alert_class_class_a0_qs;
+ logic [1:0] alert_class_class_a0_wd;
+ logic alert_class_class_a0_we;
+ logic [1:0] alert_class_class_a1_qs;
+ logic [1:0] alert_class_class_a1_wd;
+ logic alert_class_class_a1_we;
+ logic [1:0] alert_class_class_a2_qs;
+ logic [1:0] alert_class_class_a2_wd;
+ logic alert_class_class_a2_we;
+ logic [1:0] alert_class_class_a3_qs;
+ logic [1:0] alert_class_class_a3_wd;
+ logic alert_class_class_a3_we;
+ logic alert_cause_a0_qs;
+ logic alert_cause_a0_wd;
+ logic alert_cause_a0_we;
+ logic alert_cause_a1_qs;
+ logic alert_cause_a1_wd;
+ logic alert_cause_a1_we;
+ logic alert_cause_a2_qs;
+ logic alert_cause_a2_wd;
+ logic alert_cause_a2_we;
+ logic alert_cause_a3_qs;
+ logic alert_cause_a3_wd;
+ logic alert_cause_a3_we;
+ logic loc_alert_en_en_la0_qs;
+ logic loc_alert_en_en_la0_wd;
+ logic loc_alert_en_en_la0_we;
+ logic loc_alert_en_en_la1_qs;
+ logic loc_alert_en_en_la1_wd;
+ logic loc_alert_en_en_la1_we;
+ logic loc_alert_en_en_la2_qs;
+ logic loc_alert_en_en_la2_wd;
+ logic loc_alert_en_en_la2_we;
+ logic loc_alert_en_en_la3_qs;
+ logic loc_alert_en_en_la3_wd;
+ logic loc_alert_en_en_la3_we;
+ logic [1:0] loc_alert_class_class_la0_qs;
+ logic [1:0] loc_alert_class_class_la0_wd;
+ logic loc_alert_class_class_la0_we;
+ logic [1:0] loc_alert_class_class_la1_qs;
+ logic [1:0] loc_alert_class_class_la1_wd;
+ logic loc_alert_class_class_la1_we;
+ logic [1:0] loc_alert_class_class_la2_qs;
+ logic [1:0] loc_alert_class_class_la2_wd;
+ logic loc_alert_class_class_la2_we;
+ logic [1:0] loc_alert_class_class_la3_qs;
+ logic [1:0] loc_alert_class_class_la3_wd;
+ logic loc_alert_class_class_la3_we;
+ logic loc_alert_cause_la0_qs;
+ logic loc_alert_cause_la0_wd;
+ logic loc_alert_cause_la0_we;
+ logic loc_alert_cause_la1_qs;
+ logic loc_alert_cause_la1_wd;
+ logic loc_alert_cause_la1_we;
+ logic loc_alert_cause_la2_qs;
+ logic loc_alert_cause_la2_wd;
+ logic loc_alert_cause_la2_we;
+ logic loc_alert_cause_la3_qs;
+ logic loc_alert_cause_la3_wd;
+ logic loc_alert_cause_la3_we;
+ logic classa_ctrl_en_qs;
+ logic classa_ctrl_en_wd;
+ logic classa_ctrl_en_we;
+ logic classa_ctrl_lock_qs;
+ logic classa_ctrl_lock_wd;
+ logic classa_ctrl_lock_we;
+ logic classa_ctrl_en_e0_qs;
+ logic classa_ctrl_en_e0_wd;
+ logic classa_ctrl_en_e0_we;
+ logic classa_ctrl_en_e1_qs;
+ logic classa_ctrl_en_e1_wd;
+ logic classa_ctrl_en_e1_we;
+ logic classa_ctrl_en_e2_qs;
+ logic classa_ctrl_en_e2_wd;
+ logic classa_ctrl_en_e2_we;
+ logic classa_ctrl_en_e3_qs;
+ logic classa_ctrl_en_e3_wd;
+ logic classa_ctrl_en_e3_we;
+ logic [1:0] classa_ctrl_map_e0_qs;
+ logic [1:0] classa_ctrl_map_e0_wd;
+ logic classa_ctrl_map_e0_we;
+ logic [1:0] classa_ctrl_map_e1_qs;
+ logic [1:0] classa_ctrl_map_e1_wd;
+ logic classa_ctrl_map_e1_we;
+ logic [1:0] classa_ctrl_map_e2_qs;
+ logic [1:0] classa_ctrl_map_e2_wd;
+ logic classa_ctrl_map_e2_we;
+ logic [1:0] classa_ctrl_map_e3_qs;
+ logic [1:0] classa_ctrl_map_e3_wd;
+ logic classa_ctrl_map_e3_we;
+ logic classa_clren_qs;
+ logic classa_clren_wd;
+ logic classa_clren_we;
+ logic classa_clr_wd;
+ logic classa_clr_we;
+ logic [15:0] classa_accum_cnt_qs;
+ logic classa_accum_cnt_re;
+ logic [15:0] classa_accum_thresh_qs;
+ logic [15:0] classa_accum_thresh_wd;
+ logic classa_accum_thresh_we;
+ logic [31:0] classa_timeout_cyc_qs;
+ logic [31:0] classa_timeout_cyc_wd;
+ logic classa_timeout_cyc_we;
+ logic [31:0] classa_phase0_cyc_qs;
+ logic [31:0] classa_phase0_cyc_wd;
+ logic classa_phase0_cyc_we;
+ logic [31:0] classa_phase1_cyc_qs;
+ logic [31:0] classa_phase1_cyc_wd;
+ logic classa_phase1_cyc_we;
+ logic [31:0] classa_phase2_cyc_qs;
+ logic [31:0] classa_phase2_cyc_wd;
+ logic classa_phase2_cyc_we;
+ logic [31:0] classa_phase3_cyc_qs;
+ logic [31:0] classa_phase3_cyc_wd;
+ logic classa_phase3_cyc_we;
+ logic [31:0] classa_esc_cnt_qs;
+ logic classa_esc_cnt_re;
+ logic [2:0] classa_state_qs;
+ logic classa_state_re;
+ logic classb_ctrl_en_qs;
+ logic classb_ctrl_en_wd;
+ logic classb_ctrl_en_we;
+ logic classb_ctrl_lock_qs;
+ logic classb_ctrl_lock_wd;
+ logic classb_ctrl_lock_we;
+ logic classb_ctrl_en_e0_qs;
+ logic classb_ctrl_en_e0_wd;
+ logic classb_ctrl_en_e0_we;
+ logic classb_ctrl_en_e1_qs;
+ logic classb_ctrl_en_e1_wd;
+ logic classb_ctrl_en_e1_we;
+ logic classb_ctrl_en_e2_qs;
+ logic classb_ctrl_en_e2_wd;
+ logic classb_ctrl_en_e2_we;
+ logic classb_ctrl_en_e3_qs;
+ logic classb_ctrl_en_e3_wd;
+ logic classb_ctrl_en_e3_we;
+ logic [1:0] classb_ctrl_map_e0_qs;
+ logic [1:0] classb_ctrl_map_e0_wd;
+ logic classb_ctrl_map_e0_we;
+ logic [1:0] classb_ctrl_map_e1_qs;
+ logic [1:0] classb_ctrl_map_e1_wd;
+ logic classb_ctrl_map_e1_we;
+ logic [1:0] classb_ctrl_map_e2_qs;
+ logic [1:0] classb_ctrl_map_e2_wd;
+ logic classb_ctrl_map_e2_we;
+ logic [1:0] classb_ctrl_map_e3_qs;
+ logic [1:0] classb_ctrl_map_e3_wd;
+ logic classb_ctrl_map_e3_we;
+ logic classb_clren_qs;
+ logic classb_clren_wd;
+ logic classb_clren_we;
+ logic classb_clr_wd;
+ logic classb_clr_we;
+ logic [15:0] classb_accum_cnt_qs;
+ logic classb_accum_cnt_re;
+ logic [15:0] classb_accum_thresh_qs;
+ logic [15:0] classb_accum_thresh_wd;
+ logic classb_accum_thresh_we;
+ logic [31:0] classb_timeout_cyc_qs;
+ logic [31:0] classb_timeout_cyc_wd;
+ logic classb_timeout_cyc_we;
+ logic [31:0] classb_phase0_cyc_qs;
+ logic [31:0] classb_phase0_cyc_wd;
+ logic classb_phase0_cyc_we;
+ logic [31:0] classb_phase1_cyc_qs;
+ logic [31:0] classb_phase1_cyc_wd;
+ logic classb_phase1_cyc_we;
+ logic [31:0] classb_phase2_cyc_qs;
+ logic [31:0] classb_phase2_cyc_wd;
+ logic classb_phase2_cyc_we;
+ logic [31:0] classb_phase3_cyc_qs;
+ logic [31:0] classb_phase3_cyc_wd;
+ logic classb_phase3_cyc_we;
+ logic [31:0] classb_esc_cnt_qs;
+ logic classb_esc_cnt_re;
+ logic [2:0] classb_state_qs;
+ logic classb_state_re;
+ logic classc_ctrl_en_qs;
+ logic classc_ctrl_en_wd;
+ logic classc_ctrl_en_we;
+ logic classc_ctrl_lock_qs;
+ logic classc_ctrl_lock_wd;
+ logic classc_ctrl_lock_we;
+ logic classc_ctrl_en_e0_qs;
+ logic classc_ctrl_en_e0_wd;
+ logic classc_ctrl_en_e0_we;
+ logic classc_ctrl_en_e1_qs;
+ logic classc_ctrl_en_e1_wd;
+ logic classc_ctrl_en_e1_we;
+ logic classc_ctrl_en_e2_qs;
+ logic classc_ctrl_en_e2_wd;
+ logic classc_ctrl_en_e2_we;
+ logic classc_ctrl_en_e3_qs;
+ logic classc_ctrl_en_e3_wd;
+ logic classc_ctrl_en_e3_we;
+ logic [1:0] classc_ctrl_map_e0_qs;
+ logic [1:0] classc_ctrl_map_e0_wd;
+ logic classc_ctrl_map_e0_we;
+ logic [1:0] classc_ctrl_map_e1_qs;
+ logic [1:0] classc_ctrl_map_e1_wd;
+ logic classc_ctrl_map_e1_we;
+ logic [1:0] classc_ctrl_map_e2_qs;
+ logic [1:0] classc_ctrl_map_e2_wd;
+ logic classc_ctrl_map_e2_we;
+ logic [1:0] classc_ctrl_map_e3_qs;
+ logic [1:0] classc_ctrl_map_e3_wd;
+ logic classc_ctrl_map_e3_we;
+ logic classc_clren_qs;
+ logic classc_clren_wd;
+ logic classc_clren_we;
+ logic classc_clr_wd;
+ logic classc_clr_we;
+ logic [15:0] classc_accum_cnt_qs;
+ logic classc_accum_cnt_re;
+ logic [15:0] classc_accum_thresh_qs;
+ logic [15:0] classc_accum_thresh_wd;
+ logic classc_accum_thresh_we;
+ logic [31:0] classc_timeout_cyc_qs;
+ logic [31:0] classc_timeout_cyc_wd;
+ logic classc_timeout_cyc_we;
+ logic [31:0] classc_phase0_cyc_qs;
+ logic [31:0] classc_phase0_cyc_wd;
+ logic classc_phase0_cyc_we;
+ logic [31:0] classc_phase1_cyc_qs;
+ logic [31:0] classc_phase1_cyc_wd;
+ logic classc_phase1_cyc_we;
+ logic [31:0] classc_phase2_cyc_qs;
+ logic [31:0] classc_phase2_cyc_wd;
+ logic classc_phase2_cyc_we;
+ logic [31:0] classc_phase3_cyc_qs;
+ logic [31:0] classc_phase3_cyc_wd;
+ logic classc_phase3_cyc_we;
+ logic [31:0] classc_esc_cnt_qs;
+ logic classc_esc_cnt_re;
+ logic [2:0] classc_state_qs;
+ logic classc_state_re;
+ logic classd_ctrl_en_qs;
+ logic classd_ctrl_en_wd;
+ logic classd_ctrl_en_we;
+ logic classd_ctrl_lock_qs;
+ logic classd_ctrl_lock_wd;
+ logic classd_ctrl_lock_we;
+ logic classd_ctrl_en_e0_qs;
+ logic classd_ctrl_en_e0_wd;
+ logic classd_ctrl_en_e0_we;
+ logic classd_ctrl_en_e1_qs;
+ logic classd_ctrl_en_e1_wd;
+ logic classd_ctrl_en_e1_we;
+ logic classd_ctrl_en_e2_qs;
+ logic classd_ctrl_en_e2_wd;
+ logic classd_ctrl_en_e2_we;
+ logic classd_ctrl_en_e3_qs;
+ logic classd_ctrl_en_e3_wd;
+ logic classd_ctrl_en_e3_we;
+ logic [1:0] classd_ctrl_map_e0_qs;
+ logic [1:0] classd_ctrl_map_e0_wd;
+ logic classd_ctrl_map_e0_we;
+ logic [1:0] classd_ctrl_map_e1_qs;
+ logic [1:0] classd_ctrl_map_e1_wd;
+ logic classd_ctrl_map_e1_we;
+ logic [1:0] classd_ctrl_map_e2_qs;
+ logic [1:0] classd_ctrl_map_e2_wd;
+ logic classd_ctrl_map_e2_we;
+ logic [1:0] classd_ctrl_map_e3_qs;
+ logic [1:0] classd_ctrl_map_e3_wd;
+ logic classd_ctrl_map_e3_we;
+ logic classd_clren_qs;
+ logic classd_clren_wd;
+ logic classd_clren_we;
+ logic classd_clr_wd;
+ logic classd_clr_we;
+ logic [15:0] classd_accum_cnt_qs;
+ logic classd_accum_cnt_re;
+ logic [15:0] classd_accum_thresh_qs;
+ logic [15:0] classd_accum_thresh_wd;
+ logic classd_accum_thresh_we;
+ logic [31:0] classd_timeout_cyc_qs;
+ logic [31:0] classd_timeout_cyc_wd;
+ logic classd_timeout_cyc_we;
+ logic [31:0] classd_phase0_cyc_qs;
+ logic [31:0] classd_phase0_cyc_wd;
+ logic classd_phase0_cyc_we;
+ logic [31:0] classd_phase1_cyc_qs;
+ logic [31:0] classd_phase1_cyc_wd;
+ logic classd_phase1_cyc_we;
+ logic [31:0] classd_phase2_cyc_qs;
+ logic [31:0] classd_phase2_cyc_wd;
+ logic classd_phase2_cyc_we;
+ logic [31:0] classd_phase3_cyc_qs;
+ logic [31:0] classd_phase3_cyc_wd;
+ logic classd_phase3_cyc_we;
+ logic [31:0] classd_esc_cnt_qs;
+ logic classd_esc_cnt_re;
+ logic [2:0] classd_state_qs;
+ logic classd_state_re;
+
+ // Register instances
+ // R[intr_state]: V(False)
+
+ // F[classa]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_classa (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_classa_we),
+ .wd (intr_state_classa_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.classa.de),
+ .d (hw2reg.intr_state.classa.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.classa.q ),
+
+ // to register interface (read)
+ .qs (intr_state_classa_qs)
+ );
+
+
+ // F[classb]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_classb (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_classb_we),
+ .wd (intr_state_classb_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.classb.de),
+ .d (hw2reg.intr_state.classb.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.classb.q ),
+
+ // to register interface (read)
+ .qs (intr_state_classb_qs)
+ );
+
+
+ // F[classc]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_classc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_classc_we),
+ .wd (intr_state_classc_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.classc.de),
+ .d (hw2reg.intr_state.classc.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.classc.q ),
+
+ // to register interface (read)
+ .qs (intr_state_classc_qs)
+ );
+
+
+ // F[classd]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_classd (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_classd_we),
+ .wd (intr_state_classd_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.classd.de),
+ .d (hw2reg.intr_state.classd.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.classd.q ),
+
+ // to register interface (read)
+ .qs (intr_state_classd_qs)
+ );
+
+
+ // R[intr_enable]: V(False)
+
+ // F[classa]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_classa (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_classa_we),
+ .wd (intr_enable_classa_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.classa.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_classa_qs)
+ );
+
+
+ // F[classb]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_classb (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_classb_we),
+ .wd (intr_enable_classb_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.classb.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_classb_qs)
+ );
+
+
+ // F[classc]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_classc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_classc_we),
+ .wd (intr_enable_classc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.classc.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_classc_qs)
+ );
+
+
+ // F[classd]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_classd (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_classd_we),
+ .wd (intr_enable_classd_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.classd.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_classd_qs)
+ );
+
+
+ // R[intr_test]: V(True)
+
+ // F[classa]: 0:0
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_classa (
+ .re (1'b0),
+ .we (intr_test_classa_we),
+ .wd (intr_test_classa_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.classa.qe),
+ .q (reg2hw.intr_test.classa.q ),
+ .qs ()
+ );
+
+
+ // F[classb]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_classb (
+ .re (1'b0),
+ .we (intr_test_classb_we),
+ .wd (intr_test_classb_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.classb.qe),
+ .q (reg2hw.intr_test.classb.q ),
+ .qs ()
+ );
+
+
+ // F[classc]: 2:2
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_classc (
+ .re (1'b0),
+ .we (intr_test_classc_we),
+ .wd (intr_test_classc_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.classc.qe),
+ .q (reg2hw.intr_test.classc.q ),
+ .qs ()
+ );
+
+
+ // F[classd]: 3:3
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_classd (
+ .re (1'b0),
+ .we (intr_test_classd_we),
+ .wd (intr_test_classd_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.classd.qe),
+ .q (reg2hw.intr_test.classd.q ),
+ .qs ()
+ );
+
+
+ // R[regen]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h1)
+ ) u_regen (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (regen_we),
+ .wd (regen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.regen.q ),
+
+ // to register interface (read)
+ .qs (regen_qs)
+ );
+
+
+ // R[ping_timeout_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (24),
+ .SWACCESS("RW"),
+ .RESVAL (24'h20)
+ ) u_ping_timeout_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (ping_timeout_cyc_we & regen_qs),
+ .wd (ping_timeout_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ping_timeout_cyc.q ),
+
+ // to register interface (read)
+ .qs (ping_timeout_cyc_qs)
+ );
+
+
+ // R[alert_en]: V(False)
+
+ // F[en_a0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_en_a0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_en_en_a0_we & regen_qs),
+ .wd (alert_en_en_a0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en.en_a0.q ),
+
+ // to register interface (read)
+ .qs (alert_en_en_a0_qs)
+ );
+
+
+ // F[en_a1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_en_a1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_en_en_a1_we & regen_qs),
+ .wd (alert_en_en_a1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en.en_a1.q ),
+
+ // to register interface (read)
+ .qs (alert_en_en_a1_qs)
+ );
+
+
+ // F[en_a2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_en_a2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_en_en_a2_we & regen_qs),
+ .wd (alert_en_en_a2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en.en_a2.q ),
+
+ // to register interface (read)
+ .qs (alert_en_en_a2_qs)
+ );
+
+
+ // F[en_a3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_en_a3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_en_en_a3_we & regen_qs),
+ .wd (alert_en_en_a3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en.en_a3.q ),
+
+ // to register interface (read)
+ .qs (alert_en_en_a3_qs)
+ );
+
+
+ // R[alert_class]: V(False)
+
+ // F[class_a0]: 1:0
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_class_a0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_class_class_a0_we & regen_qs),
+ .wd (alert_class_class_a0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class.class_a0.q ),
+
+ // to register interface (read)
+ .qs (alert_class_class_a0_qs)
+ );
+
+
+ // F[class_a1]: 3:2
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_class_a1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_class_class_a1_we & regen_qs),
+ .wd (alert_class_class_a1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class.class_a1.q ),
+
+ // to register interface (read)
+ .qs (alert_class_class_a1_qs)
+ );
+
+
+ // F[class_a2]: 5:4
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_class_a2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_class_class_a2_we & regen_qs),
+ .wd (alert_class_class_a2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class.class_a2.q ),
+
+ // to register interface (read)
+ .qs (alert_class_class_a2_qs)
+ );
+
+
+ // F[class_a3]: 7:6
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_class_a3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_class_class_a3_we & regen_qs),
+ .wd (alert_class_class_a3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class.class_a3.q ),
+
+ // to register interface (read)
+ .qs (alert_class_class_a3_qs)
+ );
+
+
+ // R[alert_cause]: V(False)
+
+ // F[a0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_a0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (alert_cause_a0_we),
+ .wd (alert_cause_a0_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause.a0.de),
+ .d (hw2reg.alert_cause.a0.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause.a0.q ),
+
+ // to register interface (read)
+ .qs (alert_cause_a0_qs)
+ );
+
+
+ // F[a1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_a1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (alert_cause_a1_we),
+ .wd (alert_cause_a1_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause.a1.de),
+ .d (hw2reg.alert_cause.a1.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause.a1.q ),
+
+ // to register interface (read)
+ .qs (alert_cause_a1_qs)
+ );
+
+
+ // F[a2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_a2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (alert_cause_a2_we),
+ .wd (alert_cause_a2_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause.a2.de),
+ .d (hw2reg.alert_cause.a2.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause.a2.q ),
+
+ // to register interface (read)
+ .qs (alert_cause_a2_qs)
+ );
+
+
+ // F[a3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_a3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (alert_cause_a3_we),
+ .wd (alert_cause_a3_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause.a3.de),
+ .d (hw2reg.alert_cause.a3.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause.a3.q ),
+
+ // to register interface (read)
+ .qs (alert_cause_a3_qs)
+ );
+
+
+ // R[loc_alert_en]: V(False)
+
+ // F[en_la0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_loc_alert_en_en_la0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (loc_alert_en_en_la0_we & regen_qs),
+ .wd (loc_alert_en_en_la0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_en.en_la0.q ),
+
+ // to register interface (read)
+ .qs (loc_alert_en_en_la0_qs)
+ );
+
+
+ // F[en_la1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_loc_alert_en_en_la1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (loc_alert_en_en_la1_we & regen_qs),
+ .wd (loc_alert_en_en_la1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_en.en_la1.q ),
+
+ // to register interface (read)
+ .qs (loc_alert_en_en_la1_qs)
+ );
+
+
+ // F[en_la2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_loc_alert_en_en_la2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (loc_alert_en_en_la2_we & regen_qs),
+ .wd (loc_alert_en_en_la2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_en.en_la2.q ),
+
+ // to register interface (read)
+ .qs (loc_alert_en_en_la2_qs)
+ );
+
+
+ // F[en_la3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_loc_alert_en_en_la3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (loc_alert_en_en_la3_we & regen_qs),
+ .wd (loc_alert_en_en_la3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_en.en_la3.q ),
+
+ // to register interface (read)
+ .qs (loc_alert_en_en_la3_qs)
+ );
+
+
+ // R[loc_alert_class]: V(False)
+
+ // F[class_la0]: 1:0
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_loc_alert_class_class_la0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (loc_alert_class_class_la0_we & regen_qs),
+ .wd (loc_alert_class_class_la0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_class.class_la0.q ),
+
+ // to register interface (read)
+ .qs (loc_alert_class_class_la0_qs)
+ );
+
+
+ // F[class_la1]: 3:2
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_loc_alert_class_class_la1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (loc_alert_class_class_la1_we & regen_qs),
+ .wd (loc_alert_class_class_la1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_class.class_la1.q ),
+
+ // to register interface (read)
+ .qs (loc_alert_class_class_la1_qs)
+ );
+
+
+ // F[class_la2]: 5:4
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_loc_alert_class_class_la2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (loc_alert_class_class_la2_we & regen_qs),
+ .wd (loc_alert_class_class_la2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_class.class_la2.q ),
+
+ // to register interface (read)
+ .qs (loc_alert_class_class_la2_qs)
+ );
+
+
+ // F[class_la3]: 7:6
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_loc_alert_class_class_la3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (loc_alert_class_class_la3_we & regen_qs),
+ .wd (loc_alert_class_class_la3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_class.class_la3.q ),
+
+ // to register interface (read)
+ .qs (loc_alert_class_class_la3_qs)
+ );
+
+
+ // R[loc_alert_cause]: V(False)
+
+ // F[la0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_loc_alert_cause_la0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (loc_alert_cause_la0_we),
+ .wd (loc_alert_cause_la0_wd),
+
+ // from internal hardware
+ .de (hw2reg.loc_alert_cause.la0.de),
+ .d (hw2reg.loc_alert_cause.la0.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_cause.la0.q ),
+
+ // to register interface (read)
+ .qs (loc_alert_cause_la0_qs)
+ );
+
+
+ // F[la1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_loc_alert_cause_la1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (loc_alert_cause_la1_we),
+ .wd (loc_alert_cause_la1_wd),
+
+ // from internal hardware
+ .de (hw2reg.loc_alert_cause.la1.de),
+ .d (hw2reg.loc_alert_cause.la1.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_cause.la1.q ),
+
+ // to register interface (read)
+ .qs (loc_alert_cause_la1_qs)
+ );
+
+
+ // F[la2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_loc_alert_cause_la2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (loc_alert_cause_la2_we),
+ .wd (loc_alert_cause_la2_wd),
+
+ // from internal hardware
+ .de (hw2reg.loc_alert_cause.la2.de),
+ .d (hw2reg.loc_alert_cause.la2.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_cause.la2.q ),
+
+ // to register interface (read)
+ .qs (loc_alert_cause_la2_qs)
+ );
+
+
+ // F[la3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_loc_alert_cause_la3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (loc_alert_cause_la3_we),
+ .wd (loc_alert_cause_la3_wd),
+
+ // from internal hardware
+ .de (hw2reg.loc_alert_cause.la3.de),
+ .d (hw2reg.loc_alert_cause.la3.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.loc_alert_cause.la3.q ),
+
+ // to register interface (read)
+ .qs (loc_alert_cause_la3_qs)
+ );
+
+
+ // R[classa_ctrl]: V(False)
+
+ // F[en]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_classa_ctrl_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_ctrl_en_we & regen_qs),
+ .wd (classa_ctrl_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl.en.q ),
+
+ // to register interface (read)
+ .qs (classa_ctrl_en_qs)
+ );
+
+
+ // F[lock]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_classa_ctrl_lock (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_ctrl_lock_we & regen_qs),
+ .wd (classa_ctrl_lock_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl.lock.q ),
+
+ // to register interface (read)
+ .qs (classa_ctrl_lock_qs)
+ );
+
+
+ // F[en_e0]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classa_ctrl_en_e0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_ctrl_en_e0_we & regen_qs),
+ .wd (classa_ctrl_en_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl.en_e0.q ),
+
+ // to register interface (read)
+ .qs (classa_ctrl_en_e0_qs)
+ );
+
+
+ // F[en_e1]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classa_ctrl_en_e1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_ctrl_en_e1_we & regen_qs),
+ .wd (classa_ctrl_en_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl.en_e1.q ),
+
+ // to register interface (read)
+ .qs (classa_ctrl_en_e1_qs)
+ );
+
+
+ // F[en_e2]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classa_ctrl_en_e2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_ctrl_en_e2_we & regen_qs),
+ .wd (classa_ctrl_en_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl.en_e2.q ),
+
+ // to register interface (read)
+ .qs (classa_ctrl_en_e2_qs)
+ );
+
+
+ // F[en_e3]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classa_ctrl_en_e3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_ctrl_en_e3_we & regen_qs),
+ .wd (classa_ctrl_en_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl.en_e3.q ),
+
+ // to register interface (read)
+ .qs (classa_ctrl_en_e3_qs)
+ );
+
+
+ // F[map_e0]: 7:6
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_classa_ctrl_map_e0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_ctrl_map_e0_we & regen_qs),
+ .wd (classa_ctrl_map_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl.map_e0.q ),
+
+ // to register interface (read)
+ .qs (classa_ctrl_map_e0_qs)
+ );
+
+
+ // F[map_e1]: 9:8
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h1)
+ ) u_classa_ctrl_map_e1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_ctrl_map_e1_we & regen_qs),
+ .wd (classa_ctrl_map_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl.map_e1.q ),
+
+ // to register interface (read)
+ .qs (classa_ctrl_map_e1_qs)
+ );
+
+
+ // F[map_e2]: 11:10
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h2)
+ ) u_classa_ctrl_map_e2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_ctrl_map_e2_we & regen_qs),
+ .wd (classa_ctrl_map_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl.map_e2.q ),
+
+ // to register interface (read)
+ .qs (classa_ctrl_map_e2_qs)
+ );
+
+
+ // F[map_e3]: 13:12
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h3)
+ ) u_classa_ctrl_map_e3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_ctrl_map_e3_we & regen_qs),
+ .wd (classa_ctrl_map_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_ctrl.map_e3.q ),
+
+ // to register interface (read)
+ .qs (classa_ctrl_map_e3_qs)
+ );
+
+
+ // R[classa_clren]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h1)
+ ) u_classa_clren (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (classa_clren_we),
+ .wd (classa_clren_wd),
+
+ // from internal hardware
+ .de (hw2reg.classa_clren.de),
+ .d (hw2reg.classa_clren.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (classa_clren_qs)
+ );
+
+
+ // R[classa_clr]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_classa_clr (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_clr_we & classa_clren_qs),
+ .wd (classa_clr_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.classa_clr.qe),
+ .q (reg2hw.classa_clr.q ),
+
+ .qs ()
+ );
+
+
+ // R[classa_accum_cnt]: V(True)
+
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_classa_accum_cnt (
+ .re (classa_accum_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classa_accum_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (classa_accum_cnt_qs)
+ );
+
+
+ // R[classa_accum_thresh]: V(False)
+
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_classa_accum_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_accum_thresh_we & regen_qs),
+ .wd (classa_accum_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_accum_thresh.q ),
+
+ // to register interface (read)
+ .qs (classa_accum_thresh_qs)
+ );
+
+
+ // R[classa_timeout_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classa_timeout_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_timeout_cyc_we & regen_qs),
+ .wd (classa_timeout_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_timeout_cyc.q ),
+
+ // to register interface (read)
+ .qs (classa_timeout_cyc_qs)
+ );
+
+
+ // R[classa_phase0_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classa_phase0_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_phase0_cyc_we & regen_qs),
+ .wd (classa_phase0_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_phase0_cyc.q ),
+
+ // to register interface (read)
+ .qs (classa_phase0_cyc_qs)
+ );
+
+
+ // R[classa_phase1_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classa_phase1_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_phase1_cyc_we & regen_qs),
+ .wd (classa_phase1_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_phase1_cyc.q ),
+
+ // to register interface (read)
+ .qs (classa_phase1_cyc_qs)
+ );
+
+
+ // R[classa_phase2_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classa_phase2_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_phase2_cyc_we & regen_qs),
+ .wd (classa_phase2_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_phase2_cyc.q ),
+
+ // to register interface (read)
+ .qs (classa_phase2_cyc_qs)
+ );
+
+
+ // R[classa_phase3_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classa_phase3_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classa_phase3_cyc_we & regen_qs),
+ .wd (classa_phase3_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classa_phase3_cyc.q ),
+
+ // to register interface (read)
+ .qs (classa_phase3_cyc_qs)
+ );
+
+
+ // R[classa_esc_cnt]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_classa_esc_cnt (
+ .re (classa_esc_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classa_esc_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (classa_esc_cnt_qs)
+ );
+
+
+ // R[classa_state]: V(True)
+
+ prim_subreg_ext #(
+ .DW (3)
+ ) u_classa_state (
+ .re (classa_state_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classa_state.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (classa_state_qs)
+ );
+
+
+ // R[classb_ctrl]: V(False)
+
+ // F[en]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_classb_ctrl_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_ctrl_en_we & regen_qs),
+ .wd (classb_ctrl_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl.en.q ),
+
+ // to register interface (read)
+ .qs (classb_ctrl_en_qs)
+ );
+
+
+ // F[lock]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_classb_ctrl_lock (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_ctrl_lock_we & regen_qs),
+ .wd (classb_ctrl_lock_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl.lock.q ),
+
+ // to register interface (read)
+ .qs (classb_ctrl_lock_qs)
+ );
+
+
+ // F[en_e0]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classb_ctrl_en_e0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_ctrl_en_e0_we & regen_qs),
+ .wd (classb_ctrl_en_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl.en_e0.q ),
+
+ // to register interface (read)
+ .qs (classb_ctrl_en_e0_qs)
+ );
+
+
+ // F[en_e1]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classb_ctrl_en_e1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_ctrl_en_e1_we & regen_qs),
+ .wd (classb_ctrl_en_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl.en_e1.q ),
+
+ // to register interface (read)
+ .qs (classb_ctrl_en_e1_qs)
+ );
+
+
+ // F[en_e2]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classb_ctrl_en_e2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_ctrl_en_e2_we & regen_qs),
+ .wd (classb_ctrl_en_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl.en_e2.q ),
+
+ // to register interface (read)
+ .qs (classb_ctrl_en_e2_qs)
+ );
+
+
+ // F[en_e3]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classb_ctrl_en_e3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_ctrl_en_e3_we & regen_qs),
+ .wd (classb_ctrl_en_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl.en_e3.q ),
+
+ // to register interface (read)
+ .qs (classb_ctrl_en_e3_qs)
+ );
+
+
+ // F[map_e0]: 7:6
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_classb_ctrl_map_e0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_ctrl_map_e0_we & regen_qs),
+ .wd (classb_ctrl_map_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl.map_e0.q ),
+
+ // to register interface (read)
+ .qs (classb_ctrl_map_e0_qs)
+ );
+
+
+ // F[map_e1]: 9:8
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h1)
+ ) u_classb_ctrl_map_e1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_ctrl_map_e1_we & regen_qs),
+ .wd (classb_ctrl_map_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl.map_e1.q ),
+
+ // to register interface (read)
+ .qs (classb_ctrl_map_e1_qs)
+ );
+
+
+ // F[map_e2]: 11:10
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h2)
+ ) u_classb_ctrl_map_e2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_ctrl_map_e2_we & regen_qs),
+ .wd (classb_ctrl_map_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl.map_e2.q ),
+
+ // to register interface (read)
+ .qs (classb_ctrl_map_e2_qs)
+ );
+
+
+ // F[map_e3]: 13:12
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h3)
+ ) u_classb_ctrl_map_e3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_ctrl_map_e3_we & regen_qs),
+ .wd (classb_ctrl_map_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_ctrl.map_e3.q ),
+
+ // to register interface (read)
+ .qs (classb_ctrl_map_e3_qs)
+ );
+
+
+ // R[classb_clren]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h1)
+ ) u_classb_clren (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (classb_clren_we),
+ .wd (classb_clren_wd),
+
+ // from internal hardware
+ .de (hw2reg.classb_clren.de),
+ .d (hw2reg.classb_clren.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (classb_clren_qs)
+ );
+
+
+ // R[classb_clr]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_classb_clr (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_clr_we & classb_clren_qs),
+ .wd (classb_clr_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.classb_clr.qe),
+ .q (reg2hw.classb_clr.q ),
+
+ .qs ()
+ );
+
+
+ // R[classb_accum_cnt]: V(True)
+
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_classb_accum_cnt (
+ .re (classb_accum_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classb_accum_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (classb_accum_cnt_qs)
+ );
+
+
+ // R[classb_accum_thresh]: V(False)
+
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_classb_accum_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_accum_thresh_we & regen_qs),
+ .wd (classb_accum_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_accum_thresh.q ),
+
+ // to register interface (read)
+ .qs (classb_accum_thresh_qs)
+ );
+
+
+ // R[classb_timeout_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classb_timeout_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_timeout_cyc_we & regen_qs),
+ .wd (classb_timeout_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_timeout_cyc.q ),
+
+ // to register interface (read)
+ .qs (classb_timeout_cyc_qs)
+ );
+
+
+ // R[classb_phase0_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classb_phase0_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_phase0_cyc_we & regen_qs),
+ .wd (classb_phase0_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_phase0_cyc.q ),
+
+ // to register interface (read)
+ .qs (classb_phase0_cyc_qs)
+ );
+
+
+ // R[classb_phase1_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classb_phase1_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_phase1_cyc_we & regen_qs),
+ .wd (classb_phase1_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_phase1_cyc.q ),
+
+ // to register interface (read)
+ .qs (classb_phase1_cyc_qs)
+ );
+
+
+ // R[classb_phase2_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classb_phase2_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_phase2_cyc_we & regen_qs),
+ .wd (classb_phase2_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_phase2_cyc.q ),
+
+ // to register interface (read)
+ .qs (classb_phase2_cyc_qs)
+ );
+
+
+ // R[classb_phase3_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classb_phase3_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classb_phase3_cyc_we & regen_qs),
+ .wd (classb_phase3_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classb_phase3_cyc.q ),
+
+ // to register interface (read)
+ .qs (classb_phase3_cyc_qs)
+ );
+
+
+ // R[classb_esc_cnt]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_classb_esc_cnt (
+ .re (classb_esc_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classb_esc_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (classb_esc_cnt_qs)
+ );
+
+
+ // R[classb_state]: V(True)
+
+ prim_subreg_ext #(
+ .DW (3)
+ ) u_classb_state (
+ .re (classb_state_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classb_state.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (classb_state_qs)
+ );
+
+
+ // R[classc_ctrl]: V(False)
+
+ // F[en]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_classc_ctrl_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_ctrl_en_we & regen_qs),
+ .wd (classc_ctrl_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl.en.q ),
+
+ // to register interface (read)
+ .qs (classc_ctrl_en_qs)
+ );
+
+
+ // F[lock]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_classc_ctrl_lock (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_ctrl_lock_we & regen_qs),
+ .wd (classc_ctrl_lock_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl.lock.q ),
+
+ // to register interface (read)
+ .qs (classc_ctrl_lock_qs)
+ );
+
+
+ // F[en_e0]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classc_ctrl_en_e0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_ctrl_en_e0_we & regen_qs),
+ .wd (classc_ctrl_en_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl.en_e0.q ),
+
+ // to register interface (read)
+ .qs (classc_ctrl_en_e0_qs)
+ );
+
+
+ // F[en_e1]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classc_ctrl_en_e1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_ctrl_en_e1_we & regen_qs),
+ .wd (classc_ctrl_en_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl.en_e1.q ),
+
+ // to register interface (read)
+ .qs (classc_ctrl_en_e1_qs)
+ );
+
+
+ // F[en_e2]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classc_ctrl_en_e2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_ctrl_en_e2_we & regen_qs),
+ .wd (classc_ctrl_en_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl.en_e2.q ),
+
+ // to register interface (read)
+ .qs (classc_ctrl_en_e2_qs)
+ );
+
+
+ // F[en_e3]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classc_ctrl_en_e3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_ctrl_en_e3_we & regen_qs),
+ .wd (classc_ctrl_en_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl.en_e3.q ),
+
+ // to register interface (read)
+ .qs (classc_ctrl_en_e3_qs)
+ );
+
+
+ // F[map_e0]: 7:6
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_classc_ctrl_map_e0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_ctrl_map_e0_we & regen_qs),
+ .wd (classc_ctrl_map_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl.map_e0.q ),
+
+ // to register interface (read)
+ .qs (classc_ctrl_map_e0_qs)
+ );
+
+
+ // F[map_e1]: 9:8
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h1)
+ ) u_classc_ctrl_map_e1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_ctrl_map_e1_we & regen_qs),
+ .wd (classc_ctrl_map_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl.map_e1.q ),
+
+ // to register interface (read)
+ .qs (classc_ctrl_map_e1_qs)
+ );
+
+
+ // F[map_e2]: 11:10
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h2)
+ ) u_classc_ctrl_map_e2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_ctrl_map_e2_we & regen_qs),
+ .wd (classc_ctrl_map_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl.map_e2.q ),
+
+ // to register interface (read)
+ .qs (classc_ctrl_map_e2_qs)
+ );
+
+
+ // F[map_e3]: 13:12
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h3)
+ ) u_classc_ctrl_map_e3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_ctrl_map_e3_we & regen_qs),
+ .wd (classc_ctrl_map_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_ctrl.map_e3.q ),
+
+ // to register interface (read)
+ .qs (classc_ctrl_map_e3_qs)
+ );
+
+
+ // R[classc_clren]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h1)
+ ) u_classc_clren (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (classc_clren_we),
+ .wd (classc_clren_wd),
+
+ // from internal hardware
+ .de (hw2reg.classc_clren.de),
+ .d (hw2reg.classc_clren.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (classc_clren_qs)
+ );
+
+
+ // R[classc_clr]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_classc_clr (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_clr_we & classc_clren_qs),
+ .wd (classc_clr_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.classc_clr.qe),
+ .q (reg2hw.classc_clr.q ),
+
+ .qs ()
+ );
+
+
+ // R[classc_accum_cnt]: V(True)
+
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_classc_accum_cnt (
+ .re (classc_accum_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classc_accum_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (classc_accum_cnt_qs)
+ );
+
+
+ // R[classc_accum_thresh]: V(False)
+
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_classc_accum_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_accum_thresh_we & regen_qs),
+ .wd (classc_accum_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_accum_thresh.q ),
+
+ // to register interface (read)
+ .qs (classc_accum_thresh_qs)
+ );
+
+
+ // R[classc_timeout_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classc_timeout_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_timeout_cyc_we & regen_qs),
+ .wd (classc_timeout_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_timeout_cyc.q ),
+
+ // to register interface (read)
+ .qs (classc_timeout_cyc_qs)
+ );
+
+
+ // R[classc_phase0_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classc_phase0_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_phase0_cyc_we & regen_qs),
+ .wd (classc_phase0_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_phase0_cyc.q ),
+
+ // to register interface (read)
+ .qs (classc_phase0_cyc_qs)
+ );
+
+
+ // R[classc_phase1_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classc_phase1_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_phase1_cyc_we & regen_qs),
+ .wd (classc_phase1_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_phase1_cyc.q ),
+
+ // to register interface (read)
+ .qs (classc_phase1_cyc_qs)
+ );
+
+
+ // R[classc_phase2_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classc_phase2_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_phase2_cyc_we & regen_qs),
+ .wd (classc_phase2_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_phase2_cyc.q ),
+
+ // to register interface (read)
+ .qs (classc_phase2_cyc_qs)
+ );
+
+
+ // R[classc_phase3_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classc_phase3_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classc_phase3_cyc_we & regen_qs),
+ .wd (classc_phase3_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classc_phase3_cyc.q ),
+
+ // to register interface (read)
+ .qs (classc_phase3_cyc_qs)
+ );
+
+
+ // R[classc_esc_cnt]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_classc_esc_cnt (
+ .re (classc_esc_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classc_esc_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (classc_esc_cnt_qs)
+ );
+
+
+ // R[classc_state]: V(True)
+
+ prim_subreg_ext #(
+ .DW (3)
+ ) u_classc_state (
+ .re (classc_state_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classc_state.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (classc_state_qs)
+ );
+
+
+ // R[classd_ctrl]: V(False)
+
+ // F[en]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_classd_ctrl_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_ctrl_en_we & regen_qs),
+ .wd (classd_ctrl_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl.en.q ),
+
+ // to register interface (read)
+ .qs (classd_ctrl_en_qs)
+ );
+
+
+ // F[lock]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_classd_ctrl_lock (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_ctrl_lock_we & regen_qs),
+ .wd (classd_ctrl_lock_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl.lock.q ),
+
+ // to register interface (read)
+ .qs (classd_ctrl_lock_qs)
+ );
+
+
+ // F[en_e0]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classd_ctrl_en_e0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_ctrl_en_e0_we & regen_qs),
+ .wd (classd_ctrl_en_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl.en_e0.q ),
+
+ // to register interface (read)
+ .qs (classd_ctrl_en_e0_qs)
+ );
+
+
+ // F[en_e1]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classd_ctrl_en_e1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_ctrl_en_e1_we & regen_qs),
+ .wd (classd_ctrl_en_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl.en_e1.q ),
+
+ // to register interface (read)
+ .qs (classd_ctrl_en_e1_qs)
+ );
+
+
+ // F[en_e2]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classd_ctrl_en_e2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_ctrl_en_e2_we & regen_qs),
+ .wd (classd_ctrl_en_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl.en_e2.q ),
+
+ // to register interface (read)
+ .qs (classd_ctrl_en_e2_qs)
+ );
+
+
+ // F[en_e3]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h1)
+ ) u_classd_ctrl_en_e3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_ctrl_en_e3_we & regen_qs),
+ .wd (classd_ctrl_en_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl.en_e3.q ),
+
+ // to register interface (read)
+ .qs (classd_ctrl_en_e3_qs)
+ );
+
+
+ // F[map_e0]: 7:6
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_classd_ctrl_map_e0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_ctrl_map_e0_we & regen_qs),
+ .wd (classd_ctrl_map_e0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl.map_e0.q ),
+
+ // to register interface (read)
+ .qs (classd_ctrl_map_e0_qs)
+ );
+
+
+ // F[map_e1]: 9:8
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h1)
+ ) u_classd_ctrl_map_e1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_ctrl_map_e1_we & regen_qs),
+ .wd (classd_ctrl_map_e1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl.map_e1.q ),
+
+ // to register interface (read)
+ .qs (classd_ctrl_map_e1_qs)
+ );
+
+
+ // F[map_e2]: 11:10
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h2)
+ ) u_classd_ctrl_map_e2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_ctrl_map_e2_we & regen_qs),
+ .wd (classd_ctrl_map_e2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl.map_e2.q ),
+
+ // to register interface (read)
+ .qs (classd_ctrl_map_e2_qs)
+ );
+
+
+ // F[map_e3]: 13:12
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h3)
+ ) u_classd_ctrl_map_e3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_ctrl_map_e3_we & regen_qs),
+ .wd (classd_ctrl_map_e3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_ctrl.map_e3.q ),
+
+ // to register interface (read)
+ .qs (classd_ctrl_map_e3_qs)
+ );
+
+
+ // R[classd_clren]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h1)
+ ) u_classd_clren (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (classd_clren_we),
+ .wd (classd_clren_wd),
+
+ // from internal hardware
+ .de (hw2reg.classd_clren.de),
+ .d (hw2reg.classd_clren.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (classd_clren_qs)
+ );
+
+
+ // R[classd_clr]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_classd_clr (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_clr_we & classd_clren_qs),
+ .wd (classd_clr_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.classd_clr.qe),
+ .q (reg2hw.classd_clr.q ),
+
+ .qs ()
+ );
+
+
+ // R[classd_accum_cnt]: V(True)
+
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_classd_accum_cnt (
+ .re (classd_accum_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classd_accum_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (classd_accum_cnt_qs)
+ );
+
+
+ // R[classd_accum_thresh]: V(False)
+
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h0)
+ ) u_classd_accum_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_accum_thresh_we & regen_qs),
+ .wd (classd_accum_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_accum_thresh.q ),
+
+ // to register interface (read)
+ .qs (classd_accum_thresh_qs)
+ );
+
+
+ // R[classd_timeout_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classd_timeout_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_timeout_cyc_we & regen_qs),
+ .wd (classd_timeout_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_timeout_cyc.q ),
+
+ // to register interface (read)
+ .qs (classd_timeout_cyc_qs)
+ );
+
+
+ // R[classd_phase0_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classd_phase0_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_phase0_cyc_we & regen_qs),
+ .wd (classd_phase0_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_phase0_cyc.q ),
+
+ // to register interface (read)
+ .qs (classd_phase0_cyc_qs)
+ );
+
+
+ // R[classd_phase1_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classd_phase1_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_phase1_cyc_we & regen_qs),
+ .wd (classd_phase1_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_phase1_cyc.q ),
+
+ // to register interface (read)
+ .qs (classd_phase1_cyc_qs)
+ );
+
+
+ // R[classd_phase2_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classd_phase2_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_phase2_cyc_we & regen_qs),
+ .wd (classd_phase2_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_phase2_cyc.q ),
+
+ // to register interface (read)
+ .qs (classd_phase2_cyc_qs)
+ );
+
+
+ // R[classd_phase3_cyc]: V(False)
+
+ prim_subreg #(
+ .DW (32),
+ .SWACCESS("RW"),
+ .RESVAL (32'h0)
+ ) u_classd_phase3_cyc (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (classd_phase3_cyc_we & regen_qs),
+ .wd (classd_phase3_cyc_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.classd_phase3_cyc.q ),
+
+ // to register interface (read)
+ .qs (classd_phase3_cyc_qs)
+ );
+
+
+ // R[classd_esc_cnt]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_classd_esc_cnt (
+ .re (classd_esc_cnt_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classd_esc_cnt.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (classd_esc_cnt_qs)
+ );
+
+
+ // R[classd_state]: V(True)
+
+ prim_subreg_ext #(
+ .DW (3)
+ ) u_classd_state (
+ .re (classd_state_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.classd_state.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (classd_state_qs)
+ );
+
+
+
+ logic [58:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
+ addr_hit[1] = (reg_addr == ALERT_HANDLER_INTR_ENABLE_OFFSET);
+ addr_hit[2] = (reg_addr == ALERT_HANDLER_INTR_TEST_OFFSET);
+ addr_hit[3] = (reg_addr == ALERT_HANDLER_REGEN_OFFSET);
+ addr_hit[4] = (reg_addr == ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET);
+ addr_hit[5] = (reg_addr == ALERT_HANDLER_ALERT_EN_OFFSET);
+ addr_hit[6] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_OFFSET);
+ addr_hit[7] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_OFFSET);
+ addr_hit[8] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_OFFSET);
+ addr_hit[9] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_OFFSET);
+ addr_hit[10] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_OFFSET);
+ addr_hit[11] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
+ addr_hit[12] = (reg_addr == ALERT_HANDLER_CLASSA_CLREN_OFFSET);
+ addr_hit[13] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
+ addr_hit[14] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
+ addr_hit[15] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
+ addr_hit[16] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
+ addr_hit[17] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
+ addr_hit[18] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
+ addr_hit[19] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
+ addr_hit[20] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
+ addr_hit[21] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
+ addr_hit[22] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
+ addr_hit[23] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
+ addr_hit[24] = (reg_addr == ALERT_HANDLER_CLASSB_CLREN_OFFSET);
+ addr_hit[25] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
+ addr_hit[26] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
+ addr_hit[27] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
+ addr_hit[28] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
+ addr_hit[29] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
+ addr_hit[30] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
+ addr_hit[31] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
+ addr_hit[32] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
+ addr_hit[33] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
+ addr_hit[34] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
+ addr_hit[35] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
+ addr_hit[36] = (reg_addr == ALERT_HANDLER_CLASSC_CLREN_OFFSET);
+ addr_hit[37] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
+ addr_hit[38] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
+ addr_hit[39] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
+ addr_hit[40] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
+ addr_hit[41] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
+ addr_hit[42] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
+ addr_hit[43] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
+ addr_hit[44] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
+ addr_hit[45] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
+ addr_hit[46] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
+ addr_hit[47] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
+ addr_hit[48] = (reg_addr == ALERT_HANDLER_CLASSD_CLREN_OFFSET);
+ addr_hit[49] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
+ addr_hit[50] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
+ addr_hit[51] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
+ addr_hit[52] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
+ addr_hit[53] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
+ addr_hit[54] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
+ addr_hit[55] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
+ addr_hit[56] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
+ addr_hit[57] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
+ addr_hit[58] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
+ end
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ addrmiss <= 1'b0;
+ end else if (reg_re || reg_we) begin
+ addrmiss <= ~|addr_hit;
+ end
+ end
+
+ // Write Enable signal
+
+ assign intr_state_classa_we = addr_hit[0] && reg_we;
+ assign intr_state_classa_wd = reg_wdata[0];
+
+ assign intr_state_classb_we = addr_hit[0] && reg_we;
+ assign intr_state_classb_wd = reg_wdata[1];
+
+ assign intr_state_classc_we = addr_hit[0] && reg_we;
+ assign intr_state_classc_wd = reg_wdata[2];
+
+ assign intr_state_classd_we = addr_hit[0] && reg_we;
+ assign intr_state_classd_wd = reg_wdata[3];
+
+ assign intr_enable_classa_we = addr_hit[1] && reg_we;
+ assign intr_enable_classa_wd = reg_wdata[0];
+
+ assign intr_enable_classb_we = addr_hit[1] && reg_we;
+ assign intr_enable_classb_wd = reg_wdata[1];
+
+ assign intr_enable_classc_we = addr_hit[1] && reg_we;
+ assign intr_enable_classc_wd = reg_wdata[2];
+
+ assign intr_enable_classd_we = addr_hit[1] && reg_we;
+ assign intr_enable_classd_wd = reg_wdata[3];
+
+ assign intr_test_classa_we = addr_hit[2] && reg_we;
+ assign intr_test_classa_wd = reg_wdata[0];
+
+ assign intr_test_classb_we = addr_hit[2] && reg_we;
+ assign intr_test_classb_wd = reg_wdata[1];
+
+ assign intr_test_classc_we = addr_hit[2] && reg_we;
+ assign intr_test_classc_wd = reg_wdata[2];
+
+ assign intr_test_classd_we = addr_hit[2] && reg_we;
+ assign intr_test_classd_wd = reg_wdata[3];
+
+ assign regen_we = addr_hit[3] && reg_we;
+ assign regen_wd = reg_wdata[0];
+
+ assign ping_timeout_cyc_we = addr_hit[4] && reg_we;
+ assign ping_timeout_cyc_wd = reg_wdata[23:0];
+
+ assign alert_en_en_a0_we = addr_hit[5] && reg_we;
+ assign alert_en_en_a0_wd = reg_wdata[0];
+
+ assign alert_en_en_a1_we = addr_hit[5] && reg_we;
+ assign alert_en_en_a1_wd = reg_wdata[1];
+
+ assign alert_en_en_a2_we = addr_hit[5] && reg_we;
+ assign alert_en_en_a2_wd = reg_wdata[2];
+
+ assign alert_en_en_a3_we = addr_hit[5] && reg_we;
+ assign alert_en_en_a3_wd = reg_wdata[3];
+
+ assign alert_class_class_a0_we = addr_hit[6] && reg_we;
+ assign alert_class_class_a0_wd = reg_wdata[1:0];
+
+ assign alert_class_class_a1_we = addr_hit[6] && reg_we;
+ assign alert_class_class_a1_wd = reg_wdata[3:2];
+
+ assign alert_class_class_a2_we = addr_hit[6] && reg_we;
+ assign alert_class_class_a2_wd = reg_wdata[5:4];
+
+ assign alert_class_class_a3_we = addr_hit[6] && reg_we;
+ assign alert_class_class_a3_wd = reg_wdata[7:6];
+
+ assign alert_cause_a0_we = addr_hit[7] && reg_we;
+ assign alert_cause_a0_wd = reg_wdata[0];
+
+ assign alert_cause_a1_we = addr_hit[7] && reg_we;
+ assign alert_cause_a1_wd = reg_wdata[1];
+
+ assign alert_cause_a2_we = addr_hit[7] && reg_we;
+ assign alert_cause_a2_wd = reg_wdata[2];
+
+ assign alert_cause_a3_we = addr_hit[7] && reg_we;
+ assign alert_cause_a3_wd = reg_wdata[3];
+
+ assign loc_alert_en_en_la0_we = addr_hit[8] && reg_we;
+ assign loc_alert_en_en_la0_wd = reg_wdata[0];
+
+ assign loc_alert_en_en_la1_we = addr_hit[8] && reg_we;
+ assign loc_alert_en_en_la1_wd = reg_wdata[1];
+
+ assign loc_alert_en_en_la2_we = addr_hit[8] && reg_we;
+ assign loc_alert_en_en_la2_wd = reg_wdata[2];
+
+ assign loc_alert_en_en_la3_we = addr_hit[8] && reg_we;
+ assign loc_alert_en_en_la3_wd = reg_wdata[3];
+
+ assign loc_alert_class_class_la0_we = addr_hit[9] && reg_we;
+ assign loc_alert_class_class_la0_wd = reg_wdata[1:0];
+
+ assign loc_alert_class_class_la1_we = addr_hit[9] && reg_we;
+ assign loc_alert_class_class_la1_wd = reg_wdata[3:2];
+
+ assign loc_alert_class_class_la2_we = addr_hit[9] && reg_we;
+ assign loc_alert_class_class_la2_wd = reg_wdata[5:4];
+
+ assign loc_alert_class_class_la3_we = addr_hit[9] && reg_we;
+ assign loc_alert_class_class_la3_wd = reg_wdata[7:6];
+
+ assign loc_alert_cause_la0_we = addr_hit[10] && reg_we;
+ assign loc_alert_cause_la0_wd = reg_wdata[0];
+
+ assign loc_alert_cause_la1_we = addr_hit[10] && reg_we;
+ assign loc_alert_cause_la1_wd = reg_wdata[1];
+
+ assign loc_alert_cause_la2_we = addr_hit[10] && reg_we;
+ assign loc_alert_cause_la2_wd = reg_wdata[2];
+
+ assign loc_alert_cause_la3_we = addr_hit[10] && reg_we;
+ assign loc_alert_cause_la3_wd = reg_wdata[3];
+
+ assign classa_ctrl_en_we = addr_hit[11] && reg_we;
+ assign classa_ctrl_en_wd = reg_wdata[0];
+
+ assign classa_ctrl_lock_we = addr_hit[11] && reg_we;
+ assign classa_ctrl_lock_wd = reg_wdata[1];
+
+ assign classa_ctrl_en_e0_we = addr_hit[11] && reg_we;
+ assign classa_ctrl_en_e0_wd = reg_wdata[2];
+
+ assign classa_ctrl_en_e1_we = addr_hit[11] && reg_we;
+ assign classa_ctrl_en_e1_wd = reg_wdata[3];
+
+ assign classa_ctrl_en_e2_we = addr_hit[11] && reg_we;
+ assign classa_ctrl_en_e2_wd = reg_wdata[4];
+
+ assign classa_ctrl_en_e3_we = addr_hit[11] && reg_we;
+ assign classa_ctrl_en_e3_wd = reg_wdata[5];
+
+ assign classa_ctrl_map_e0_we = addr_hit[11] && reg_we;
+ assign classa_ctrl_map_e0_wd = reg_wdata[7:6];
+
+ assign classa_ctrl_map_e1_we = addr_hit[11] && reg_we;
+ assign classa_ctrl_map_e1_wd = reg_wdata[9:8];
+
+ assign classa_ctrl_map_e2_we = addr_hit[11] && reg_we;
+ assign classa_ctrl_map_e2_wd = reg_wdata[11:10];
+
+ assign classa_ctrl_map_e3_we = addr_hit[11] && reg_we;
+ assign classa_ctrl_map_e3_wd = reg_wdata[13:12];
+
+ assign classa_clren_we = addr_hit[12] && reg_we;
+ assign classa_clren_wd = reg_wdata[0];
+
+ assign classa_clr_we = addr_hit[13] && reg_we;
+ assign classa_clr_wd = reg_wdata[0];
+
+ assign classa_accum_cnt_re = addr_hit[14] && reg_re;
+
+ assign classa_accum_thresh_we = addr_hit[15] && reg_we;
+ assign classa_accum_thresh_wd = reg_wdata[15:0];
+
+ assign classa_timeout_cyc_we = addr_hit[16] && reg_we;
+ assign classa_timeout_cyc_wd = reg_wdata[31:0];
+
+ assign classa_phase0_cyc_we = addr_hit[17] && reg_we;
+ assign classa_phase0_cyc_wd = reg_wdata[31:0];
+
+ assign classa_phase1_cyc_we = addr_hit[18] && reg_we;
+ assign classa_phase1_cyc_wd = reg_wdata[31:0];
+
+ assign classa_phase2_cyc_we = addr_hit[19] && reg_we;
+ assign classa_phase2_cyc_wd = reg_wdata[31:0];
+
+ assign classa_phase3_cyc_we = addr_hit[20] && reg_we;
+ assign classa_phase3_cyc_wd = reg_wdata[31:0];
+
+ assign classa_esc_cnt_re = addr_hit[21] && reg_re;
+
+ assign classa_state_re = addr_hit[22] && reg_re;
+
+ assign classb_ctrl_en_we = addr_hit[23] && reg_we;
+ assign classb_ctrl_en_wd = reg_wdata[0];
+
+ assign classb_ctrl_lock_we = addr_hit[23] && reg_we;
+ assign classb_ctrl_lock_wd = reg_wdata[1];
+
+ assign classb_ctrl_en_e0_we = addr_hit[23] && reg_we;
+ assign classb_ctrl_en_e0_wd = reg_wdata[2];
+
+ assign classb_ctrl_en_e1_we = addr_hit[23] && reg_we;
+ assign classb_ctrl_en_e1_wd = reg_wdata[3];
+
+ assign classb_ctrl_en_e2_we = addr_hit[23] && reg_we;
+ assign classb_ctrl_en_e2_wd = reg_wdata[4];
+
+ assign classb_ctrl_en_e3_we = addr_hit[23] && reg_we;
+ assign classb_ctrl_en_e3_wd = reg_wdata[5];
+
+ assign classb_ctrl_map_e0_we = addr_hit[23] && reg_we;
+ assign classb_ctrl_map_e0_wd = reg_wdata[7:6];
+
+ assign classb_ctrl_map_e1_we = addr_hit[23] && reg_we;
+ assign classb_ctrl_map_e1_wd = reg_wdata[9:8];
+
+ assign classb_ctrl_map_e2_we = addr_hit[23] && reg_we;
+ assign classb_ctrl_map_e2_wd = reg_wdata[11:10];
+
+ assign classb_ctrl_map_e3_we = addr_hit[23] && reg_we;
+ assign classb_ctrl_map_e3_wd = reg_wdata[13:12];
+
+ assign classb_clren_we = addr_hit[24] && reg_we;
+ assign classb_clren_wd = reg_wdata[0];
+
+ assign classb_clr_we = addr_hit[25] && reg_we;
+ assign classb_clr_wd = reg_wdata[0];
+
+ assign classb_accum_cnt_re = addr_hit[26] && reg_re;
+
+ assign classb_accum_thresh_we = addr_hit[27] && reg_we;
+ assign classb_accum_thresh_wd = reg_wdata[15:0];
+
+ assign classb_timeout_cyc_we = addr_hit[28] && reg_we;
+ assign classb_timeout_cyc_wd = reg_wdata[31:0];
+
+ assign classb_phase0_cyc_we = addr_hit[29] && reg_we;
+ assign classb_phase0_cyc_wd = reg_wdata[31:0];
+
+ assign classb_phase1_cyc_we = addr_hit[30] && reg_we;
+ assign classb_phase1_cyc_wd = reg_wdata[31:0];
+
+ assign classb_phase2_cyc_we = addr_hit[31] && reg_we;
+ assign classb_phase2_cyc_wd = reg_wdata[31:0];
+
+ assign classb_phase3_cyc_we = addr_hit[32] && reg_we;
+ assign classb_phase3_cyc_wd = reg_wdata[31:0];
+
+ assign classb_esc_cnt_re = addr_hit[33] && reg_re;
+
+ assign classb_state_re = addr_hit[34] && reg_re;
+
+ assign classc_ctrl_en_we = addr_hit[35] && reg_we;
+ assign classc_ctrl_en_wd = reg_wdata[0];
+
+ assign classc_ctrl_lock_we = addr_hit[35] && reg_we;
+ assign classc_ctrl_lock_wd = reg_wdata[1];
+
+ assign classc_ctrl_en_e0_we = addr_hit[35] && reg_we;
+ assign classc_ctrl_en_e0_wd = reg_wdata[2];
+
+ assign classc_ctrl_en_e1_we = addr_hit[35] && reg_we;
+ assign classc_ctrl_en_e1_wd = reg_wdata[3];
+
+ assign classc_ctrl_en_e2_we = addr_hit[35] && reg_we;
+ assign classc_ctrl_en_e2_wd = reg_wdata[4];
+
+ assign classc_ctrl_en_e3_we = addr_hit[35] && reg_we;
+ assign classc_ctrl_en_e3_wd = reg_wdata[5];
+
+ assign classc_ctrl_map_e0_we = addr_hit[35] && reg_we;
+ assign classc_ctrl_map_e0_wd = reg_wdata[7:6];
+
+ assign classc_ctrl_map_e1_we = addr_hit[35] && reg_we;
+ assign classc_ctrl_map_e1_wd = reg_wdata[9:8];
+
+ assign classc_ctrl_map_e2_we = addr_hit[35] && reg_we;
+ assign classc_ctrl_map_e2_wd = reg_wdata[11:10];
+
+ assign classc_ctrl_map_e3_we = addr_hit[35] && reg_we;
+ assign classc_ctrl_map_e3_wd = reg_wdata[13:12];
+
+ assign classc_clren_we = addr_hit[36] && reg_we;
+ assign classc_clren_wd = reg_wdata[0];
+
+ assign classc_clr_we = addr_hit[37] && reg_we;
+ assign classc_clr_wd = reg_wdata[0];
+
+ assign classc_accum_cnt_re = addr_hit[38] && reg_re;
+
+ assign classc_accum_thresh_we = addr_hit[39] && reg_we;
+ assign classc_accum_thresh_wd = reg_wdata[15:0];
+
+ assign classc_timeout_cyc_we = addr_hit[40] && reg_we;
+ assign classc_timeout_cyc_wd = reg_wdata[31:0];
+
+ assign classc_phase0_cyc_we = addr_hit[41] && reg_we;
+ assign classc_phase0_cyc_wd = reg_wdata[31:0];
+
+ assign classc_phase1_cyc_we = addr_hit[42] && reg_we;
+ assign classc_phase1_cyc_wd = reg_wdata[31:0];
+
+ assign classc_phase2_cyc_we = addr_hit[43] && reg_we;
+ assign classc_phase2_cyc_wd = reg_wdata[31:0];
+
+ assign classc_phase3_cyc_we = addr_hit[44] && reg_we;
+ assign classc_phase3_cyc_wd = reg_wdata[31:0];
+
+ assign classc_esc_cnt_re = addr_hit[45] && reg_re;
+
+ assign classc_state_re = addr_hit[46] && reg_re;
+
+ assign classd_ctrl_en_we = addr_hit[47] && reg_we;
+ assign classd_ctrl_en_wd = reg_wdata[0];
+
+ assign classd_ctrl_lock_we = addr_hit[47] && reg_we;
+ assign classd_ctrl_lock_wd = reg_wdata[1];
+
+ assign classd_ctrl_en_e0_we = addr_hit[47] && reg_we;
+ assign classd_ctrl_en_e0_wd = reg_wdata[2];
+
+ assign classd_ctrl_en_e1_we = addr_hit[47] && reg_we;
+ assign classd_ctrl_en_e1_wd = reg_wdata[3];
+
+ assign classd_ctrl_en_e2_we = addr_hit[47] && reg_we;
+ assign classd_ctrl_en_e2_wd = reg_wdata[4];
+
+ assign classd_ctrl_en_e3_we = addr_hit[47] && reg_we;
+ assign classd_ctrl_en_e3_wd = reg_wdata[5];
+
+ assign classd_ctrl_map_e0_we = addr_hit[47] && reg_we;
+ assign classd_ctrl_map_e0_wd = reg_wdata[7:6];
+
+ assign classd_ctrl_map_e1_we = addr_hit[47] && reg_we;
+ assign classd_ctrl_map_e1_wd = reg_wdata[9:8];
+
+ assign classd_ctrl_map_e2_we = addr_hit[47] && reg_we;
+ assign classd_ctrl_map_e2_wd = reg_wdata[11:10];
+
+ assign classd_ctrl_map_e3_we = addr_hit[47] && reg_we;
+ assign classd_ctrl_map_e3_wd = reg_wdata[13:12];
+
+ assign classd_clren_we = addr_hit[48] && reg_we;
+ assign classd_clren_wd = reg_wdata[0];
+
+ assign classd_clr_we = addr_hit[49] && reg_we;
+ assign classd_clr_wd = reg_wdata[0];
+
+ assign classd_accum_cnt_re = addr_hit[50] && reg_re;
+
+ assign classd_accum_thresh_we = addr_hit[51] && reg_we;
+ assign classd_accum_thresh_wd = reg_wdata[15:0];
+
+ assign classd_timeout_cyc_we = addr_hit[52] && reg_we;
+ assign classd_timeout_cyc_wd = reg_wdata[31:0];
+
+ assign classd_phase0_cyc_we = addr_hit[53] && reg_we;
+ assign classd_phase0_cyc_wd = reg_wdata[31:0];
+
+ assign classd_phase1_cyc_we = addr_hit[54] && reg_we;
+ assign classd_phase1_cyc_wd = reg_wdata[31:0];
+
+ assign classd_phase2_cyc_we = addr_hit[55] && reg_we;
+ assign classd_phase2_cyc_wd = reg_wdata[31:0];
+
+ assign classd_phase3_cyc_we = addr_hit[56] && reg_we;
+ assign classd_phase3_cyc_wd = reg_wdata[31:0];
+
+ assign classd_esc_cnt_re = addr_hit[57] && reg_re;
+
+ assign classd_state_re = addr_hit[58] && reg_re;
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = intr_state_classa_qs;
+ reg_rdata_next[1] = intr_state_classb_qs;
+ reg_rdata_next[2] = intr_state_classc_qs;
+ reg_rdata_next[3] = intr_state_classd_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[0] = intr_enable_classa_qs;
+ reg_rdata_next[1] = intr_enable_classb_qs;
+ reg_rdata_next[2] = intr_enable_classc_qs;
+ reg_rdata_next[3] = intr_enable_classd_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
+ reg_rdata_next[2] = '0;
+ reg_rdata_next[3] = '0;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[0] = regen_qs;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[23:0] = ping_timeout_cyc_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[0] = alert_en_en_a0_qs;
+ reg_rdata_next[1] = alert_en_en_a1_qs;
+ reg_rdata_next[2] = alert_en_en_a2_qs;
+ reg_rdata_next[3] = alert_en_en_a3_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[1:0] = alert_class_class_a0_qs;
+ reg_rdata_next[3:2] = alert_class_class_a1_qs;
+ reg_rdata_next[5:4] = alert_class_class_a2_qs;
+ reg_rdata_next[7:6] = alert_class_class_a3_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[0] = alert_cause_a0_qs;
+ reg_rdata_next[1] = alert_cause_a1_qs;
+ reg_rdata_next[2] = alert_cause_a2_qs;
+ reg_rdata_next[3] = alert_cause_a3_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[0] = loc_alert_en_en_la0_qs;
+ reg_rdata_next[1] = loc_alert_en_en_la1_qs;
+ reg_rdata_next[2] = loc_alert_en_en_la2_qs;
+ reg_rdata_next[3] = loc_alert_en_en_la3_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[1:0] = loc_alert_class_class_la0_qs;
+ reg_rdata_next[3:2] = loc_alert_class_class_la1_qs;
+ reg_rdata_next[5:4] = loc_alert_class_class_la2_qs;
+ reg_rdata_next[7:6] = loc_alert_class_class_la3_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[0] = loc_alert_cause_la0_qs;
+ reg_rdata_next[1] = loc_alert_cause_la1_qs;
+ reg_rdata_next[2] = loc_alert_cause_la2_qs;
+ reg_rdata_next[3] = loc_alert_cause_la3_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[0] = classa_ctrl_en_qs;
+ reg_rdata_next[1] = classa_ctrl_lock_qs;
+ reg_rdata_next[2] = classa_ctrl_en_e0_qs;
+ reg_rdata_next[3] = classa_ctrl_en_e1_qs;
+ reg_rdata_next[4] = classa_ctrl_en_e2_qs;
+ reg_rdata_next[5] = classa_ctrl_en_e3_qs;
+ reg_rdata_next[7:6] = classa_ctrl_map_e0_qs;
+ reg_rdata_next[9:8] = classa_ctrl_map_e1_qs;
+ reg_rdata_next[11:10] = classa_ctrl_map_e2_qs;
+ reg_rdata_next[13:12] = classa_ctrl_map_e3_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[0] = classa_clren_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[15:0] = classa_accum_cnt_qs;
+ end
+
+ addr_hit[15]: begin
+ reg_rdata_next[15:0] = classa_accum_thresh_qs;
+ end
+
+ addr_hit[16]: begin
+ reg_rdata_next[31:0] = classa_timeout_cyc_qs;
+ end
+
+ addr_hit[17]: begin
+ reg_rdata_next[31:0] = classa_phase0_cyc_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[31:0] = classa_phase1_cyc_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[31:0] = classa_phase2_cyc_qs;
+ end
+
+ addr_hit[20]: begin
+ reg_rdata_next[31:0] = classa_phase3_cyc_qs;
+ end
+
+ addr_hit[21]: begin
+ reg_rdata_next[31:0] = classa_esc_cnt_qs;
+ end
+
+ addr_hit[22]: begin
+ reg_rdata_next[2:0] = classa_state_qs;
+ end
+
+ addr_hit[23]: begin
+ reg_rdata_next[0] = classb_ctrl_en_qs;
+ reg_rdata_next[1] = classb_ctrl_lock_qs;
+ reg_rdata_next[2] = classb_ctrl_en_e0_qs;
+ reg_rdata_next[3] = classb_ctrl_en_e1_qs;
+ reg_rdata_next[4] = classb_ctrl_en_e2_qs;
+ reg_rdata_next[5] = classb_ctrl_en_e3_qs;
+ reg_rdata_next[7:6] = classb_ctrl_map_e0_qs;
+ reg_rdata_next[9:8] = classb_ctrl_map_e1_qs;
+ reg_rdata_next[11:10] = classb_ctrl_map_e2_qs;
+ reg_rdata_next[13:12] = classb_ctrl_map_e3_qs;
+ end
+
+ addr_hit[24]: begin
+ reg_rdata_next[0] = classb_clren_qs;
+ end
+
+ addr_hit[25]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ addr_hit[26]: begin
+ reg_rdata_next[15:0] = classb_accum_cnt_qs;
+ end
+
+ addr_hit[27]: begin
+ reg_rdata_next[15:0] = classb_accum_thresh_qs;
+ end
+
+ addr_hit[28]: begin
+ reg_rdata_next[31:0] = classb_timeout_cyc_qs;
+ end
+
+ addr_hit[29]: begin
+ reg_rdata_next[31:0] = classb_phase0_cyc_qs;
+ end
+
+ addr_hit[30]: begin
+ reg_rdata_next[31:0] = classb_phase1_cyc_qs;
+ end
+
+ addr_hit[31]: begin
+ reg_rdata_next[31:0] = classb_phase2_cyc_qs;
+ end
+
+ addr_hit[32]: begin
+ reg_rdata_next[31:0] = classb_phase3_cyc_qs;
+ end
+
+ addr_hit[33]: begin
+ reg_rdata_next[31:0] = classb_esc_cnt_qs;
+ end
+
+ addr_hit[34]: begin
+ reg_rdata_next[2:0] = classb_state_qs;
+ end
+
+ addr_hit[35]: begin
+ reg_rdata_next[0] = classc_ctrl_en_qs;
+ reg_rdata_next[1] = classc_ctrl_lock_qs;
+ reg_rdata_next[2] = classc_ctrl_en_e0_qs;
+ reg_rdata_next[3] = classc_ctrl_en_e1_qs;
+ reg_rdata_next[4] = classc_ctrl_en_e2_qs;
+ reg_rdata_next[5] = classc_ctrl_en_e3_qs;
+ reg_rdata_next[7:6] = classc_ctrl_map_e0_qs;
+ reg_rdata_next[9:8] = classc_ctrl_map_e1_qs;
+ reg_rdata_next[11:10] = classc_ctrl_map_e2_qs;
+ reg_rdata_next[13:12] = classc_ctrl_map_e3_qs;
+ end
+
+ addr_hit[36]: begin
+ reg_rdata_next[0] = classc_clren_qs;
+ end
+
+ addr_hit[37]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ addr_hit[38]: begin
+ reg_rdata_next[15:0] = classc_accum_cnt_qs;
+ end
+
+ addr_hit[39]: begin
+ reg_rdata_next[15:0] = classc_accum_thresh_qs;
+ end
+
+ addr_hit[40]: begin
+ reg_rdata_next[31:0] = classc_timeout_cyc_qs;
+ end
+
+ addr_hit[41]: begin
+ reg_rdata_next[31:0] = classc_phase0_cyc_qs;
+ end
+
+ addr_hit[42]: begin
+ reg_rdata_next[31:0] = classc_phase1_cyc_qs;
+ end
+
+ addr_hit[43]: begin
+ reg_rdata_next[31:0] = classc_phase2_cyc_qs;
+ end
+
+ addr_hit[44]: begin
+ reg_rdata_next[31:0] = classc_phase3_cyc_qs;
+ end
+
+ addr_hit[45]: begin
+ reg_rdata_next[31:0] = classc_esc_cnt_qs;
+ end
+
+ addr_hit[46]: begin
+ reg_rdata_next[2:0] = classc_state_qs;
+ end
+
+ addr_hit[47]: begin
+ reg_rdata_next[0] = classd_ctrl_en_qs;
+ reg_rdata_next[1] = classd_ctrl_lock_qs;
+ reg_rdata_next[2] = classd_ctrl_en_e0_qs;
+ reg_rdata_next[3] = classd_ctrl_en_e1_qs;
+ reg_rdata_next[4] = classd_ctrl_en_e2_qs;
+ reg_rdata_next[5] = classd_ctrl_en_e3_qs;
+ reg_rdata_next[7:6] = classd_ctrl_map_e0_qs;
+ reg_rdata_next[9:8] = classd_ctrl_map_e1_qs;
+ reg_rdata_next[11:10] = classd_ctrl_map_e2_qs;
+ reg_rdata_next[13:12] = classd_ctrl_map_e3_qs;
+ end
+
+ addr_hit[48]: begin
+ reg_rdata_next[0] = classd_clren_qs;
+ end
+
+ addr_hit[49]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ addr_hit[50]: begin
+ reg_rdata_next[15:0] = classd_accum_cnt_qs;
+ end
+
+ addr_hit[51]: begin
+ reg_rdata_next[15:0] = classd_accum_thresh_qs;
+ end
+
+ addr_hit[52]: begin
+ reg_rdata_next[31:0] = classd_timeout_cyc_qs;
+ end
+
+ addr_hit[53]: begin
+ reg_rdata_next[31:0] = classd_phase0_cyc_qs;
+ end
+
+ addr_hit[54]: begin
+ reg_rdata_next[31:0] = classd_phase1_cyc_qs;
+ end
+
+ addr_hit[55]: begin
+ reg_rdata_next[31:0] = classd_phase2_cyc_qs;
+ end
+
+ addr_hit[56]: begin
+ reg_rdata_next[31:0] = classd_phase3_cyc_qs;
+ end
+
+ addr_hit[57]: begin
+ reg_rdata_next[31:0] = classd_esc_cnt_qs;
+ end
+
+ addr_hit[58]: begin
+ reg_rdata_next[2:0] = classd_state_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ `ASSERT(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
+
+endmodule
diff --git a/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv b/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv
new file mode 100644
index 0000000..d99a1af
--- /dev/null
+++ b/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv
@@ -0,0 +1,294 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Breakout / remapping wrapper for register file. Generated from template.
+
+module alert_handler_reg_wrap (
+ input clk_i,
+ input rst_ni,
+ // Bus Interface (device)
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // interrupt
+ output logic [alert_pkg::N_CLASSES-1:0] irq_o,
+ // hw2reg
+ input alert_pkg::hw2reg_wrap_t hw2reg_wrap,
+ // reg2hw
+ output alert_pkg::reg2hw_wrap_t reg2hw_wrap
+);
+
+ //////////////////////////////////////////////////////
+ // reg instance
+ //////////////////////////////////////////////////////
+
+ logic [alert_pkg::N_CLASSES-1:0] class_autolock_en;
+ alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw;
+ alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg;
+
+ alert_handler_reg_top i_reg (
+ .clk_i,
+ .rst_ni,
+ .tl_i,
+ .tl_o,
+ .reg2hw,
+ .hw2reg
+ );
+
+ //////////////////////////////////////////////////////
+ // interrupts
+ //////////////////////////////////////////////////////
+
+ prim_intr_hw #(
+ .Width(1)
+ ) i_irq_classa (
+ .event_intr_i ( hw2reg_wrap.class_trig[0] & reg2hw_wrap.class_en[0] ),
+ .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classa.q ),
+ .reg2hw_intr_test_q_i ( reg2hw.intr_test.classa.q ),
+ .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classa.qe ),
+ .reg2hw_intr_state_q_i ( reg2hw.intr_state.classa.q ),
+ .hw2reg_intr_state_de_o ( hw2reg.intr_state.classa.de ),
+ .hw2reg_intr_state_d_o ( hw2reg.intr_state.classa.d ),
+ .intr_o ( irq_o[0] )
+ );
+
+ prim_intr_hw #(
+ .Width(1)
+ ) i_irq_classb (
+ .event_intr_i ( hw2reg_wrap.class_trig[1] & reg2hw_wrap.class_en[1] ),
+ .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classb.q ),
+ .reg2hw_intr_test_q_i ( reg2hw.intr_test.classb.q ),
+ .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classb.qe ),
+ .reg2hw_intr_state_q_i ( reg2hw.intr_state.classb.q ),
+ .hw2reg_intr_state_de_o ( hw2reg.intr_state.classb.de ),
+ .hw2reg_intr_state_d_o ( hw2reg.intr_state.classb.d ),
+ .intr_o ( irq_o[1] )
+ );
+
+ prim_intr_hw #(
+ .Width(1)
+ ) i_irq_classc (
+ .event_intr_i ( hw2reg_wrap.class_trig[2] & reg2hw_wrap.class_en[2] ),
+ .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classc.q ),
+ .reg2hw_intr_test_q_i ( reg2hw.intr_test.classc.q ),
+ .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classc.qe ),
+ .reg2hw_intr_state_q_i ( reg2hw.intr_state.classc.q ),
+ .hw2reg_intr_state_de_o ( hw2reg.intr_state.classc.de ),
+ .hw2reg_intr_state_d_o ( hw2reg.intr_state.classc.d ),
+ .intr_o ( irq_o[2] )
+ );
+
+ prim_intr_hw #(
+ .Width(1)
+ ) i_irq_classd (
+ .event_intr_i ( hw2reg_wrap.class_trig[3] & reg2hw_wrap.class_en[3] ),
+ .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classd.q ),
+ .reg2hw_intr_test_q_i ( reg2hw.intr_test.classd.q ),
+ .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classd.qe ),
+ .reg2hw_intr_state_q_i ( reg2hw.intr_state.classd.q ),
+ .hw2reg_intr_state_de_o ( hw2reg.intr_state.classd.de ),
+ .hw2reg_intr_state_d_o ( hw2reg.intr_state.classd.d ),
+ .intr_o ( irq_o[3] )
+ );
+
+ //////////////////////////////////////////////////////
+ // hw2reg mappings
+ //////////////////////////////////////////////////////
+
+ //////////////////////////////////////////////////////////////////////////////
+ // if an alert is enabled and it fires,
+ // we have to set the corresponding cause bit
+
+ assign { hw2reg.cause_word.a3.d,
+ hw2reg.cause_word.a2.d,
+ hw2reg.cause_word.a1.d,
+ hw2reg.cause_word.a0.d
+ } = '1;
+
+
+ assign { hw2reg.cause_word.a3.de,
+ hw2reg.cause_word.a2.de,
+ hw2reg.cause_word.a1.de,
+ hw2reg.cause_word.a0.de
+ } = hw2reg_wrap.alert_cause;
+ //----------------------------------------------------------------------------
+
+ // if a local alert is enabled and it fires,
+ // we have to set the corresponding cause bit
+ assign { hw2reg.cause_local.la3.d,
+ hw2reg.cause_local.la2.d,
+ hw2reg.cause_local.la1.d,
+ hw2reg.cause_local.la0.d } = '1;
+
+ assign { hw2reg.cause_local.la3.de,
+ hw2reg.cause_local.la2.de,
+ hw2reg.cause_local.la1.de,
+ hw2reg.cause_local.la0.de } = hw2reg_wrap.loc_alert_cause;
+
+ // autolock can clear these regs automatically upon entering escalation
+ // note: the class must be activated for this to occur
+ assign { hw2reg.classd_clren.d,
+ hw2reg.classc_clren.d,
+ hw2reg.classb_clren.d,
+ hw2reg.classa_clren.d } = '0;
+
+ assign { hw2reg.classd_clren.de,
+ hw2reg.classc_clren.de,
+ hw2reg.classb_clren.de,
+ hw2reg.classa_clren.de } = hw2reg_wrap.class_esc_trig &
+ class_autolock_en &
+ reg2hw_wrap.class_en;
+
+ // current accumulator counts
+ assign { hw2reg.classd_accum_cnt.d,
+ hw2reg.classc_accum_cnt.d,
+ hw2reg.classb_accum_cnt.d,
+ hw2reg.classa_accum_cnt.d } = hw2reg_wrap.class_accum_cnt;
+
+ // current accumulator counts
+ assign { hw2reg.classd_esc_cnt.d,
+ hw2reg.classc_esc_cnt.d,
+ hw2reg.classb_esc_cnt.d,
+ hw2reg.classa_esc_cnt.d } = hw2reg_wrap.class_esc_cnt;
+
+ // current accumulator counts
+ assign { hw2reg.classd_state.d,
+ hw2reg.classc_state.d,
+ hw2reg.classb_state.d,
+ hw2reg.classa_state.d } = hw2reg_wrap.class_esc_state;
+
+ //////////////////////////////////////////////////////
+ // reg2hw mappings
+ //////////////////////////////////////////////////////
+
+ // config register lock
+ assign reg2hw_wrap.config_locked = ~reg2hw.regen.q;
+
+ //////////////////////////////////////////////////////////////////////////////
+ // alert enable
+
+ assign reg2hw_wrap.alert_en = { reg2hw.alert_en.en_a3.q,
+ reg2hw.alert_en.en_a2.q,
+ reg2hw.alert_en.en_a1.q,
+ reg2hw.alert_en.en_a0.q };
+ //----------------------------------------------------------------------------
+
+ //////////////////////////////////////////////////////////////////////////////
+ // classification mapping
+
+ assign reg2hw_wrap.alert_class = { reg2hw.alert_class.class_a3.q,
+ reg2hw.alert_class.class_a2.q,
+ reg2hw.alert_class.class_a1.q,
+ reg2hw.alert_class.class_a0.q };
+ //----------------------------------------------------------------------------
+
+ // local alert enable and class assignments
+ assign reg2hw_wrap.loc_alert_en = { reg2hw.loc_alert_en.en_la3.q,
+ reg2hw.loc_alert_en.en_la2.q,
+ reg2hw.loc_alert_en.en_la1.q,
+ reg2hw.loc_alert_en.en_la0.q };
+
+ assign reg2hw_wrap.loc_alert_class = { reg2hw.loc_alert_class.class_la3.q[1:0],
+ reg2hw.loc_alert_class.class_la2.q[1:0],
+ reg2hw.loc_alert_class.class_la1.q[1:0],
+ reg2hw.loc_alert_class.class_la0.q[1:0]};
+ // ping timeout in cycles
+ assign reg2hw_wrap.ping_timeout_cyc = reg2hw.ping_timeout_cyc.q;
+
+ // class enable
+ assign reg2hw_wrap.class_en = { reg2hw.classd_ctrl.en,
+ reg2hw.classc_ctrl.en,
+ reg2hw.classb_ctrl.en,
+ reg2hw.classa_ctrl.en };
+
+ // autolock enable
+ assign class_autolock_en = { reg2hw.classd_ctrl.lock,
+ reg2hw.classc_ctrl.lock,
+ reg2hw.classb_ctrl.lock,
+ reg2hw.classa_ctrl.lock };
+
+ // escalation signal enable
+ assign reg2hw_wrap.class_esc_en = { reg2hw.classd_ctrl.en_e3,
+ reg2hw.classd_ctrl.en_e2,
+ reg2hw.classd_ctrl.en_e1,
+ reg2hw.classd_ctrl.en_e0,
+ //
+ reg2hw.classc_ctrl.en_e3,
+ reg2hw.classc_ctrl.en_e2,
+ reg2hw.classc_ctrl.en_e1,
+ reg2hw.classc_ctrl.en_e0,
+ //
+ reg2hw.classb_ctrl.en_e3,
+ reg2hw.classb_ctrl.en_e2,
+ reg2hw.classb_ctrl.en_e1,
+ reg2hw.classb_ctrl.en_e0,
+ //
+ reg2hw.classa_ctrl.en_e3,
+ reg2hw.classa_ctrl.en_e2,
+ reg2hw.classa_ctrl.en_e1,
+ reg2hw.classa_ctrl.en_e0 };
+
+
+ // escalation phase to escalation signal mapping
+ assign reg2hw_wrap.class_esc_map = { reg2hw.classd_ctrl.map_e3,
+ reg2hw.classd_ctrl.map_e2,
+ reg2hw.classd_ctrl.map_e1,
+ reg2hw.classd_ctrl.map_e0,
+ //
+ reg2hw.classc_ctrl.map_e3,
+ reg2hw.classc_ctrl.map_e2,
+ reg2hw.classc_ctrl.map_e1,
+ reg2hw.classc_ctrl.map_e0,
+ //
+ reg2hw.classb_ctrl.map_e3,
+ reg2hw.classb_ctrl.map_e2,
+ reg2hw.classb_ctrl.map_e1,
+ reg2hw.classb_ctrl.map_e0,
+ //
+ reg2hw.classa_ctrl.map_e3,
+ reg2hw.classa_ctrl.map_e2,
+ reg2hw.classa_ctrl.map_e1,
+ reg2hw.classa_ctrl.map_e0 };
+
+ // TODO: check whether this is correctly locked inside the regfile
+ // writing 1b1 to a class clr register clears the accumulator and
+ // escalation state if autolock is not asserted
+ assign reg2hw_wrap.class_clr = { reg2hw.classd_clr.q & reg2hw.classd_clr.qe,
+ reg2hw.classc_clr.q & reg2hw.classc_clr.qe,
+ reg2hw.classb_clr.q & reg2hw.classb_clr.qe,
+ reg2hw.classa_clr.q & reg2hw.classa_clr.qe };
+
+ // accumulator thresholds
+ assign reg2hw_wrap.class_accum_thresh = { reg2hw.classd_accum_thresh.q,
+ reg2hw.classc_accum_thresh.q,
+ reg2hw.classb_accum_thresh.q,
+ reg2hw.classa_accum_thresh.q };
+
+ // interrupt timeout lengths
+ assign reg2hw_wrap.class_timeout_cyc = { reg2hw.classd_timeout_cyc.q,
+ reg2hw.classc_timeout_cyc.q,
+ reg2hw.classb_timeout_cyc.q,
+ reg2hw.classa_timeout_cyc.q };
+ // escalation phase lengths
+ assign reg2hw_wrap.class_phase_cyc = { reg2hw.classd_phase3_cyc.q,
+ reg2hw.classd_phase2_cyc.q,
+ reg2hw.classd_phase1_cyc.q,
+ reg2hw.classd_phase0_cyc.q,
+ //
+ reg2hw.classc_phase3_cyc.q,
+ reg2hw.classc_phase2_cyc.q,
+ reg2hw.classc_phase1_cyc.q,
+ reg2hw.classc_phase0_cyc.q,
+ //
+ reg2hw.classb_phase3_cyc.q,
+ reg2hw.classb_phase2_cyc.q,
+ reg2hw.classb_phase1_cyc.q,
+ reg2hw.classb_phase0_cyc.q,
+ //
+ reg2hw.classa_phase3_cyc.q,
+ reg2hw.classa_phase2_cyc.q,
+ reg2hw.classa_phase1_cyc.q,
+ reg2hw.classa_phase0_cyc.q};
+
+endmodule : alert_handler_reg_wrap
+
diff --git a/hw/ip/alert_handler/rtl/alert_pkg.sv b/hw/ip/alert_handler/rtl/alert_pkg.sv
new file mode 100644
index 0000000..226bbcc
--- /dev/null
+++ b/hw/ip/alert_handler/rtl/alert_pkg.sv
@@ -0,0 +1,64 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package alert_pkg;
+
+ // these localparams are generated based on the system top-level configuration
+ localparam int unsigned NAlerts = 4; // maximum 252
+ localparam int unsigned EscCntDw = 32; // maximum 32
+ localparam int unsigned AccuCntDw = 16; // maximum 32
+ localparam logic [31:0] LfsrSeed = 2147483647; // seed for the ping timer (must be nonzero!)
+ localparam bit [NAlerts-1:0] AsyncOn = '0; // TODO: make parametric via generator
+
+ // common constants, do not change
+ localparam int unsigned N_CLASSES = 4;
+ localparam int unsigned N_ESC_SEV = 4;
+ localparam int unsigned N_PHASES = 4;
+ localparam int unsigned N_LOC_ALERT = 4;
+
+ localparam int unsigned PING_CNT_DW = 24;
+ localparam int unsigned PHASE_DW = $clog2(N_PHASES);
+ localparam int unsigned CLASS_DW = $clog2(N_CLASSES);
+
+ // do not change the phase encoding
+ typedef enum logic [2:0] {Idle = 3'b000, Timeout = 3'b001, Terminal = 3'b011,
+ Phase0 = 3'b100, Phase1 = 3'b101, Phase2 = 3'b110,
+ Phase3 = 3'b111} cstate_e;
+
+ // breakout wrapper structs
+ typedef struct packed {
+ // alerts
+ logic [NAlerts-1:0] alert_cause; // alert cause bits
+ logic [N_LOC_ALERT-1:0] loc_alert_cause; // local alert cause bits
+ // class state
+ logic [N_CLASSES-1:0] class_trig; // class has been triggered
+ logic [N_CLASSES-1:0] class_esc_trig; // escalation has triggered
+ logic [N_CLASSES-1:0][AccuCntDw-1:0] class_accum_cnt; // current accumulator value
+ logic [N_CLASSES-1:0][EscCntDw-1:0] class_esc_cnt; // current escalation counter value
+ cstate_e [N_CLASSES-1:0] class_esc_state; // current escalation protocol state
+ } hw2reg_wrap_t;
+
+ typedef struct packed {
+ // ping config
+ logic config_locked; // locked -> ping enabled
+ logic [PING_CNT_DW-1:0] ping_timeout_cyc; // ping timeout config
+ // alert config
+ logic [N_LOC_ALERT-1:0] loc_alert_en; // alert enable
+ logic [N_LOC_ALERT-1:0][CLASS_DW-1:0] loc_alert_class; // alert class config
+ logic [NAlerts-1:0] alert_en; // alert enable
+ logic [NAlerts-1:0][CLASS_DW-1:0] alert_class; // alert class config
+ // class config
+ logic [N_CLASSES-1:0] class_en; // enables esc mechanisms
+ logic [N_CLASSES-1:0] class_clr; // clears esc/accu
+ logic [N_CLASSES-1:0][AccuCntDw-1:0] class_accum_thresh; // accum esc threshold
+ logic [N_CLASSES-1:0][EscCntDw-1:0] class_timeout_cyc; // interrupt timeout
+ logic [N_CLASSES-1:0][N_PHASES-1:0][EscCntDw-1:0] class_phase_cyc; // length of phases 0..3
+ logic [N_CLASSES-1:0][N_ESC_SEV-1:0] class_esc_en; // esc signal enables
+ logic [N_CLASSES-1:0][N_ESC_SEV-1:0][PHASE_DW-1:0] class_esc_map; // esc signal/phase map
+ } reg2hw_wrap_t;
+
+endpackage : alert_pkg
+
+
diff --git a/hw/ip/alert_handler/sw/alert_handler_regs.h b/hw/ip/alert_handler/sw/alert_handler_regs.h
new file mode 100644
index 0000000..b0e76a6
--- /dev/null
+++ b/hw/ip/alert_handler/sw/alert_handler_regs.h
@@ -0,0 +1,362 @@
+// Generated register defines for ALERT_HANDLER
+
+// Copyright information found in source file:
+// Copyright lowRISC contributors.
+
+// Licensing information found in source file:
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _ALERT_HANDLER_REG_DEFS_
+#define _ALERT_HANDLER_REG_DEFS_
+
+// Interrupt State Register
+#define ALERT_HANDLER_INTR_STATE(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x0)
+#define ALERT_HANDLER_INTR_STATE_CLASSA 0
+#define ALERT_HANDLER_INTR_STATE_CLASSB 1
+#define ALERT_HANDLER_INTR_STATE_CLASSC 2
+#define ALERT_HANDLER_INTR_STATE_CLASSD 3
+
+// Interrupt Enable Register
+#define ALERT_HANDLER_INTR_ENABLE(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x4)
+#define ALERT_HANDLER_INTR_ENABLE_CLASSA 0
+#define ALERT_HANDLER_INTR_ENABLE_CLASSB 1
+#define ALERT_HANDLER_INTR_ENABLE_CLASSC 2
+#define ALERT_HANDLER_INTR_ENABLE_CLASSD 3
+
+// Interrupt Test Register
+#define ALERT_HANDLER_INTR_TEST(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x8)
+#define ALERT_HANDLER_INTR_TEST_CLASSA 0
+#define ALERT_HANDLER_INTR_TEST_CLASSB 1
+#define ALERT_HANDLER_INTR_TEST_CLASSC 2
+#define ALERT_HANDLER_INTR_TEST_CLASSD 3
+
+// Register write enable for all control registers.
+#define ALERT_HANDLER_REGEN(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xc)
+#define ALERT_HANDLER_REGEN 0
+
+// Ping timeout cycle count.
+#define ALERT_HANDLER_PING_TIMEOUT_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x10)
+#define ALERT_HANDLER_PING_TIMEOUT_CYC_MASK 0xffffff
+#define ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET 0
+
+// Enable register for alerts.
+#define ALERT_HANDLER_ALERT_EN(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x14)
+#define ALERT_HANDLER_ALERT_EN_EN_A0 0
+#define ALERT_HANDLER_ALERT_EN_EN_A1 1
+#define ALERT_HANDLER_ALERT_EN_EN_A2 2
+#define ALERT_HANDLER_ALERT_EN_EN_A3 3
+
+// Class assignment of alerts.
+#define ALERT_HANDLER_ALERT_CLASS(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x18)
+#define ALERT_HANDLER_ALERT_CLASS_CLASS_A0_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_CLASS_A0_OFFSET 0
+#define ALERT_HANDLER_ALERT_CLASS_CLASS_A0_CLASSA 0
+#define ALERT_HANDLER_ALERT_CLASS_CLASS_A0_CLASSB 1
+#define ALERT_HANDLER_ALERT_CLASS_CLASS_A0_CLASSC 2
+#define ALERT_HANDLER_ALERT_CLASS_CLASS_A0_CLASSD 3
+#define ALERT_HANDLER_ALERT_CLASS_CLASS_A1_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_CLASS_A1_OFFSET 2
+#define ALERT_HANDLER_ALERT_CLASS_CLASS_A2_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_CLASS_A2_OFFSET 4
+#define ALERT_HANDLER_ALERT_CLASS_CLASS_A3_MASK 0x3
+#define ALERT_HANDLER_ALERT_CLASS_CLASS_A3_OFFSET 6
+
+// Alert Cause Register
+#define ALERT_HANDLER_ALERT_CAUSE(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x1c)
+#define ALERT_HANDLER_ALERT_CAUSE_A0 0
+#define ALERT_HANDLER_ALERT_CAUSE_A1 1
+#define ALERT_HANDLER_ALERT_CAUSE_A2 2
+#define ALERT_HANDLER_ALERT_CAUSE_A3 3
+
+// Enable register for the aggregated local alerts "alert
+#define ALERT_HANDLER_LOC_ALERT_EN(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x20)
+#define ALERT_HANDLER_LOC_ALERT_EN_EN_LA0 0
+#define ALERT_HANDLER_LOC_ALERT_EN_EN_LA1 1
+#define ALERT_HANDLER_LOC_ALERT_EN_EN_LA2 2
+#define ALERT_HANDLER_LOC_ALERT_EN_EN_LA3 3
+
+// Class assignment of local alerts. "alert
+#define ALERT_HANDLER_LOC_ALERT_CLASS(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x24)
+#define ALERT_HANDLER_LOC_ALERT_CLASS_CLASS_LA0_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_CLASS_LA0_OFFSET 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_CLASS_LA0_CLASSA 0
+#define ALERT_HANDLER_LOC_ALERT_CLASS_CLASS_LA0_CLASSB 1
+#define ALERT_HANDLER_LOC_ALERT_CLASS_CLASS_LA0_CLASSC 2
+#define ALERT_HANDLER_LOC_ALERT_CLASS_CLASS_LA0_CLASSD 3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_CLASS_LA1_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_CLASS_LA1_OFFSET 2
+#define ALERT_HANDLER_LOC_ALERT_CLASS_CLASS_LA2_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_CLASS_LA2_OFFSET 4
+#define ALERT_HANDLER_LOC_ALERT_CLASS_CLASS_LA3_MASK 0x3
+#define ALERT_HANDLER_LOC_ALERT_CLASS_CLASS_LA3_OFFSET 6
+
+// Alert Cause Register for Local Alerts
+#define ALERT_HANDLER_LOC_ALERT_CAUSE(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x28)
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_LA0 0
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_LA1 1
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_LA2 2
+#define ALERT_HANDLER_LOC_ALERT_CAUSE_LA3 3
+
+// Escalation control register for alert Class A. Can not be modified if !!REGEN is false.
+#define ALERT_HANDLER_CLASSA_CTRL(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x2c)
+#define ALERT_HANDLER_CLASSA_CTRL_EN 0
+#define ALERT_HANDLER_CLASSA_CTRL_LOCK 1
+#define ALERT_HANDLER_CLASSA_CTRL_EN_E0 2
+#define ALERT_HANDLER_CLASSA_CTRL_EN_E1 3
+#define ALERT_HANDLER_CLASSA_CTRL_EN_E2 4
+#define ALERT_HANDLER_CLASSA_CTRL_EN_E3 5
+#define ALERT_HANDLER_CLASSA_CTRL_MAP_E0_MASK 0x3
+#define ALERT_HANDLER_CLASSA_CTRL_MAP_E0_OFFSET 6
+#define ALERT_HANDLER_CLASSA_CTRL_MAP_E1_MASK 0x3
+#define ALERT_HANDLER_CLASSA_CTRL_MAP_E1_OFFSET 8
+#define ALERT_HANDLER_CLASSA_CTRL_MAP_E2_MASK 0x3
+#define ALERT_HANDLER_CLASSA_CTRL_MAP_E2_OFFSET 10
+#define ALERT_HANDLER_CLASSA_CTRL_MAP_E3_MASK 0x3
+#define ALERT_HANDLER_CLASSA_CTRL_MAP_E3_OFFSET 12
+
+// Clear enable for escalation protocol of class A alerts.
+#define ALERT_HANDLER_CLASSA_CLREN(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x30)
+#define ALERT_HANDLER_CLASSA_CLREN 0
+
+// Clear for esclation protocol of class A.
+#define ALERT_HANDLER_CLASSA_CLR(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x34)
+#define ALERT_HANDLER_CLASSA_CLR 0
+
+// Current accumulation value for alert Class A. Software can clear this register
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x38)
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT_MASK 0xffff
+#define ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET 0
+
+// Accumulation threshold value for alert Class A.
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x3c)
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_MASK 0xffff
+#define ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET 0
+
+// Interrupt timeout in cycles.
+#define ALERT_HANDLER_CLASSA_TIMEOUT_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x40)
+
+// Duration of escalation phase 0 for class A.
+#define ALERT_HANDLER_CLASSA_PHASE0_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x44)
+
+// Duration of escalation phase 1 for class A.
+#define ALERT_HANDLER_CLASSA_PHASE1_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x48)
+
+// Duration of escalation phase 2 for class A.
+#define ALERT_HANDLER_CLASSA_PHASE2_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x4c)
+
+// Duration of escalation phase 3 for class A.
+#define ALERT_HANDLER_CLASSA_PHASE3_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x50)
+
+// Escalation counter in cycles for class A.
+#define ALERT_HANDLER_CLASSA_ESC_CNT(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x54)
+
+// Current escalation state of Class A. See also !!CLASSA_ESC_CNT.
+#define ALERT_HANDLER_CLASSA_STATE(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x58)
+#define ALERT_HANDLER_CLASSA_STATE_MASK 0x7
+#define ALERT_HANDLER_CLASSA_STATE_OFFSET 0
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_IDLE 0b000
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_TIMEOUT 0b001
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_TERMINAL 0b011
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_PHASE0 0b100
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_PHASE1 0b101
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_PHASE2 0b110
+#define ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_PHASE3 0b111
+
+// Escalation control register for alert Class B. Can not be modified if !!REGEN is false.
+#define ALERT_HANDLER_CLASSB_CTRL(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x5c)
+#define ALERT_HANDLER_CLASSB_CTRL_EN 0
+#define ALERT_HANDLER_CLASSB_CTRL_LOCK 1
+#define ALERT_HANDLER_CLASSB_CTRL_EN_E0 2
+#define ALERT_HANDLER_CLASSB_CTRL_EN_E1 3
+#define ALERT_HANDLER_CLASSB_CTRL_EN_E2 4
+#define ALERT_HANDLER_CLASSB_CTRL_EN_E3 5
+#define ALERT_HANDLER_CLASSB_CTRL_MAP_E0_MASK 0x3
+#define ALERT_HANDLER_CLASSB_CTRL_MAP_E0_OFFSET 6
+#define ALERT_HANDLER_CLASSB_CTRL_MAP_E1_MASK 0x3
+#define ALERT_HANDLER_CLASSB_CTRL_MAP_E1_OFFSET 8
+#define ALERT_HANDLER_CLASSB_CTRL_MAP_E2_MASK 0x3
+#define ALERT_HANDLER_CLASSB_CTRL_MAP_E2_OFFSET 10
+#define ALERT_HANDLER_CLASSB_CTRL_MAP_E3_MASK 0x3
+#define ALERT_HANDLER_CLASSB_CTRL_MAP_E3_OFFSET 12
+
+// Clear enable for escalation protocol of class B alerts.
+#define ALERT_HANDLER_CLASSB_CLREN(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x60)
+#define ALERT_HANDLER_CLASSB_CLREN 0
+
+// Clear for esclation protocol of class B.
+#define ALERT_HANDLER_CLASSB_CLR(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x64)
+#define ALERT_HANDLER_CLASSB_CLR 0
+
+// Current accumulation value for alert Class B. Software can clear this register
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x68)
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT_MASK 0xffff
+#define ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET 0
+
+// Accumulation threshold value for alert Class B.
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x6c)
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_MASK 0xffff
+#define ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET 0
+
+// Interrupt timeout in cycles.
+#define ALERT_HANDLER_CLASSB_TIMEOUT_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x70)
+
+// Duration of escalation phase 0 for class B.
+#define ALERT_HANDLER_CLASSB_PHASE0_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x74)
+
+// Duration of escalation phase 1 for class B.
+#define ALERT_HANDLER_CLASSB_PHASE1_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x78)
+
+// Duration of escalation phase 2 for class B.
+#define ALERT_HANDLER_CLASSB_PHASE2_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x7c)
+
+// Duration of escalation phase 3 for class B.
+#define ALERT_HANDLER_CLASSB_PHASE3_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x80)
+
+// Escalation counter in cycles for class B.
+#define ALERT_HANDLER_CLASSB_ESC_CNT(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x84)
+
+// Current escalation state of Class B. See also !!CLASSB_ESC_CNT.
+#define ALERT_HANDLER_CLASSB_STATE(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x88)
+#define ALERT_HANDLER_CLASSB_STATE_MASK 0x7
+#define ALERT_HANDLER_CLASSB_STATE_OFFSET 0
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_IDLE 0b000
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_TIMEOUT 0b001
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_TERMINAL 0b011
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_PHASE0 0b100
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_PHASE1 0b101
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_PHASE2 0b110
+#define ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_PHASE3 0b111
+
+// Escalation control register for alert Class C. Can not be modified if !!REGEN is false.
+#define ALERT_HANDLER_CLASSC_CTRL(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x8c)
+#define ALERT_HANDLER_CLASSC_CTRL_EN 0
+#define ALERT_HANDLER_CLASSC_CTRL_LOCK 1
+#define ALERT_HANDLER_CLASSC_CTRL_EN_E0 2
+#define ALERT_HANDLER_CLASSC_CTRL_EN_E1 3
+#define ALERT_HANDLER_CLASSC_CTRL_EN_E2 4
+#define ALERT_HANDLER_CLASSC_CTRL_EN_E3 5
+#define ALERT_HANDLER_CLASSC_CTRL_MAP_E0_MASK 0x3
+#define ALERT_HANDLER_CLASSC_CTRL_MAP_E0_OFFSET 6
+#define ALERT_HANDLER_CLASSC_CTRL_MAP_E1_MASK 0x3
+#define ALERT_HANDLER_CLASSC_CTRL_MAP_E1_OFFSET 8
+#define ALERT_HANDLER_CLASSC_CTRL_MAP_E2_MASK 0x3
+#define ALERT_HANDLER_CLASSC_CTRL_MAP_E2_OFFSET 10
+#define ALERT_HANDLER_CLASSC_CTRL_MAP_E3_MASK 0x3
+#define ALERT_HANDLER_CLASSC_CTRL_MAP_E3_OFFSET 12
+
+// Clear enable for escalation protocol of class C alerts.
+#define ALERT_HANDLER_CLASSC_CLREN(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x90)
+#define ALERT_HANDLER_CLASSC_CLREN 0
+
+// Clear for esclation protocol of class C.
+#define ALERT_HANDLER_CLASSC_CLR(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x94)
+#define ALERT_HANDLER_CLASSC_CLR 0
+
+// Current accumulation value for alert Class C. Software can clear this register
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x98)
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT_MASK 0xffff
+#define ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET 0
+
+// Accumulation threshold value for alert Class C.
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH(id) (ALERT_HANDLER##id##_BASE_ADDR + 0x9c)
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_MASK 0xffff
+#define ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET 0
+
+// Interrupt timeout in cycles.
+#define ALERT_HANDLER_CLASSC_TIMEOUT_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xa0)
+
+// Duration of escalation phase 0 for class C.
+#define ALERT_HANDLER_CLASSC_PHASE0_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xa4)
+
+// Duration of escalation phase 1 for class C.
+#define ALERT_HANDLER_CLASSC_PHASE1_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xa8)
+
+// Duration of escalation phase 2 for class C.
+#define ALERT_HANDLER_CLASSC_PHASE2_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xac)
+
+// Duration of escalation phase 3 for class C.
+#define ALERT_HANDLER_CLASSC_PHASE3_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xb0)
+
+// Escalation counter in cycles for class C.
+#define ALERT_HANDLER_CLASSC_ESC_CNT(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xb4)
+
+// Current escalation state of Class C. See also !!CLASSC_ESC_CNT.
+#define ALERT_HANDLER_CLASSC_STATE(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xb8)
+#define ALERT_HANDLER_CLASSC_STATE_MASK 0x7
+#define ALERT_HANDLER_CLASSC_STATE_OFFSET 0
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_IDLE 0b000
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_TIMEOUT 0b001
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_TERMINAL 0b011
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_PHASE0 0b100
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_PHASE1 0b101
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_PHASE2 0b110
+#define ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_PHASE3 0b111
+
+// Escalation control register for alert Class D. Can not be modified if !!REGEN is false.
+#define ALERT_HANDLER_CLASSD_CTRL(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xbc)
+#define ALERT_HANDLER_CLASSD_CTRL_EN 0
+#define ALERT_HANDLER_CLASSD_CTRL_LOCK 1
+#define ALERT_HANDLER_CLASSD_CTRL_EN_E0 2
+#define ALERT_HANDLER_CLASSD_CTRL_EN_E1 3
+#define ALERT_HANDLER_CLASSD_CTRL_EN_E2 4
+#define ALERT_HANDLER_CLASSD_CTRL_EN_E3 5
+#define ALERT_HANDLER_CLASSD_CTRL_MAP_E0_MASK 0x3
+#define ALERT_HANDLER_CLASSD_CTRL_MAP_E0_OFFSET 6
+#define ALERT_HANDLER_CLASSD_CTRL_MAP_E1_MASK 0x3
+#define ALERT_HANDLER_CLASSD_CTRL_MAP_E1_OFFSET 8
+#define ALERT_HANDLER_CLASSD_CTRL_MAP_E2_MASK 0x3
+#define ALERT_HANDLER_CLASSD_CTRL_MAP_E2_OFFSET 10
+#define ALERT_HANDLER_CLASSD_CTRL_MAP_E3_MASK 0x3
+#define ALERT_HANDLER_CLASSD_CTRL_MAP_E3_OFFSET 12
+
+// Clear enable for escalation protocol of class D alerts.
+#define ALERT_HANDLER_CLASSD_CLREN(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xc0)
+#define ALERT_HANDLER_CLASSD_CLREN 0
+
+// Clear for esclation protocol of class D.
+#define ALERT_HANDLER_CLASSD_CLR(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xc4)
+#define ALERT_HANDLER_CLASSD_CLR 0
+
+// Current accumulation value for alert Class D. Software can clear this register
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xc8)
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT_MASK 0xffff
+#define ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET 0
+
+// Accumulation threshold value for alert Class D.
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xcc)
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_MASK 0xffff
+#define ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET 0
+
+// Interrupt timeout in cycles.
+#define ALERT_HANDLER_CLASSD_TIMEOUT_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xd0)
+
+// Duration of escalation phase 0 for class D.
+#define ALERT_HANDLER_CLASSD_PHASE0_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xd4)
+
+// Duration of escalation phase 1 for class D.
+#define ALERT_HANDLER_CLASSD_PHASE1_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xd8)
+
+// Duration of escalation phase 2 for class D.
+#define ALERT_HANDLER_CLASSD_PHASE2_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xdc)
+
+// Duration of escalation phase 3 for class D.
+#define ALERT_HANDLER_CLASSD_PHASE3_CYC(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xe0)
+
+// Escalation counter in cycles for class D.
+#define ALERT_HANDLER_CLASSD_ESC_CNT(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xe4)
+
+// Current escalation state of Class D. See also !!CLASSD_ESC_CNT.
+#define ALERT_HANDLER_CLASSD_STATE(id) (ALERT_HANDLER##id##_BASE_ADDR + 0xe8)
+#define ALERT_HANDLER_CLASSD_STATE_MASK 0x7
+#define ALERT_HANDLER_CLASSD_STATE_OFFSET 0
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_IDLE 0b000
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_TIMEOUT 0b001
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_TERMINAL 0b011
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_PHASE0 0b100
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_PHASE1 0b101
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_PHASE2 0b110
+#define ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_PHASE3 0b111
+
+#endif // _ALERT_HANDLER_REG_DEFS_
+// End generated register defines for ALERT_HANDLER
