| commit | 359de277d6b93a258c8e4d51e09ba0c72123acf2 | [log] [tgz] |
|---|---|---|
| author | Philipp Wagner <phw@lowrisc.org> | Tue Nov 10 11:38:10 2020 +0000 |
| committer | Philipp Wagner <mail@philipp-wagner.com> | Tue Nov 10 14:06:20 2020 +0000 |
| tree | bdb6197a2036579762d398d4cb36610af5ba3ed0 | |
| parent | 7c66e95964adc22a32810d818994900ec6f38e00 [diff] |
[ci] Disable RISC-V compliance tests The RISC-V compliance tests are important to catch issues in the CPU and the interconnect, but take a very long time to run (30-60 min for each of the two chunks) in Verilator simulation on the Microsoft-provided Azure Runners. Furthermore, the runners we get are rather unpredictable in their performance, leading to huge variations in the test execution time. At the same time, these tests didn't flag a new issue recently which wasn't caught somewhere else. Therefore, disabling them is unlikely to reduce the quality of the testing much. We still need to find a way to re-enable these tests. Running them on the FPGA platform is likely to be a good approach, which will bring down test times massively. Having a dedicated, powerful runner could be another option if we want to continue running the tests in simulation. Fixes #4128 Signed-off-by: Philipp Wagner <phw@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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