[csrng/rtl] instantiate and generate bug fixes
Fixes rtl problems that now enable instantiate and generate to work.
Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
diff --git a/hw/ip/csrng/rtl/csrng_block_encrypt.sv b/hw/ip/csrng/rtl/csrng_block_encrypt.sv
index e79749b..221e6dc 100644
--- a/hw/ip/csrng/rtl/csrng_block_encrypt.sv
+++ b/hw/ip/csrng/rtl/csrng_block_encrypt.sv
@@ -5,7 +5,7 @@
// Description: csrng block encrypt module
//
-module csrng_block_encrypt #(
+module csrng_block_encrypt import csrng_pkg::*; #(
parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplLut,
parameter int Cmd = 3,
parameter int StateId = 4,
@@ -70,11 +70,11 @@
assign prd_clearing[0] = '0;
- assign state_init[0] = aes_pkg::aes_transpose(block_encrypt_v_i);
+ assign state_init[0] = aes_pkg::aes_transpose({<<8{block_encrypt_v_i}});
- assign key_init[0] = block_encrypt_key_i;
+ assign key_init[0] = {<<8{block_encrypt_key_i}};
assign state_out = aes_pkg::aes_transpose(state_done[0]);
- assign cipher_data_out = state_out;
+ assign cipher_data_out = {<<8{state_out}};
//--------------------------------------------
diff --git a/hw/ip/csrng/rtl/csrng_cmd_stage.sv b/hw/ip/csrng/rtl/csrng_cmd_stage.sv
index f9fa396..e182e56 100644
--- a/hw/ip/csrng/rtl/csrng_cmd_stage.sv
+++ b/hw/ip/csrng/rtl/csrng_cmd_stage.sv
@@ -48,6 +48,7 @@
localparam int GenBitsFifoWidth = 1+128;
localparam int GenBitsFifoDepth = 1;
+ localparam int GenBitsCntrWidth = 19;
// signals
// command fifo
@@ -76,6 +77,7 @@
logic cmd_gen_cnt_dec;
logic cmd_gen_1st_req;
logic cmd_gen_inc_req;
+ logic cmd_gen_cnt_last;
logic cmd_final_ack;
// flops
@@ -83,7 +85,7 @@
logic cmd_ack_sts_q, cmd_ack_sts_d;
logic [3:0] cmd_len_q, cmd_len_d;
logic cmd_gen_flag_q, cmd_gen_flag_d;
- logic [18:0] cmd_gen_cnt_q, cmd_gen_cnt_d; // max_nuber_of_bits_per_request = 2^19
+ logic [GenBitsCntrWidth-1:0] cmd_gen_cnt_q, cmd_gen_cnt_d; // max_nuber_of_bits_per_request = 2^19
logic [11:0] cmd_gen_cmd_q, cmd_gen_cmd_d;
@@ -137,10 +139,11 @@
assign sfifo_cmd_pop = cs_enable_i && cmd_fifo_pop;
assign cmd_arb_bus_o =
- cmd_gen_inc_req ? {16'b0,cmd_stage_shid_i,cmd_gen_cmd_q} :
- cmd_gen_1st_req ? {16'b0,cmd_stage_shid_i,sfifo_cmd_rdata[11:0]} : // pad,id,f,clen,cmd
- cmd_arb_mop_o ? sfifo_cmd_rdata :
- '0;
+ cmd_gen_inc_req ? {15'b0,cmd_gen_cnt_last,cmd_stage_shid_i,cmd_gen_cmd_q} :
+ // pad,glast,id,f,clen,cmd
+ cmd_gen_1st_req ? {15'b0,cmd_gen_cnt_last,cmd_stage_shid_i,sfifo_cmd_rdata[11:0]} :
+ cmd_arb_mop_o ? sfifo_cmd_rdata :
+ '0;
assign cmd_stage_rdy_o = !sfifo_cmd_full;
@@ -239,6 +242,7 @@
cmd_gen_cnt_dec= 1'b0;
cmd_gen_1st_req = 1'b0;
cmd_gen_inc_req = 1'b0;
+ cmd_gen_cnt_last = 1'b0;
cmd_final_ack = 1'b0;
cmd_arb_req_o = 1'b0;
cmd_arb_sop_o = 1'b0;
@@ -257,6 +261,9 @@
cmd_gen_1st_req = 1'b1;
cmd_arb_sop_o = 1'b1;
cmd_fifo_pop = 1'b1;
+ if (sfifo_cmd_rdata[30:12] == 20'h00001) begin
+ cmd_gen_cnt_last = 1'b1;
+ end
if (cmd_len == '0) begin
cmd_arb_eop_o = 1'b1;
state_d = GenCmdChk;
@@ -306,6 +313,10 @@
cmd_arb_eop_o = 1'b1;
cmd_gen_inc_req = 1'b1;
state_d = GenCmdChk;
+ // check for final genbits beat
+ if (cmd_gen_cnt_q == GenBitsCntrWidth'(1)) begin
+ cmd_gen_cnt_last = 1'b1;
+ end
end
end
end
diff --git a/hw/ip/csrng/rtl/csrng_core.sv b/hw/ip/csrng/rtl/csrng_core.sv
index 9a0468a..a1f8436 100644
--- a/hw/ip/csrng/rtl/csrng_core.sv
+++ b/hw/ip/csrng/rtl/csrng_core.sv
@@ -101,6 +101,7 @@
logic [Cmd-1:0] cmd_result_ccmd;
logic cmd_result_ack_rdy;
logic [StateId-1:0] cmd_result_inst_id;
+ logic cmd_result_glast;
logic cmd_result_fips;
logic [SeedLen-1:0] cmd_result_adata;
logic [KeyLen-1:0] cmd_result_key;
@@ -114,6 +115,7 @@
logic gen_result_wr_req;
logic gen_result_ack_sts;
logic gen_result_ack_rdy;
+ logic [Cmd-1:0] gen_result_ccmd;
logic [StateId-1:0] gen_result_inst_id;
logic gen_result_fips;
logic [KeyLen-1:0] gen_result_key;
@@ -183,6 +185,7 @@
logic state_db_rd_fips;
logic [2:0] acmd_hold;
logic [3:0] shid;
+ logic gen_last;
logic flag0;
// blk encrypt arbiter
@@ -320,6 +323,7 @@
// flops
logic [2:0] acmd_q, acmd_d;
logic [3:0] shid_q, shid_d;
+ logic gen_last_q, gen_last_d;
logic flag0_q, flag0_d;
logic statedb_wr_select_q, statedb_wr_select_d;
logic genbits_stage_fips_sw_q, genbits_stage_fips_sw_d;
@@ -336,6 +340,7 @@
if (!rst_ni) begin
acmd_q <= '0;
shid_q <= '0;
+ gen_last_q <= '0;
flag0_q <= '0;
statedb_wr_select_q <= '0;
genbits_stage_fips_sw_q <= '0;
@@ -350,6 +355,7 @@
end else begin
acmd_q <= acmd_d;
shid_q <= shid_d;
+ gen_last_q <= gen_last_d;
flag0_q <= flag0_d;
statedb_wr_select_q <= statedb_wr_select_d;
genbits_stage_fips_sw_q <= genbits_stage_fips_sw_d;
@@ -817,6 +823,7 @@
assign acmd_hold = acmd_sop ? acmd_bus[2:0] : acmd_q;
assign flag0 = acmd_bus[8];
assign shid = acmd_bus[15:12];
+ assign gen_last = acmd_bus[16];
assign acmd_d =
(!cs_enable) ? '0 :
@@ -829,6 +836,11 @@
state_db_reg_rd_id_pulse ? state_db_reg_rd_id :
shid_q;
+ assign gen_last_d =
+ (!cs_enable) ? '0 :
+ acmd_sop ? gen_last :
+ gen_last_q;
+
assign flag0_d =
(!cs_enable) ? '0 :
acmd_sop ? flag0 :
@@ -974,8 +986,8 @@
// muxes for statedb block inputs
assign state_db_wr_req = gen_blk_select ? gen_result_wr_req : cmd_result_wr_req;
assign state_db_wr_inst_id = gen_blk_select ? gen_result_inst_id : cmd_result_inst_id;
- assign state_db_wr_fips = cmd_result_fips;
- assign state_db_wr_ccmd = cmd_result_ccmd;
+ assign state_db_wr_fips = gen_blk_select ? gen_result_fips : cmd_result_fips;
+ assign state_db_wr_ccmd = gen_blk_select ? gen_result_ccmd : cmd_result_ccmd;
assign state_db_wr_key = gen_blk_select ? gen_result_key : cmd_result_key;
assign state_db_wr_v = gen_blk_select ? gen_result_v : cmd_result_v;
assign state_db_wr_rc = gen_blk_select ? gen_result_rc : cmd_result_rc;
@@ -1058,6 +1070,7 @@
.ctr_drbg_cmd_rdy_o(ctr_drbg_cmd_req_rdy),
.ctr_drbg_cmd_ccmd_i(ctr_drbg_cmd_ccmd),
.ctr_drbg_cmd_inst_id_i(shid_q),
+ .ctr_drbg_cmd_glast_i(gen_last_q),
.ctr_drbg_cmd_entropy_i(cmd_entropy),
.ctr_drbg_cmd_entropy_fips_i(cmd_entropy_fips), // send to state_db
.ctr_drbg_cmd_adata_i(packer_adata),
@@ -1071,6 +1084,7 @@
.ctr_drbg_cmd_rdy_i(cmd_result_ack_rdy),
.ctr_drbg_cmd_ccmd_o(cmd_result_ccmd),
.ctr_drbg_cmd_inst_id_o(cmd_result_inst_id),
+ .ctr_drbg_cmd_glast_o(cmd_result_glast),
.ctr_drbg_cmd_fips_o(cmd_result_fips),
.ctr_drbg_cmd_adata_o(cmd_result_adata),
.ctr_drbg_cmd_key_o(cmd_result_key),
@@ -1316,6 +1330,7 @@
.ctr_drbg_gen_rdy_o(ctr_drbg_gen_req_rdy),
.ctr_drbg_gen_ccmd_i(cmd_result_ccmd),
.ctr_drbg_gen_inst_id_i(cmd_result_inst_id),
+ .ctr_drbg_gen_glast_i(cmd_result_glast),
.ctr_drbg_gen_fips_i(cmd_result_fips),
.ctr_drbg_gen_adata_i(cmd_result_adata),
.ctr_drbg_gen_key_i(cmd_result_key),
@@ -1325,7 +1340,7 @@
.ctr_drbg_gen_ack_o(gen_result_wr_req),
.ctr_drbg_gen_sts_o(gen_result_ack_sts),
.ctr_drbg_gen_rdy_i(gen_result_ack_rdy),
- .ctr_drbg_gen_ccmd_o(), // NC
+ .ctr_drbg_gen_ccmd_o(gen_result_ccmd),
.ctr_drbg_gen_inst_id_o(gen_result_inst_id),
.ctr_drbg_gen_fips_o(gen_result_fips),
.ctr_drbg_gen_key_o(gen_result_key),
diff --git a/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv b/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv
index 8fe0b2d..f71a51c 100644
--- a/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv
+++ b/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv
@@ -23,6 +23,7 @@
output logic ctr_drbg_cmd_rdy_o, // ready to process the req above
input logic [Cmd-1:0] ctr_drbg_cmd_ccmd_i, // current command
input logic [StateId-1:0] ctr_drbg_cmd_inst_id_i, // instantance id
+ input logic ctr_drbg_cmd_glast_i, // gen cmd last beat
input logic [SeedLen-1:0] ctr_drbg_cmd_entropy_i, // es entropy
input logic ctr_drbg_cmd_entropy_fips_i, // es entropy)fips
input logic [SeedLen-1:0] ctr_drbg_cmd_adata_i, // additional data
@@ -36,6 +37,7 @@
input logic ctr_drbg_cmd_rdy_i, // ready to process the ack above
output logic [Cmd-1:0] ctr_drbg_cmd_ccmd_o,
output logic [StateId-1:0] ctr_drbg_cmd_inst_id_o,
+ output logic ctr_drbg_cmd_glast_o,
output logic ctr_drbg_cmd_fips_o,
output logic [SeedLen-1:0] ctr_drbg_cmd_adata_o,
output logic [KeyLen-1:0] ctr_drbg_cmd_key_o,
@@ -64,16 +66,17 @@
);
localparam int CmdreqFifoDepth = 1;
- localparam int CmdreqFifoWidth = KeyLen+BlkLen+CtrLen+1+2*SeedLen+StateId+Cmd;
+ localparam int CmdreqFifoWidth = KeyLen+BlkLen+CtrLen+1+2*SeedLen+1+StateId+Cmd;
localparam int RCStageFifoDepth = 1;
- localparam int RCStageFifoWidth = KeyLen+BlkLen+StateId+CtrLen+1+SeedLen+Cmd;
+ localparam int RCStageFifoWidth = KeyLen+BlkLen+StateId+CtrLen+1+SeedLen+1+Cmd;
localparam int KeyVRCFifoDepth = 1;
- localparam int KeyVRCFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+StateId+Cmd;
+ localparam int KeyVRCFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+1+StateId+Cmd;
// signals
logic [Cmd-1:0] cmdreq_ccmd;
logic [StateId-1:0] cmdreq_id;
+ logic cmdreq_glast;
logic [SeedLen-1:0] cmdreq_entropy;
logic cmdreq_entropy_fips;
logic [SeedLen-1:0] cmdreq_adata;
@@ -91,6 +94,7 @@
logic [StateId-1:0] rcstage_id;
logic [CtrLen-1:0] rcstage_rc;
logic [Cmd-1:0] rcstage_ccmd;
+ logic rcstage_glast;
logic [SeedLen-1:0] rcstage_adata;
logic rcstage_fips;
logic fips_modified;
@@ -159,6 +163,7 @@
assign sfifo_cmdreq_wdata = {ctr_drbg_cmd_key_i,ctr_drbg_cmd_v_i,
ctr_drbg_cmd_rc_i,fips_modified,
ctr_drbg_cmd_entropy_i,ctr_drbg_cmd_adata_i,
+ ctr_drbg_cmd_glast_i,
ctr_drbg_cmd_inst_id_i,ctr_drbg_cmd_ccmd_i};
assign sfifo_cmdreq_push = ctr_drbg_cmd_enable_i && ctr_drbg_cmd_req_i;
@@ -168,7 +173,7 @@
assign {cmdreq_key,cmdreq_v,cmdreq_rc,
cmdreq_entropy_fips,cmdreq_entropy,cmdreq_adata,
- cmdreq_id,cmdreq_ccmd} = sfifo_cmdreq_rdata;
+ cmdreq_glast,cmdreq_id,cmdreq_ccmd} = sfifo_cmdreq_rdata;
assign ctr_drbg_cmd_rdy_o = !sfifo_cmdreq_full;
@@ -210,8 +215,7 @@
(cmdreq_ccmd == UPD) ? cmdreq_rc :
'0;
- assign prep_gen_adata_null = (cmdreq_ccmd == GEN) && (cmdreq_adata == '0) &&
- sfifo_cmdreq_not_empty;
+ assign prep_gen_adata_null = (cmdreq_ccmd == GEN) && (cmdreq_adata == '0);
assign gen_adata_null_d = prep_gen_adata_null;
@@ -250,10 +254,10 @@
assign sfifo_rcstage_push = sfifo_cmdreq_pop;
assign sfifo_rcstage_wdata = {prep_key,prep_v,cmdreq_id,prep_rc,cmdreq_entropy_fips,
- cmdreq_adata,cmdreq_ccmd};
+ cmdreq_adata,cmdreq_glast,cmdreq_ccmd};
assign sfifo_rcstage_pop = sfifo_rcstage_not_empty && (upd_cmd_ack_i || gen_adata_null_q);
assign {rcstage_key,rcstage_v,rcstage_id,rcstage_rc,rcstage_fips,
- rcstage_adata,rcstage_ccmd} = sfifo_rcstage_rdata;
+ rcstage_adata,rcstage_glast,rcstage_ccmd} = sfifo_rcstage_rdata;
assign ctr_drbg_cmd_sfifo_rcstage_err_o =
@@ -290,16 +294,16 @@
// if a UNI command, reset the state values
assign sfifo_keyvrc_wdata = (rcstage_ccmd == UNI) ?
- {{(KeyLen+BlkLen+CtrLen+1+SeedLen){1'b0}},upd_cmd_inst_id_i,upd_cmd_ccmd_i} :
+ {{(KeyLen+BlkLen+CtrLen+1+SeedLen){1'b0}},rcstage_glast,upd_cmd_inst_id_i,upd_cmd_ccmd_i} :
gen_adata_null_q ?
{rcstage_key,rcstage_v,rcstage_rc,rcstage_fips,
- rcstage_adata,rcstage_id,rcstage_ccmd} :
+ rcstage_adata,rcstage_glast,rcstage_id,rcstage_ccmd} :
{upd_cmd_key_i,upd_cmd_v_i,rcstage_rc,rcstage_fips,
- rcstage_adata,upd_cmd_inst_id_i,upd_cmd_ccmd_i};
+ rcstage_adata,rcstage_glast,upd_cmd_inst_id_i,upd_cmd_ccmd_i};
assign sfifo_keyvrc_pop = ctr_drbg_cmd_rdy_i && sfifo_keyvrc_not_empty;
assign {ctr_drbg_cmd_key_o,ctr_drbg_cmd_v_o,ctr_drbg_cmd_rc_o,
- ctr_drbg_cmd_fips_o,ctr_drbg_cmd_adata_o,
+ ctr_drbg_cmd_fips_o,ctr_drbg_cmd_adata_o,ctr_drbg_cmd_glast_o,
ctr_drbg_cmd_inst_id_o,ctr_drbg_cmd_ccmd_o} = sfifo_keyvrc_rdata;
assign ctr_drbg_cmd_sfifo_keyvrc_err_o =
diff --git a/hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv b/hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv
index 9068f64..e68483c 100644
--- a/hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv
+++ b/hw/ip/csrng/rtl/csrng_ctr_drbg_gen.sv
@@ -25,6 +25,7 @@
output logic ctr_drbg_gen_rdy_o, // ready to process the req above
input logic [Cmd-1:0] ctr_drbg_gen_ccmd_i, // current command
input logic [StateId-1:0] ctr_drbg_gen_inst_id_i, // instantance id
+ input logic ctr_drbg_gen_glast_i, // gen cmd last beat
input logic ctr_drbg_gen_fips_i, // fips
input logic [SeedLen-1:0] ctr_drbg_gen_adata_i, // additional data
input logic [KeyLen-1:0] ctr_drbg_gen_key_i,
@@ -83,19 +84,20 @@
);
localparam int GenreqFifoDepth = 1;
- localparam int GenreqFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+StateId+Cmd;
+ localparam int GenreqFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+1+StateId+Cmd;
localparam int BlkEncAckFifoDepth = 1;
localparam int BlkEncAckFifoWidth = BlkLen+StateId+Cmd;
localparam int AdstageFifoDepth = 1;
- localparam int AdstageFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen;
+ localparam int AdstageFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+1;
localparam int RCStageFifoDepth = 1;
- localparam int RCStageFifoWidth = BlkLen+CtrLen+1;
+ localparam int RCStageFifoWidth = KeyLen+BlkLen+BlkLen+CtrLen+1+1+StateId+Cmd;
localparam int GenbitsFifoDepth = 1;
localparam int GenbitsFifoWidth = 1+BlkLen+KeyLen+BlkLen+CtrLen+StateId+Cmd;
// signals
logic [Cmd-1:0] genreq_ccmd;
logic [StateId-1:0] genreq_id;
+ logic genreq_glast;
logic [SeedLen-1:0] genreq_adata;
logic genreq_fips;
logic [KeyLen-1:0] genreq_key;
@@ -106,12 +108,18 @@
logic [BlkLen-1:0] adstage_v;
logic [CtrLen-1:0] adstage_rc;
logic adstage_fips;
+ logic adstage_glast;
logic [SeedLen-1:0] adstage_adata;
+ logic [KeyLen-1:0] rcstage_key;
+ logic [BlkLen-1:0] rcstage_v;
logic [BlkLen-1:0] rcstage_bits;
logic [CtrLen-1:0] rcstage_rc;
+ logic rcstage_glast;
logic rcstage_fips;
logic [CtrLen-1:0] rcstage_rc_plus1;
+ logic [Cmd-1:0] rcstage_ccmd;
+ logic [StateId-1:0] rcstage_inst_id;
logic [Cmd-1:0] genreq_ccmd_modified;
logic [Cmd-1:0] bencack_ccmd_modified;
@@ -254,13 +262,13 @@
assign genreq_ccmd_modified = (ctr_drbg_gen_ccmd_i == GEN) ? GENB : INV;
assign sfifo_genreq_wdata = {ctr_drbg_gen_key_i,ctr_drbg_gen_v_i,ctr_drbg_gen_rc_i,
- ctr_drbg_gen_fips_i,ctr_drbg_gen_adata_i,
+ ctr_drbg_gen_fips_i,ctr_drbg_gen_adata_i,ctr_drbg_gen_glast_i,
ctr_drbg_gen_inst_id_i,genreq_ccmd_modified};
assign sfifo_genreq_push = ctr_drbg_gen_enable_i && ctr_drbg_gen_req_i;
assign {genreq_key,genreq_v,genreq_rc,
- genreq_fips,genreq_adata,
+ genreq_fips,genreq_adata,genreq_glast,
genreq_id,genreq_ccmd} = sfifo_genreq_rdata;
assign ctr_drbg_gen_rdy_o = !sfifo_genreq_full;
@@ -381,9 +389,10 @@
.depth_o ()
);
- assign sfifo_adstage_wdata = {genreq_key,v_sized,genreq_rc,genreq_fips,genreq_adata};
+ assign sfifo_adstage_wdata = {genreq_key,v_sized,genreq_rc,genreq_fips,genreq_adata,genreq_glast};
assign sfifo_adstage_pop = sfifo_adstage_not_empty && sfifo_bencack_pop;
- assign {adstage_key,adstage_v,adstage_rc,adstage_fips,adstage_adata} = sfifo_adstage_rdata;
+ assign {adstage_key,adstage_v,adstage_rc,adstage_fips,
+ adstage_adata,adstage_glast} = sfifo_adstage_rdata;
assign ctr_drbg_gen_sfifo_gadstage_err_o =
{(sfifo_adstage_push && sfifo_adstage_full),
@@ -421,7 +430,8 @@
assign sfifo_bencack_wdata = {block_encrypt_v_i,block_encrypt_inst_id_i,bencack_ccmd_modified};
assign block_encrypt_rdy_o = !sfifo_bencack_full;
- assign sfifo_bencack_pop = !sfifo_rcstage_full && sfifo_bencack_not_empty && upd_gen_rdy_i;
+ assign sfifo_bencack_pop = !sfifo_rcstage_full && sfifo_bencack_not_empty &&
+ (upd_gen_rdy_i || !adstage_glast);
assign {sfifo_bencack_bits,sfifo_bencack_inst_id,sfifo_bencack_ccmd} = sfifo_bencack_rdata;
@@ -436,7 +446,7 @@
//--------------------------------------------
// send to the update block
- assign gen_upd_req_o = sfifo_bencack_not_empty;
+ assign gen_upd_req_o = sfifo_bencack_not_empty && adstage_glast;
assign gen_upd_ccmd_o = sfifo_bencack_ccmd;
assign gen_upd_inst_id_o = sfifo_bencack_inst_id;
assign gen_upd_pdata_o = adstage_adata;
@@ -469,9 +479,14 @@
);
assign sfifo_rcstage_push = sfifo_adstage_pop;
- assign sfifo_rcstage_wdata = {sfifo_bencack_bits,adstage_rc,adstage_fips};
- assign sfifo_rcstage_pop = sfifo_rcstage_not_empty && upd_gen_ack_i;
- assign {rcstage_bits,rcstage_rc,rcstage_fips} = sfifo_rcstage_rdata;
+ assign sfifo_rcstage_wdata = {adstage_key,adstage_v,sfifo_bencack_bits,
+ adstage_rc,adstage_fips,adstage_glast,
+ sfifo_bencack_inst_id,sfifo_bencack_ccmd};
+
+ assign sfifo_rcstage_pop = sfifo_rcstage_not_empty && (upd_gen_ack_i || !rcstage_glast);
+
+ assign {rcstage_key,rcstage_v,rcstage_bits,rcstage_rc,rcstage_fips,rcstage_glast,
+ rcstage_inst_id,rcstage_ccmd} = sfifo_rcstage_rdata;
assign ctr_drbg_gen_sfifo_grcstage_err_o =
@@ -509,9 +524,11 @@
assign rcstage_rc_plus1 = (rcstage_rc+1);
- assign sfifo_genbits_wdata =
- {rcstage_fips,rcstage_bits,upd_gen_key_i,upd_gen_v_i,
- rcstage_rc_plus1,upd_gen_inst_id_i,upd_gen_ccmd_i};
+ assign sfifo_genbits_wdata = rcstage_glast ?
+ {rcstage_fips,rcstage_bits,upd_gen_key_i,upd_gen_v_i,
+ rcstage_rc_plus1,upd_gen_inst_id_i,upd_gen_ccmd_i} :
+ {rcstage_fips,rcstage_bits,rcstage_key,rcstage_v,
+ rcstage_rc,rcstage_inst_id,rcstage_ccmd};
assign sfifo_genbits_pop = ctr_drbg_gen_rdy_i && sfifo_genbits_not_empty;
assign {ctr_drbg_gen_fips_o,ctr_drbg_gen_bits_o,
diff --git a/hw/ip/csrng/rtl/csrng_state_db.sv b/hw/ip/csrng/rtl/csrng_state_db.sv
index bb9ab02..c3b1dd0 100644
--- a/hw/ip/csrng/rtl/csrng_state_db.sv
+++ b/hw/ip/csrng/rtl/csrng_state_db.sv
@@ -180,7 +180,7 @@
assign instance_status =
(state_db_wr_ccmd_i == INS) ||
(state_db_wr_ccmd_i == RES) ||
- (state_db_wr_ccmd_i == GEN) ||
+ (state_db_wr_ccmd_i == GENU) ||
(state_db_wr_ccmd_i == UPD);
