[rtl/alert] change the naming from _en_i to _req_i
This PR changes alert_handler related RTL and DV files.
It changes variable namings in from `_en_i` to `_req_i` according to the suggestion from PR #2534
Signed-off-by: Cindy Chen <chencindy@google.com>
diff --git a/hw/ip/alert_handler/dv/tb/tb.sv b/hw/ip/alert_handler/dv/tb/tb.sv
index 5b5bf0b..120a8c5 100644
--- a/hw/ip/alert_handler/dv/tb/tb.sv
+++ b/hw/ip/alert_handler/dv/tb/tb.sv
@@ -55,7 +55,7 @@
assign esc_device_if[k].esc_tx.esc_p = esc_tx[k].esc_p;
assign esc_device_if[k].esc_tx.esc_n = esc_tx[k].esc_n;
// TODO: add assertions to check the probed signal
- assign probe_if[k].esc_en = dut.esc_sig_en[k];
+ assign probe_if[k].esc_en = dut.esc_sig_req[k];
initial begin
uvm_config_db#(virtual alert_esc_if)::set(null, $sformatf("*.env.esc_device_agent[%0d]", k),
"vif", esc_device_if[k]);
diff --git a/hw/ip/alert_handler/rtl/alert_handler.sv b/hw/ip/alert_handler/rtl/alert_handler.sv
index 65035ad..bf3b5a2 100644
--- a/hw/ip/alert_handler/rtl/alert_handler.sv
+++ b/hw/ip/alert_handler/rtl/alert_handler.sv
@@ -68,9 +68,9 @@
logic [N_LOC_ALERT-1:0] loc_alert_trig;
- logic [NAlerts-1:0] alert_ping_en;
+ logic [NAlerts-1:0] alert_ping_req;
logic [NAlerts-1:0] alert_ping_ok;
- logic [N_ESC_SEV-1:0] esc_ping_en;
+ logic [N_ESC_SEV-1:0] esc_ping_req;
logic [N_ESC_SEV-1:0] esc_ping_ok;
alert_handler_ping_timer i_ping_timer (
@@ -85,8 +85,8 @@
// this determines the range of the randomly generated
// wait period between ping. maximum mask width is PING_CNT_DW.
.wait_cyc_mask_i ( PING_CNT_DW'(24'hFFFFFF) ),
- .alert_ping_en_o ( alert_ping_en ),
- .esc_ping_en_o ( esc_ping_en ),
+ .alert_ping_req_o ( alert_ping_req ),
+ .esc_ping_req_o ( esc_ping_req ),
.alert_ping_ok_i ( alert_ping_ok ),
.esc_ping_ok_i ( esc_ping_ok ),
.alert_ping_fail_o ( loc_alert_trig[0] ),
@@ -107,7 +107,7 @@
) i_alert_receiver (
.clk_i ,
.rst_ni ,
- .ping_en_i ( alert_ping_en[k] ),
+ .ping_req_i ( alert_ping_req[k] ),
.ping_ok_o ( alert_ping_ok[k] ),
.integ_fail_o ( alert_integfail[k] ),
.alert_o ( alert_trig[k] ),
@@ -139,7 +139,7 @@
////////////////////////////////////
logic [N_CLASSES-1:0] class_accum_trig;
- logic [N_CLASSES-1:0][N_ESC_SEV-1:0] class_esc_sig_en;
+ logic [N_CLASSES-1:0][N_ESC_SEV-1:0] class_esc_sig_req;
for (genvar k = 0; k < N_CLASSES; k++) begin : gen_classes
alert_handler_accu i_accu (
@@ -169,7 +169,7 @@
.esc_trig_o ( hw2reg_wrap.class_esc_trig[k] ),
.esc_cnt_o ( hw2reg_wrap.class_esc_cnt[k] ),
.esc_state_o ( hw2reg_wrap.class_esc_state[k] ),
- .esc_sig_en_o ( class_esc_sig_en[k] )
+ .esc_sig_req_o ( class_esc_sig_req[k] )
);
end
@@ -177,24 +177,24 @@
// Escalation Senders //
////////////////////////
- logic [N_ESC_SEV-1:0] esc_sig_en;
+ logic [N_ESC_SEV-1:0] esc_sig_req;
logic [N_ESC_SEV-1:0] esc_integfail;
- logic [N_ESC_SEV-1:0][N_CLASSES-1:0] esc_sig_en_trsp;
+ logic [N_ESC_SEV-1:0][N_CLASSES-1:0] esc_sig_req_trsp;
for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_esc_sev
for (genvar j = 0; j < N_CLASSES; j++) begin : gen_transp
- assign esc_sig_en_trsp[k][j] = class_esc_sig_en[j][k];
+ assign esc_sig_req_trsp[k][j] = class_esc_sig_req[j][k];
end
- assign esc_sig_en[k] = |esc_sig_en_trsp[k];
+ assign esc_sig_req[k] = |esc_sig_req_trsp[k];
prim_esc_sender i_esc_sender (
.clk_i,
.rst_ni,
- .ping_en_i ( esc_ping_en[k] ),
+ .ping_req_i ( esc_ping_req[k] ),
.ping_ok_o ( esc_ping_ok[k] ),
.integ_fail_o ( esc_integfail[k] ),
- .esc_en_i ( esc_sig_en[k] ),
+ .esc_req_i ( esc_sig_req[k] ),
.esc_rx_i ( esc_rx_i[k] ),
.esc_tx_o ( esc_tx_o[k] )
);
diff --git a/hw/ip/alert_handler/rtl/alert_handler_esc_timer.sv b/hw/ip/alert_handler/rtl/alert_handler_esc_timer.sv
index cb2fb45..e633892 100644
--- a/hw/ip/alert_handler/rtl/alert_handler_esc_timer.sv
+++ b/hw/ip/alert_handler/rtl/alert_handler_esc_timer.sv
@@ -33,7 +33,7 @@
[EscCntDw-1:0] phase_cyc_i, // cycle counts of individual phases
output logic esc_trig_o, // asserted if escalation triggers
output logic [EscCntDw-1:0] esc_cnt_o, // current timeout / escalation count
- output logic [N_ESC_SEV-1:0] esc_sig_en_o, // escalation signal outputs
+ output logic [N_ESC_SEV-1:0] esc_sig_req_o, // escalation signal outputs
// current state output
// 000: idle, 001: irq timeout counting 100: phase0, 101: phase1, 110: phase2, 111: phase3
output cstate_e esc_state_o
@@ -191,7 +191,7 @@
// generate configuration mask for escalation enable signals
assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
// mask reduce current phase state vector
- assign esc_sig_en_o[k] = |(esc_map_oh[k] & phase_oh);
+ assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh);
end
///////////////
diff --git a/hw/ip/alert_handler/rtl/alert_handler_ping_timer.sv b/hw/ip/alert_handler/rtl/alert_handler_ping_timer.sv
index 937c882..055926a 100644
--- a/hw/ip/alert_handler/rtl/alert_handler_ping_timer.sv
+++ b/hw/ip/alert_handler/rtl/alert_handler_ping_timer.sv
@@ -36,8 +36,8 @@
input [NAlerts-1:0] alert_en_i, // determines which alerts to ping
input [PING_CNT_DW-1:0] ping_timeout_cyc_i, // timeout in cycles
input [PING_CNT_DW-1:0] wait_cyc_mask_i, // wait cycles mask
- output logic [NAlerts-1:0] alert_ping_en_o, // enable to alert receivers
- output logic [N_ESC_SEV-1:0] esc_ping_en_o, // enable to esc senders
+ output logic [NAlerts-1:0] alert_ping_req_o, // request to alert receivers
+ output logic [N_ESC_SEV-1:0] esc_ping_req_o, // enable to esc senders
input [NAlerts-1:0] alert_ping_ok_i, // response from alert receivers
input [N_ESC_SEV-1:0] esc_ping_ok_i, // response from esc senders
output logic alert_ping_fail_o, // any of the alert receivers failed
@@ -137,8 +137,8 @@
// generate ping enable vector
assign ping_sel = NModsToPing'(ping_en) << id_to_ping;
- assign alert_ping_en_o = ping_sel[NAlerts-1:0];
- assign esc_ping_en_o = ping_sel[NModsToPing-1:NAlerts];
+ assign alert_ping_req_o = ping_sel[NAlerts-1:0];
+ assign esc_ping_req_o = ping_sel[NModsToPing-1:NAlerts];
// mask out response
assign ping_ok = |({esc_ping_ok_i, alert_ping_ok_i} & ping_sel);
diff --git a/hw/ip/prim/rtl/prim_alert_receiver.sv b/hw/ip/prim/rtl/prim_alert_receiver.sv
index f8954b8..38951cb 100644
--- a/hw/ip/prim/rtl/prim_alert_receiver.sv
+++ b/hw/ip/prim/rtl/prim_alert_receiver.sv
@@ -11,10 +11,10 @@
// raise an error by asserting integ_fail_o.
//
// Further, the module supports ping testing of the alert diff pair. In order to
-// initiate a ping test, ping_en_i shall be set to 1'b1 until ping_ok_o is
+// initiate a ping test, ping_req_i shall be set to 1'b1 until ping_ok_o is
// asserted for one cycle. The signal may be de-asserted (e.g. after a long)
// timeout period. However note that all ping responses that come in after
-// deasserting ping_en_i will be treated as native alerts.
+// deasserting ping_req_i will be treated as native alerts.
//
// The protocol works in both asynchronous and synchronous cases. In the
// asynchronous case, the parameter AsyncOn must be set to 1'b1 in order to
@@ -39,7 +39,7 @@
input rst_ni,
// this triggers a ping test. keep asserted
// until ping_ok_o is asserted.
- input ping_en_i,
+ input ping_req_i,
output logic ping_ok_o,
// asserted if signal integrity issue detected
output logic integ_fail_o,
@@ -79,13 +79,13 @@
state_e state_d, state_q;
logic ping_rise;
logic ping_tog_d, ping_tog_q, ack_d, ack_q;
- logic ping_en_d, ping_en_q;
+ logic ping_req_d, ping_req_q;
logic ping_pending_d, ping_pending_q;
- // signal ping request upon positive transition on ping_en_i
+ // signal ping request upon positive transition on ping_req_i
// signalling is performed by a level change event on the diff output
- assign ping_en_d = ping_en_i;
- assign ping_rise = ping_en_i && !ping_en_q;
+ assign ping_req_d = ping_req_i;
+ assign ping_rise = ping_req_i && !ping_req_q;
assign ping_tog_d = (ping_rise) ? ~ping_tog_q : ping_tog_q;
// the ping pending signal is used to in the FSM to distinguish whether the
@@ -93,7 +93,7 @@
// it is important that this is only set on a rising ping_en level change, since
// otherwise the ping enable signal could be abused to "mask" all native alerts
// as ping responses by constantly tying it to 1.
- assign ping_pending_d = ping_rise | ((~ping_ok_o) & ping_en_i & ping_pending_q);
+ assign ping_pending_d = ping_rise | ((~ping_ok_o) & ping_req_i & ping_pending_q);
// diff pair outputs
assign alert_rx_o.ack_p = ack_q;
@@ -156,13 +156,13 @@
state_q <= Idle;
ack_q <= 1'b0;
ping_tog_q <= 1'b0;
- ping_en_q <= 1'b0;
+ ping_req_q <= 1'b0;
ping_pending_q <= 1'b0;
end else begin
state_q <= state_d;
ack_q <= ack_d;
ping_tog_q <= ping_tog_d;
- ping_en_q <= ping_en_d;
+ ping_req_q <= ping_req_d;
ping_pending_q <= ping_pending_d;
end
end
@@ -182,11 +182,11 @@
`ASSERT(PingDiffOk_A, alert_rx_o.ping_p ^ alert_rx_o.ping_n)
`ASSERT(AckDiffOk_A, alert_rx_o.ack_p ^ alert_rx_o.ack_n)
// ping request at input -> need to see encoded ping request
- `ASSERT(PingRequest0_A, ##1 $rose(ping_en_i) |=> $changed(alert_rx_o.ping_p))
+ `ASSERT(PingRequest0_A, ##1 $rose(ping_req_i) |=> $changed(alert_rx_o.ping_p))
// ping response implies it has been requested
`ASSERT(PingResponse0_A, ping_ok_o |-> ping_pending_q)
// correctly latch ping request
- `ASSERT(PingPending_A, ##1 $rose(ping_en_i) |=> ping_pending_q)
+ `ASSERT(PingPending_A, ##1 $rose(ping_req_i) |=> ping_pending_q)
if (AsyncOn) begin : gen_async_assert
// signal integrity check propagation
diff --git a/hw/ip/prim/rtl/prim_esc_sender.sv b/hw/ip/prim/rtl/prim_esc_sender.sv
index 960461f..a911c41 100644
--- a/hw/ip/prim/rtl/prim_esc_sender.sv
+++ b/hw/ip/prim/rtl/prim_esc_sender.sv
@@ -8,7 +8,7 @@
// The module supports in-band ping testing of the escalation
// wires. This is accomplished by sending out a single, differentially
// encoded pulse on esc_p/n which will be interpreted as a ping
-// request by the escalation receiver. Note that ping_en_i shall
+// request by the escalation receiver. Note that ping_req_i shall
// be held high until either ping_ok_o or integ_fail_o is asserted.
//
// Native escalation enable pulses are differentiated from ping
@@ -27,12 +27,12 @@
input clk_i,
input rst_ni,
// this triggers a ping test. keep asserted until ping_ok_o is pulsed high.
- input ping_en_i,
+ input ping_req_i,
output logic ping_ok_o,
// asserted if signal integrity issue detected
output logic integ_fail_o,
- // escalation enable signal
- input esc_en_i,
+ // escalation request signal
+ input esc_req_i,
// escalation / ping response
input esc_rx_t esc_rx_i,
// escalation output diff pair
@@ -63,15 +63,15 @@
// TX Logic //
//////////////
- logic ping_en_d, ping_en_q;
- logic esc_en_d, esc_en_q, esc_en_q1;
+ logic ping_req_d, ping_req_q;
+ logic esc_req_d, esc_req_q, esc_req_q1;
- assign ping_en_d = ping_en_i;
- assign esc_en_d = esc_en_i;
+ assign ping_req_d = ping_req_i;
+ assign esc_req_d = esc_req_i;
// ping enable is 1 cycle pulse
// escalation pulse is always longer than 2 cycles
- assign esc_tx_o.esc_p = esc_en_i | esc_en_q | (ping_en_d & ~ping_en_q);
+ assign esc_tx_o.esc_p = esc_req_i | esc_req_q | (ping_req_d & ~ping_req_q);
assign esc_tx_o.esc_n = ~esc_tx_o.esc_p;
//////////////
@@ -92,9 +92,9 @@
unique case (state_q)
// wait for ping or escalation enable
Idle: begin
- if (esc_en_i) begin
+ if (esc_req_i) begin
state_d = CheckEscRespHi;
- end else if (ping_en_i) begin
+ end else if (ping_req_i) begin
state_d = CheckPingResp0;
end
// any assertion of the response signal
@@ -125,7 +125,7 @@
state_d = CheckPingResp1;
// abort sequence immediately if escalation is signalled,
// jump to escalation response checking (lo state)
- if (esc_en_i) begin
+ if (esc_req_i) begin
state_d = CheckEscRespLo;
// abort if response is wrong
end else if (!resp) begin
@@ -137,7 +137,7 @@
state_d = CheckPingResp2;
// abort sequence immediately if escalation is signalled,
// jump to escalation response checking (hi state)
- if (esc_en_i) begin
+ if (esc_req_i) begin
state_d = CheckEscRespHi;
// abort if response is wrong
end else if (resp) begin
@@ -149,7 +149,7 @@
state_d = CheckPingResp3;
// abort sequence immediately if escalation is signalled,
// jump to escalation response checking (lo state)
- if (esc_en_i) begin
+ if (esc_req_i) begin
state_d = CheckEscRespLo;
// abort if response is wrong
end else if (!resp) begin
@@ -161,13 +161,13 @@
state_d = Idle;
// abort sequence immediately if escalation is signalled,
// jump to escalation response checking (hi state)
- if (esc_en_i) begin
+ if (esc_req_i) begin
state_d = CheckEscRespHi;
// abort if response is wrong
end else if (resp) begin
integ_fail_o = 1'b1;
end else begin
- ping_ok_o = ping_en_i;
+ ping_ok_o = ping_req_i;
end
end
default : state_d = Idle;
@@ -183,7 +183,7 @@
// escalation takes precedence,
// immediately return ok in that case
- if ((esc_en_i || esc_en_q || esc_en_q1) && ping_en_i) begin
+ if ((esc_req_i || esc_req_q || esc_req_q1) && ping_req_i) begin
ping_ok_o = 1'b1;
end
end
@@ -195,14 +195,14 @@
always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
if (!rst_ni) begin
state_q <= Idle;
- esc_en_q <= 1'b0;
- esc_en_q1 <= 1'b0;
- ping_en_q <= 1'b0;
+ esc_req_q <= 1'b0;
+ esc_req_q1 <= 1'b0;
+ ping_req_q <= 1'b0;
end else begin
state_q <= state_d;
- esc_en_q <= esc_en_d;
- esc_en_q1 <= esc_en_q;
- ping_en_q <= ping_en_d;
+ esc_req_q <= esc_req_d;
+ esc_req_q1 <= esc_req_q;
+ ping_req_q <= ping_req_d;
end
end
@@ -220,11 +220,11 @@
// signal integrity check propagation
`ASSERT(SigIntCheck0_A, esc_rx_i.resp_p == esc_rx_i.resp_n |-> integ_fail_o)
// this happens in case we did not get a correct escalation response
- `ASSERT(SigIntCheck1_A, ##1 $rose(esc_en_i) &&
+ `ASSERT(SigIntCheck1_A, ##1 $rose(esc_req_i) &&
state_q inside {Idle, CheckPingResp1, CheckPingResp3} ##1 !esc_rx_i.resp_p |->
integ_fail_o, clk_i, !rst_ni || (esc_rx_i.resp_p == esc_rx_i.resp_n) ||
(state_q == Idle && resp))
- `ASSERT(SigIntCheck2_A, ##1 $rose(esc_en_i) &&
+ `ASSERT(SigIntCheck2_A, ##1 $rose(esc_req_i) &&
state_q inside {CheckPingResp0, CheckPingResp2} ##1 esc_rx_i.resp_p |->
integ_fail_o, clk_i, !rst_ni || (esc_rx_i.resp_p == esc_rx_i.resp_n) ||
(state_q == Idle && resp))
@@ -242,11 +242,11 @@
`ASSERT(StateEscRespHiBackCheck_A, state_q == CheckEscRespHi |-> $past(esc_tx_o.esc_p))
`ASSERT(StateEscRespLoBackCheck_A, state_q == CheckEscRespLo |-> $past(esc_tx_o.esc_p))
// check that escalation signal is at least 2 cycles high
- `ASSERT(EscCheck_A, esc_en_i |-> esc_tx_o.esc_p [*2] )
+ `ASSERT(EscCheck_A, esc_req_i |-> esc_tx_o.esc_p [*2] )
// escalation / ping collision
- `ASSERT(EscPingCheck_A, esc_en_i && ping_en_i |-> ping_ok_o)
+ `ASSERT(EscPingCheck_A, esc_req_i && ping_req_i |-> ping_ok_o)
// check that ping request results in only a single cycle pulse
- `ASSERT(PingCheck_A, ##1 $rose(ping_en_i) |-> esc_tx_o.esc_p ##1 !esc_tx_o.esc_p , clk_i,
- !rst_ni || esc_en_i || integ_fail_o)
+ `ASSERT(PingCheck_A, ##1 $rose(ping_req_i) |-> esc_tx_o.esc_p ##1 !esc_tx_o.esc_p , clk_i,
+ !rst_ni || esc_req_i || integ_fail_o)
endmodule : prim_esc_sender
