[doc] Simplify example for building the Verilator model
This is simpler and has the benefit of matching what we do in CI (so
we know it will continue to work).
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/doc/getting_started/setup_verilator.md b/doc/getting_started/setup_verilator.md
index 95f20d6..57adebb 100644
--- a/doc/getting_started/setup_verilator.md
+++ b/doc/getting_started/setup_verilator.md
@@ -51,11 +51,13 @@
## Simulating a design with Verilator
-First the simulation needs to built itself.
+First the RTL must be built into a simulator binary.
+This is done by running fusesoc, which collects up RTL code and passes it to Verilator to generate and then compile a C++ model.
+The fusesoc command line arguments are reasonably complicated so we have a wrapper script:
```console
$ cd $REPO_TOP
-$ fusesoc --cores-root . run --flag=fileset_top --target=sim --setup --build lowrisc:dv:chip_verilator_sim
+$ ci/scripts/build-chip-verilator earlgrey
```
Then we need to build software to run on the simulated system.
