[Verilator] Test pass/fail signature & banner
This change unifies the way the test status is determined and printed in
the simulation log file, across DV and Verilator. The DV report test
status method is invoked in top_earlgrey_verilator.sv after the pass /
fail signature is detected from SW. It prints a specific signature and
banner. The signature is used by DVSim to guage the test status.
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
index 1209140..df80abe 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
@@ -274,6 +274,7 @@
if (u_sw_test_status_if.sw_test_done) begin
$display("Verilator sim termination requested");
$display("Your simulation wrote to 0x%h", u_sw_test_status_if.sw_test_status_addr);
+ dv_test_status_pkg::dv_test_status(u_sw_test_status_if.sw_test_passed);
$finish;
end
end
diff --git a/hw/top_earlgrey/top_earlgrey_verilator.core b/hw/top_earlgrey/top_earlgrey_verilator.core
index 351c1df..9f454ac 100644
--- a/hw/top_earlgrey/top_earlgrey_verilator.core
+++ b/hw/top_earlgrey/top_earlgrey_verilator.core
@@ -20,6 +20,7 @@
- lowrisc:ibex:ibex_tracer
- lowrisc:dv:sim_sram
- lowrisc:dv:sw_test_status
+ - lowrisc:dv:dv_test_status
files:
- rtl/top_earlgrey_verilator.sv: { file_type: systemVerilogSource }
