| commit | 31fd7dc3c06edf895d29ec15914c7c2d6063f618 | [log] [tgz] |
|---|---|---|
| author | Udi Jonnalagadda <udij@google.com> | Thu Jan 14 15:23:44 2021 -0800 |
| committer | udinator <udij@google.com> | Thu Jan 14 18:23:36 2021 -0800 |
| tree | fc7fccc83c6ab6bde7a5c52a79c798ad32d3342d | |
| parent | c60393def6e4b45e7f614e3ee85c19869dc7b97f [diff] |
[rtl/sram_ctrl] update error signaling logic Currently SRAM controller performs a bitwise OR of the 2-bit error signal to check whether there are any correctable/uncorrectable memory errors. However correctable memory errors are not supported by the SRAM. This patch adds an assertion to ensure that the error bit indicating a correctable error never goes high and updates the error signaling logic to only rely on the bit indicating uncorrectable errors. Signed-off-by: Udi Jonnalagadda <udij@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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