| commit | 93f12ea8c42de02112c730bb28727008df658ee1 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Thu Feb 25 15:19:20 2021 +0000 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Sat Feb 27 14:14:50 2021 +0000 |
| tree | 3509c35528b7c280e601a32fa92c97bb61afbb0a | |
| parent | 6442e7ed8775f563d8568b331ddf78dad20d1611 [diff] |
[otbn] Remove enable_i input from otbn_core_model The previous code had a race in the initial blocks when used in otbn.sv. The obvious way to fix this in the SystemVerilog code would be to call otbn_model_init() just before we first call otbn_model_step. Unfortunately, you can't do that (for Verilator, at least) because that ends up mixing blocking and non-blocking assignments. Rather than think hard about how to do this properly in Verilog, we can just put in a simple layer of indirection in the C++ and only start the subprocess when we see start_i for the first time. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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