[dv/alert_handler] improve cov
1. Adjust reset timing to improve FSM cov
2. Fix ":=" to ":/"
Signed-off-by: Cindy Chen <chencindy@google.com>
diff --git a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv
index 39b4272..41842d4 100644
--- a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv
+++ b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv
@@ -65,10 +65,10 @@
endtask
virtual task alert_handler_wr_clren_regs(bit [NUM_ALERT_HANDLER_CLASSES-1:0] clr_en);
- csr_wr(.csr(ral.classa_clren), .value(clr_en[0]));
- csr_wr(.csr(ral.classb_clren), .value(clr_en[1]));
- csr_wr(.csr(ral.classc_clren), .value(clr_en[2]));
- csr_wr(.csr(ral.classd_clren), .value(clr_en[3]));
+ if (!clr_en[0]) csr_wr(.csr(ral.classa_clren), .value($urandom_range(0, 1)));
+ if (!clr_en[1]) csr_wr(.csr(ral.classb_clren), .value($urandom_range(0, 1)));
+ if (!clr_en[2]) csr_wr(.csr(ral.classc_clren), .value($urandom_range(0, 1)));
+ if (!clr_en[3]) csr_wr(.csr(ral.classd_clren), .value($urandom_range(0, 1)));
endtask
// write regen register if do_lock_config is set. If not set, 50% of chance to write value 0
diff --git a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv
index 2bde8e5..b361a72 100644
--- a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv
+++ b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv
@@ -8,6 +8,16 @@
constraint num_trans_c {
num_trans inside {[1:2]};
}
+
+ constraint delay_to_reset_c {
+ delay_to_reset dist {
+ [1 :1000] :/ 5,
+ [1001 :100_000] :/ 1,
+ [100_001 :1_000_000] :/ 1,
+ [1_000_001 :10_000_000] :/ 3
+ };
+ }
+
`uvm_object_new
virtual task body();
diff --git a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv
index d27ffe6..6d01a81 100644
--- a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv
+++ b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv
@@ -20,7 +20,7 @@
// increase the possibility to enable more alerts, because alert_handler only sends ping on
// enabled alerts
constraint enable_one_alert_c {
- alert_en dist {'b1111 := 9, [0:'b1110] := 1};
+ alert_en dist {'b1111 :/ 9, [0:'b1110] :/ 1};
}
constraint sig_int_c {
diff --git a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_ping_rsp_fail_vseq.sv b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_ping_rsp_fail_vseq.sv
index 28e7cc5..2375677 100644
--- a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_ping_rsp_fail_vseq.sv
+++ b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_ping_rsp_fail_vseq.sv
@@ -11,7 +11,7 @@
constraint sig_int_c {
esc_int_err == '1;
- esc_standalone_int_err dist {0 := 9, [1:'b1111] := 1};
+ esc_standalone_int_err dist {0 :/ 9, [1:'b1111] :/ 1};
}
endclass : alert_handler_ping_rsp_fail_vseq
diff --git a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv
index af24ff4..7c39b07 100644
--- a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv
+++ b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv
@@ -9,11 +9,6 @@
`uvm_object_new
- constraint clr_en_c {
- clr_en == 0;
- lock_bit_en == 0;
- }
-
function void pre_randomize();
this.enable_one_alert_c.constraint_mode(0);
endfunction
diff --git a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_sanity_vseq.sv b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_sanity_vseq.sv
index c97ddc3..e412ae6 100644
--- a/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_sanity_vseq.sv
+++ b/hw/ip/alert_handler/dv/env/seq_lib/alert_handler_sanity_vseq.sv
@@ -40,8 +40,8 @@
}
constraint clr_and_lock_en_c {
- clr_en dist {0 := 8, [1:'b1111] := 2};
- lock_bit_en dist {0 := 8, [1:'b1111] := 2};
+ clr_en dist {0 :/ 6, [1:'b1111] :/ 4};
+ lock_bit_en dist {0 :/ 6, [1:'b1111] :/ 4};
}
constraint enable_one_alert_c {
