[chip dv] Cleanup more Xcelium warnings
- stricter type coversions between int and enum
- fix single bit `delay` var (should have been int)
- Display test timeout ns setting
- Check the return value of uvm_hdl_read
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv
index b35599d..544aa4a 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_base_vseq.sv
@@ -147,14 +147,10 @@
// shorten alert ping timer enable wait time
virtual task check_lc_ctrl_broadcast(bit [LcBroadcastLast-1:0] bool_vector);
- string path;
- lc_ctrl_pkg::lc_tx_t curr_val;
-
foreach (lc_broadcast_paths[i]) begin
- path = {`DV_STRINGIFY(`LC_CTRL_HIER),
- ".", lc_broadcast_paths[i]};
- uvm_hdl_read(path, curr_val);
-
+ uvm_hdl_data_t curr_val;
+ string path = {`DV_STRINGIFY(`LC_CTRL_HIER), ".", lc_broadcast_paths[i]};
+ `DV_CHECK_FATAL(uvm_hdl_read(path, curr_val))
// if bool vector bit is 1, the probed value should be ON
// if bool vector bit is 0, the probed value should be OFF
if (bool_vector[i] ~^ (curr_val == lc_ctrl_pkg::On)) begin
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_common_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_common_vseq.sv
index 8938cd9..8fca4ff 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_common_vseq.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_common_vseq.sv
@@ -14,10 +14,10 @@
super.post_apply_reset(reset_kind);
for (int ram_idx = 0; ram_idx < cfg.num_ram_ret_tiles; ram_idx++) begin
- cfg.mem_bkdr_util_h[int'(RamRet0) + ram_idx].randomize_mem();
+ cfg.mem_bkdr_util_h[chip_mem_e'(RamRet0 + ram_idx)].randomize_mem();
end
for (int ram_idx = 0; ram_idx < cfg.num_ram_main_tiles; ram_idx++) begin
- cfg.mem_bkdr_util_h[int'(RamMain0) + ram_idx].randomize_mem();
+ cfg.mem_bkdr_util_h[chip_mem_e'(RamMain0 + ram_idx)].randomize_mem();
end
wait_rom_check_done();
endtask
@@ -52,4 +52,5 @@
$asserton(0, "tb.dut.u_ast.u_jitter_en_sync.PrimMubi4SyncCheckTransients0_A");
$asserton(0, "tb.dut.u_ast.u_jitter_en_sync.PrimMubi4SyncCheckTransients1_A");
endtask
+
endclass
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_alert_handler_escalation_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_alert_handler_escalation_vseq.sv
index c251b7b..46d44c1 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_alert_handler_escalation_vseq.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_alert_handler_escalation_vseq.sv
@@ -68,7 +68,7 @@
cfg.sw_test_timeout_ns);
prev_key = curr_key;
- uvm_hdl_read(keymgr_path, curr_key);
+ `DV_CHECK_FATAL(uvm_hdl_read(keymgr_path, curr_key))
if (curr_key == prev_key) begin
`uvm_fatal(`gfn, $sformatf("something is very wrong"))
end
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv
index f40f21e..c7a2806 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv
@@ -71,7 +71,7 @@
// as early portions of mask ROM will initialize it to the correct value.
// The randomization here is just to ensure we do not have x's in the memory.
for (int ram_idx = 0; ram_idx < cfg.num_ram_ret_tiles; ram_idx++) begin
- cfg.mem_bkdr_util_h[int'(RamRet0) + ram_idx].randomize_mem();
+ cfg.mem_bkdr_util_h[chip_mem_e'(RamRet0 + ram_idx)].randomize_mem();
end
`uvm_info(`gfn, "Initializing ROM", UVM_MEDIUM)
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_deep_sleep_all_reset_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_deep_sleep_all_reset_vseq.sv
index 4a3c41b..0392a18 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_deep_sleep_all_reset_vseq.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_deep_sleep_all_reset_vseq.sv
@@ -23,7 +23,7 @@
rand int cycles_after_trigger;
rand int cycles_till_reset;
- rand bit reset_delay;
+ rand int reset_delay;
int loop_num;
constraint cycles_after_trigger_c {cycles_after_trigger inside {[0 : 9]};}
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_random_sleep_all_reset_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_random_sleep_all_reset_vseq.sv
index 08af68a..492ec8c 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_random_sleep_all_reset_vseq.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_random_sleep_all_reset_vseq.sv
@@ -23,7 +23,7 @@
rand int cycles_after_trigger;
rand int cycles_till_reset;
- rand bit reset_delay;
+ rand int reset_delay;
int loop_num;
constraint cycles_after_trigger_c {cycles_after_trigger inside {[0 : 9]};}
diff --git a/hw/top_earlgrey/dv/tests/chip_base_test.sv b/hw/top_earlgrey/dv/tests/chip_base_test.sv
index 880cf6d..3c3e1ab 100644
--- a/hw/top_earlgrey/dv/tests/chip_base_test.sv
+++ b/hw/top_earlgrey/dv/tests/chip_base_test.sv
@@ -75,6 +75,7 @@
// Set the test timeout value to be sufficiently large.
test_timeout_ns = 50_000_000;
test_timeout_ns = `DV_MAX2(test_timeout_ns, 5 * cfg.sw_test_timeout_ns);
+ `uvm_info(`gfn, $sformatf("test_timeout_ns = %0d", test_timeout_ns), UVM_LOW)
endfunction : build_phase
endclass : chip_base_test
