[spi_device] Rename the interrupts
As discussed in #8585 spi_device HWIP's interrupts are revised to have
more descritive names. This helps the autogenerated SPI_DEVICE DIF to
be easier to understand.
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/hw/ip/spi_device/data/spi_device.hjson b/hw/ip/spi_device/data/spi_device.hjson
index 68ff937..3704ab6 100644
--- a/hw/ip/spi_device/data/spi_device.hjson
+++ b/hw/ip/spi_device/data/spi_device.hjson
@@ -25,13 +25,27 @@
}
]
interrupt_list: [
- { name: "rxf", desc: "RX SRAM FIFO Full" },
- { name: "rxlvl", desc: "RX SRAM FIFO is above the level" },
- { name: "txlvl", desc: "TX SRAM FIFO is under the level" },
- { name: "rxerr", desc: "SDI in FwMode has error" },
- { name: "rxoverflow", desc: "RX Async FIFO overflow" },
- { name: "txunderflow", desc: "TX Async FIFO underflow" },
- { name: "tpm_cmdaddr_notempty", desc: "TPM Command/Address buffer available" }
+ { name: "rx_full"
+ desc: "RX SRAM FIFO Full"
+ }
+ { name: "rx_watermark"
+ desc: "RX SRAM FIFO is above the level"
+ }
+ { name: "tx_watermark"
+ desc: "TX SRAM FIFO is under the level"
+ }
+ { name: "rx_error"
+ desc: "SDI in FwMode has error"
+ }
+ { name: "rx_overflow"
+ desc: "RX Async FIFO overflow"
+ }
+ { name: "tx_underflow"
+ desc: "TX Async FIFO underflow"
+ }
+ { name: "tpm_header_not_empty"
+ desc: "TPM Header(Command/Address) buffer available"
+ }
],
alert_list: [
{ name: "fatal_fault",
diff --git a/hw/ip/spi_device/dv/tb/tb.sv b/hw/ip/spi_device/dv/tb/tb.sv
index 0927d06..efcb4bb 100644
--- a/hw/ip/spi_device/dv/tb/tb.sv
+++ b/hw/ip/spi_device/dv/tb/tb.sv
@@ -59,12 +59,13 @@
.cio_tpm_csb_i (1'b 1 ), // TODO: Add TPM agent
- .intr_rxf_o (intr_rxf ),
- .intr_rxlvl_o (intr_rxlvl),
- .intr_txlvl_o (intr_txlvl),
- .intr_rxerr_o (intr_rxerr),
- .intr_rxoverflow_o (intr_rxoverflow),
- .intr_txunderflow_o(intr_txunderflow),
+ .intr_rx_full_o (intr_rxf ),
+ .intr_rx_watermark_o (intr_rxlvl),
+ .intr_tx_watermark_o (intr_txlvl),
+ .intr_rx_error_o (intr_rxerr),
+ .intr_rx_overflow_o (intr_rxoverflow),
+ .intr_tx_underflow_o (intr_txunderflow),
+ .intr_tpm_header_not_empty_o(),
.mbist_en_i (1'b0),
.scanmode_i (lc_ctrl_pkg::Off)
);
diff --git a/hw/ip/spi_device/rtl/spi_device.sv b/hw/ip/spi_device/rtl/spi_device.sv
index 1e0b73b..e0aef36 100644
--- a/hw/ip/spi_device/rtl/spi_device.sv
+++ b/hw/ip/spi_device/rtl/spi_device.sv
@@ -37,13 +37,13 @@
input spi_device_pkg::passthrough_rsp_t passthrough_i,
// Interrupts
- output logic intr_rxf_o, // RX FIFO Full
- output logic intr_rxlvl_o, // RX FIFO above level
- output logic intr_txlvl_o, // TX FIFO below level
- output logic intr_rxerr_o, // RX Frame error
- output logic intr_rxoverflow_o, // RX Async FIFO Overflow
- output logic intr_txunderflow_o, // TX Async FIFO Underflow
- output logic intr_tpm_cmdaddr_notempty_o, // TPM Command/Address buffer
+ output logic intr_rx_full_o, // RX FIFO Full
+ output logic intr_rx_watermark_o, // RX FIFO above level
+ output logic intr_tx_watermark_o, // TX FIFO below level
+ output logic intr_rx_error_o, // RX Frame error
+ output logic intr_rx_overflow_o, // RX Async FIFO Overflow
+ output logic intr_tx_underflow_o, // TX Async FIFO Underflow
+ output logic intr_tpm_header_not_empty_o, // TPM Command/Address buffer
// Memory configuration
input prim_ram_2p_pkg::ram_2p_cfg_t ram_cfg_i,
@@ -438,92 +438,92 @@
prim_intr_hw #(.Width(1)) u_intr_rxf (
.clk_i,
.rst_ni,
- .event_intr_i (intr_sram_rxf_full ),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rxf.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.rxf.q ),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.rxf.qe ),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.rxf.q ),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.rxf.de),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.rxf.d ),
- .intr_o (intr_rxf_o )
+ .event_intr_i (intr_sram_rxf_full ),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_full.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_full.q ),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_full.qe ),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_full.q ),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_full.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_full.d ),
+ .intr_o (intr_rx_full_o )
);
prim_intr_hw #(.Width(1)) u_intr_rxlvl (
.clk_i,
.rst_ni,
- .event_intr_i (intr_fwm_rxlvl ),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rxlvl.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.rxlvl.q ),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.rxlvl.qe ),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.rxlvl.q ),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.rxlvl.de),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.rxlvl.d ),
- .intr_o (intr_rxlvl_o )
+ .event_intr_i (intr_fwm_rxlvl ),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_watermark.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_watermark.q ),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_watermark.qe ),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_watermark.q ),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_watermark.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_watermark.d ),
+ .intr_o (intr_rx_watermark_o )
);
prim_intr_hw #(.Width(1)) u_intr_txlvl (
.clk_i,
.rst_ni,
- .event_intr_i (intr_fwm_txlvl ),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.txlvl.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.txlvl.q ),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.txlvl.qe ),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.txlvl.q ),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.txlvl.de),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.txlvl.d ),
- .intr_o (intr_txlvl_o )
+ .event_intr_i (intr_fwm_txlvl ),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_watermark.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.tx_watermark.q ),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.tx_watermark.qe ),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.tx_watermark.q ),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_watermark.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.tx_watermark.d ),
+ .intr_o (intr_tx_watermark_o )
);
prim_intr_hw #(.Width(1)) u_intr_rxerr (
.clk_i,
.rst_ni,
- .event_intr_i (intr_fwm_rxerr ),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rxerr.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.rxerr.q ),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.rxerr.qe ),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.rxerr.q ),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.rxerr.de),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.rxerr.d ),
- .intr_o (intr_rxerr_o )
+ .event_intr_i (intr_fwm_rxerr ),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_error.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_error.q ),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_error.qe ),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_error.q ),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_error.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_error.d ),
+ .intr_o (intr_rx_error_o )
);
prim_intr_hw #(.Width(1)) u_intr_rxoverflow (
.clk_i,
.rst_ni,
- .event_intr_i (intr_fwm_rxoverflow ),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rxoverflow.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.rxoverflow.q ),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.rxoverflow.qe ),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.rxoverflow.q ),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.rxoverflow.de),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.rxoverflow.d ),
- .intr_o (intr_rxoverflow_o )
+ .event_intr_i (intr_fwm_rxoverflow ),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_overflow.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_overflow.q ),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_overflow.qe ),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_overflow.q ),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_overflow.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_overflow.d ),
+ .intr_o (intr_rx_overflow_o )
);
prim_intr_hw #(.Width(1)) u_intr_txunderflow (
.clk_i,
.rst_ni,
- .event_intr_i (intr_fwm_txunderflow ),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.txunderflow.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.txunderflow.q ),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.txunderflow.qe ),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.txunderflow.q ),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.txunderflow.de),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.txunderflow.d ),
- .intr_o (intr_txunderflow_o )
+ .event_intr_i (intr_fwm_txunderflow ),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_underflow.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.tx_underflow.q ),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.tx_underflow.qe ),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.tx_underflow.q ),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_underflow.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.tx_underflow.d ),
+ .intr_o (intr_tx_underflow_o )
);
prim_intr_hw #(.Width(1)) u_intr_tpm_cmdaddr_notempty (
.clk_i,
.rst_ni,
.event_intr_i (intr_tpm_cmdaddr_notempty ),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tpm_cmdaddr_notempty.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.tpm_cmdaddr_notempty.q ),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.tpm_cmdaddr_notempty.qe ),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.tpm_cmdaddr_notempty.q ),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.tpm_cmdaddr_notempty.d ),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.tpm_cmdaddr_notempty.de),
- .intr_o (intr_tpm_cmdaddr_notempty_o )
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tpm_header_not_empty.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.tpm_header_not_empty.q ),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.tpm_header_not_empty.qe ),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.tpm_header_not_empty.q ),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.tpm_header_not_empty.d ),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.tpm_header_not_empty.de),
+ .intr_o (intr_tpm_header_not_empty_o )
);
// SPI Flash commands registers
@@ -1642,12 +1642,13 @@
`ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_i, 0)
`ASSERT_KNOWN(CioSdoEnOKnown, cio_sd_en_o)
- `ASSERT_KNOWN(IntrRxfOKnown, intr_rxf_o )
- `ASSERT_KNOWN(IntrRxlvlOKnown, intr_rxlvl_o )
- `ASSERT_KNOWN(IntrTxlvlOKnown, intr_txlvl_o )
- `ASSERT_KNOWN(IntrRxerrOKnown, intr_rxerr_o )
- `ASSERT_KNOWN(IntrRxoverflowOKnown, intr_rxoverflow_o )
- `ASSERT_KNOWN(IntrTxunderflowOKnown, intr_txunderflow_o)
+ `ASSERT_KNOWN(IntrRxfOKnown, intr_rx_full_o )
+ `ASSERT_KNOWN(IntrRxlvlOKnown, intr_rx_watermark_o)
+ `ASSERT_KNOWN(IntrTxlvlOKnown, intr_tx_watermark_o)
+ `ASSERT_KNOWN(IntrRxerrOKnown, intr_rx_error_o )
+ `ASSERT_KNOWN(IntrRxoverflowOKnown, intr_rx_overflow_o )
+ `ASSERT_KNOWN(IntrTxunderflowOKnown, intr_tx_underflow_o)
+ `ASSERT_KNOWN(IntrTpmHeaderNotEmptyOKnown, intr_tpm_header_not_empty_o)
`ASSERT_KNOWN(AlertKnownO_A, alert_tx_o)
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv b/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
index c0be998..ccc5a03 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
@@ -22,80 +22,80 @@
typedef struct packed {
struct packed {
logic q;
- } rxf;
+ } rx_full;
struct packed {
logic q;
- } rxlvl;
+ } rx_watermark;
struct packed {
logic q;
- } txlvl;
+ } tx_watermark;
struct packed {
logic q;
- } rxerr;
+ } rx_error;
struct packed {
logic q;
- } rxoverflow;
+ } rx_overflow;
struct packed {
logic q;
- } txunderflow;
+ } tx_underflow;
struct packed {
logic q;
- } tpm_cmdaddr_notempty;
+ } tpm_header_not_empty;
} spi_device_reg2hw_intr_state_reg_t;
typedef struct packed {
struct packed {
logic q;
- } rxf;
+ } rx_full;
struct packed {
logic q;
- } rxlvl;
+ } rx_watermark;
struct packed {
logic q;
- } txlvl;
+ } tx_watermark;
struct packed {
logic q;
- } rxerr;
+ } rx_error;
struct packed {
logic q;
- } rxoverflow;
+ } rx_overflow;
struct packed {
logic q;
- } txunderflow;
+ } tx_underflow;
struct packed {
logic q;
- } tpm_cmdaddr_notempty;
+ } tpm_header_not_empty;
} spi_device_reg2hw_intr_enable_reg_t;
typedef struct packed {
struct packed {
logic q;
logic qe;
- } rxf;
+ } rx_full;
struct packed {
logic q;
logic qe;
- } rxlvl;
+ } rx_watermark;
struct packed {
logic q;
logic qe;
- } txlvl;
+ } tx_watermark;
struct packed {
logic q;
logic qe;
- } rxerr;
+ } rx_error;
struct packed {
logic q;
logic qe;
- } rxoverflow;
+ } rx_overflow;
struct packed {
logic q;
logic qe;
- } txunderflow;
+ } tx_underflow;
struct packed {
logic q;
logic qe;
- } tpm_cmdaddr_notempty;
+ } tpm_header_not_empty;
} spi_device_reg2hw_intr_test_reg_t;
typedef struct packed {
@@ -353,31 +353,31 @@
struct packed {
logic d;
logic de;
- } rxf;
+ } rx_full;
struct packed {
logic d;
logic de;
- } rxlvl;
+ } rx_watermark;
struct packed {
logic d;
logic de;
- } txlvl;
+ } tx_watermark;
struct packed {
logic d;
logic de;
- } rxerr;
+ } rx_error;
struct packed {
logic d;
logic de;
- } rxoverflow;
+ } rx_overflow;
struct packed {
logic d;
logic de;
- } txunderflow;
+ } tx_underflow;
struct packed {
logic d;
logic de;
- } tpm_cmdaddr_notempty;
+ } tpm_header_not_empty;
} spi_device_hw2reg_intr_state_reg_t;
typedef struct packed {
@@ -644,13 +644,13 @@
// Reset values for hwext registers and their fields
parameter logic [6:0] SPI_DEVICE_INTR_TEST_RESVAL = 7'h 0;
- parameter logic [0:0] SPI_DEVICE_INTR_TEST_RXF_RESVAL = 1'h 0;
- parameter logic [0:0] SPI_DEVICE_INTR_TEST_RXLVL_RESVAL = 1'h 0;
- parameter logic [0:0] SPI_DEVICE_INTR_TEST_TXLVL_RESVAL = 1'h 0;
- parameter logic [0:0] SPI_DEVICE_INTR_TEST_RXERR_RESVAL = 1'h 0;
- parameter logic [0:0] SPI_DEVICE_INTR_TEST_RXOVERFLOW_RESVAL = 1'h 0;
- parameter logic [0:0] SPI_DEVICE_INTR_TEST_TXUNDERFLOW_RESVAL = 1'h 0;
- parameter logic [0:0] SPI_DEVICE_INTR_TEST_TPM_CMDADDR_NOTEMPTY_RESVAL = 1'h 0;
+ parameter logic [0:0] SPI_DEVICE_INTR_TEST_RX_FULL_RESVAL = 1'h 0;
+ parameter logic [0:0] SPI_DEVICE_INTR_TEST_RX_WATERMARK_RESVAL = 1'h 0;
+ parameter logic [0:0] SPI_DEVICE_INTR_TEST_TX_WATERMARK_RESVAL = 1'h 0;
+ parameter logic [0:0] SPI_DEVICE_INTR_TEST_RX_ERROR_RESVAL = 1'h 0;
+ parameter logic [0:0] SPI_DEVICE_INTR_TEST_RX_OVERFLOW_RESVAL = 1'h 0;
+ parameter logic [0:0] SPI_DEVICE_INTR_TEST_TX_UNDERFLOW_RESVAL = 1'h 0;
+ parameter logic [0:0] SPI_DEVICE_INTR_TEST_TPM_HEADER_NOT_EMPTY_RESVAL = 1'h 0;
parameter logic [0:0] SPI_DEVICE_ALERT_TEST_RESVAL = 1'h 0;
parameter logic [0:0] SPI_DEVICE_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
parameter logic [23:0] SPI_DEVICE_ASYNC_FIFO_LEVEL_RESVAL = 24'h 0;
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_top.sv b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
index 890cfbf..298f22c 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_top.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
@@ -157,43 +157,43 @@
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
logic intr_state_we;
- logic intr_state_rxf_qs;
- logic intr_state_rxf_wd;
- logic intr_state_rxlvl_qs;
- logic intr_state_rxlvl_wd;
- logic intr_state_txlvl_qs;
- logic intr_state_txlvl_wd;
- logic intr_state_rxerr_qs;
- logic intr_state_rxerr_wd;
- logic intr_state_rxoverflow_qs;
- logic intr_state_rxoverflow_wd;
- logic intr_state_txunderflow_qs;
- logic intr_state_txunderflow_wd;
- logic intr_state_tpm_cmdaddr_notempty_qs;
- logic intr_state_tpm_cmdaddr_notempty_wd;
+ logic intr_state_rx_full_qs;
+ logic intr_state_rx_full_wd;
+ logic intr_state_rx_watermark_qs;
+ logic intr_state_rx_watermark_wd;
+ logic intr_state_tx_watermark_qs;
+ logic intr_state_tx_watermark_wd;
+ logic intr_state_rx_error_qs;
+ logic intr_state_rx_error_wd;
+ logic intr_state_rx_overflow_qs;
+ logic intr_state_rx_overflow_wd;
+ logic intr_state_tx_underflow_qs;
+ logic intr_state_tx_underflow_wd;
+ logic intr_state_tpm_header_not_empty_qs;
+ logic intr_state_tpm_header_not_empty_wd;
logic intr_enable_we;
- logic intr_enable_rxf_qs;
- logic intr_enable_rxf_wd;
- logic intr_enable_rxlvl_qs;
- logic intr_enable_rxlvl_wd;
- logic intr_enable_txlvl_qs;
- logic intr_enable_txlvl_wd;
- logic intr_enable_rxerr_qs;
- logic intr_enable_rxerr_wd;
- logic intr_enable_rxoverflow_qs;
- logic intr_enable_rxoverflow_wd;
- logic intr_enable_txunderflow_qs;
- logic intr_enable_txunderflow_wd;
- logic intr_enable_tpm_cmdaddr_notempty_qs;
- logic intr_enable_tpm_cmdaddr_notempty_wd;
+ logic intr_enable_rx_full_qs;
+ logic intr_enable_rx_full_wd;
+ logic intr_enable_rx_watermark_qs;
+ logic intr_enable_rx_watermark_wd;
+ logic intr_enable_tx_watermark_qs;
+ logic intr_enable_tx_watermark_wd;
+ logic intr_enable_rx_error_qs;
+ logic intr_enable_rx_error_wd;
+ logic intr_enable_rx_overflow_qs;
+ logic intr_enable_rx_overflow_wd;
+ logic intr_enable_tx_underflow_qs;
+ logic intr_enable_tx_underflow_wd;
+ logic intr_enable_tpm_header_not_empty_qs;
+ logic intr_enable_tpm_header_not_empty_wd;
logic intr_test_we;
- logic intr_test_rxf_wd;
- logic intr_test_rxlvl_wd;
- logic intr_test_txlvl_wd;
- logic intr_test_rxerr_wd;
- logic intr_test_rxoverflow_wd;
- logic intr_test_txunderflow_wd;
- logic intr_test_tpm_cmdaddr_notempty_wd;
+ logic intr_test_rx_full_wd;
+ logic intr_test_rx_watermark_wd;
+ logic intr_test_tx_watermark_wd;
+ logic intr_test_rx_error_wd;
+ logic intr_test_rx_overflow_wd;
+ logic intr_test_tx_underflow_wd;
+ logic intr_test_tpm_header_not_empty_wd;
logic alert_test_we;
logic alert_test_wd;
logic control_we;
@@ -1424,195 +1424,195 @@
// Register instances
// R[intr_state]: V(False)
- // F[rxf]: 0:0
+ // F[rx_full]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_intr_state_rxf (
+ ) u_intr_state_rx_full (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
- .wd (intr_state_rxf_wd),
+ .wd (intr_state_rx_full_wd),
// from internal hardware
- .de (hw2reg.intr_state.rxf.de),
- .d (hw2reg.intr_state.rxf.d),
+ .de (hw2reg.intr_state.rx_full.de),
+ .d (hw2reg.intr_state.rx_full.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rxf.q),
+ .q (reg2hw.intr_state.rx_full.q),
// to register interface (read)
- .qs (intr_state_rxf_qs)
+ .qs (intr_state_rx_full_qs)
);
- // F[rxlvl]: 1:1
+ // F[rx_watermark]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_intr_state_rxlvl (
+ ) u_intr_state_rx_watermark (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
- .wd (intr_state_rxlvl_wd),
+ .wd (intr_state_rx_watermark_wd),
// from internal hardware
- .de (hw2reg.intr_state.rxlvl.de),
- .d (hw2reg.intr_state.rxlvl.d),
+ .de (hw2reg.intr_state.rx_watermark.de),
+ .d (hw2reg.intr_state.rx_watermark.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rxlvl.q),
+ .q (reg2hw.intr_state.rx_watermark.q),
// to register interface (read)
- .qs (intr_state_rxlvl_qs)
+ .qs (intr_state_rx_watermark_qs)
);
- // F[txlvl]: 2:2
+ // F[tx_watermark]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_intr_state_txlvl (
+ ) u_intr_state_tx_watermark (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
- .wd (intr_state_txlvl_wd),
+ .wd (intr_state_tx_watermark_wd),
// from internal hardware
- .de (hw2reg.intr_state.txlvl.de),
- .d (hw2reg.intr_state.txlvl.d),
+ .de (hw2reg.intr_state.tx_watermark.de),
+ .d (hw2reg.intr_state.tx_watermark.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.txlvl.q),
+ .q (reg2hw.intr_state.tx_watermark.q),
// to register interface (read)
- .qs (intr_state_txlvl_qs)
+ .qs (intr_state_tx_watermark_qs)
);
- // F[rxerr]: 3:3
+ // F[rx_error]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_intr_state_rxerr (
+ ) u_intr_state_rx_error (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
- .wd (intr_state_rxerr_wd),
+ .wd (intr_state_rx_error_wd),
// from internal hardware
- .de (hw2reg.intr_state.rxerr.de),
- .d (hw2reg.intr_state.rxerr.d),
+ .de (hw2reg.intr_state.rx_error.de),
+ .d (hw2reg.intr_state.rx_error.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rxerr.q),
+ .q (reg2hw.intr_state.rx_error.q),
// to register interface (read)
- .qs (intr_state_rxerr_qs)
+ .qs (intr_state_rx_error_qs)
);
- // F[rxoverflow]: 4:4
+ // F[rx_overflow]: 4:4
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_intr_state_rxoverflow (
+ ) u_intr_state_rx_overflow (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
- .wd (intr_state_rxoverflow_wd),
+ .wd (intr_state_rx_overflow_wd),
// from internal hardware
- .de (hw2reg.intr_state.rxoverflow.de),
- .d (hw2reg.intr_state.rxoverflow.d),
+ .de (hw2reg.intr_state.rx_overflow.de),
+ .d (hw2reg.intr_state.rx_overflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rxoverflow.q),
+ .q (reg2hw.intr_state.rx_overflow.q),
// to register interface (read)
- .qs (intr_state_rxoverflow_qs)
+ .qs (intr_state_rx_overflow_qs)
);
- // F[txunderflow]: 5:5
+ // F[tx_underflow]: 5:5
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_intr_state_txunderflow (
+ ) u_intr_state_tx_underflow (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
- .wd (intr_state_txunderflow_wd),
+ .wd (intr_state_tx_underflow_wd),
// from internal hardware
- .de (hw2reg.intr_state.txunderflow.de),
- .d (hw2reg.intr_state.txunderflow.d),
+ .de (hw2reg.intr_state.tx_underflow.de),
+ .d (hw2reg.intr_state.tx_underflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.txunderflow.q),
+ .q (reg2hw.intr_state.tx_underflow.q),
// to register interface (read)
- .qs (intr_state_txunderflow_qs)
+ .qs (intr_state_tx_underflow_qs)
);
- // F[tpm_cmdaddr_notempty]: 6:6
+ // F[tpm_header_not_empty]: 6:6
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_intr_state_tpm_cmdaddr_notempty (
+ ) u_intr_state_tpm_header_not_empty (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
- .wd (intr_state_tpm_cmdaddr_notempty_wd),
+ .wd (intr_state_tpm_header_not_empty_wd),
// from internal hardware
- .de (hw2reg.intr_state.tpm_cmdaddr_notempty.de),
- .d (hw2reg.intr_state.tpm_cmdaddr_notempty.d),
+ .de (hw2reg.intr_state.tpm_header_not_empty.de),
+ .d (hw2reg.intr_state.tpm_header_not_empty.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.tpm_cmdaddr_notempty.q),
+ .q (reg2hw.intr_state.tpm_header_not_empty.q),
// to register interface (read)
- .qs (intr_state_tpm_cmdaddr_notempty_qs)
+ .qs (intr_state_tpm_header_not_empty_qs)
);
// R[intr_enable]: V(False)
- // F[rxf]: 0:0
+ // F[rx_full]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_intr_enable_rxf (
+ ) u_intr_enable_rx_full (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
- .wd (intr_enable_rxf_wd),
+ .wd (intr_enable_rx_full_wd),
// from internal hardware
.de (1'b0),
@@ -1620,24 +1620,24 @@
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rxf.q),
+ .q (reg2hw.intr_enable.rx_full.q),
// to register interface (read)
- .qs (intr_enable_rxf_qs)
+ .qs (intr_enable_rx_full_qs)
);
- // F[rxlvl]: 1:1
+ // F[rx_watermark]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_intr_enable_rxlvl (
+ ) u_intr_enable_rx_watermark (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
- .wd (intr_enable_rxlvl_wd),
+ .wd (intr_enable_rx_watermark_wd),
// from internal hardware
.de (1'b0),
@@ -1645,24 +1645,24 @@
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rxlvl.q),
+ .q (reg2hw.intr_enable.rx_watermark.q),
// to register interface (read)
- .qs (intr_enable_rxlvl_qs)
+ .qs (intr_enable_rx_watermark_qs)
);
- // F[txlvl]: 2:2
+ // F[tx_watermark]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_intr_enable_txlvl (
+ ) u_intr_enable_tx_watermark (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
- .wd (intr_enable_txlvl_wd),
+ .wd (intr_enable_tx_watermark_wd),
// from internal hardware
.de (1'b0),
@@ -1670,24 +1670,24 @@
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.txlvl.q),
+ .q (reg2hw.intr_enable.tx_watermark.q),
// to register interface (read)
- .qs (intr_enable_txlvl_qs)
+ .qs (intr_enable_tx_watermark_qs)
);
- // F[rxerr]: 3:3
+ // F[rx_error]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_intr_enable_rxerr (
+ ) u_intr_enable_rx_error (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
- .wd (intr_enable_rxerr_wd),
+ .wd (intr_enable_rx_error_wd),
// from internal hardware
.de (1'b0),
@@ -1695,24 +1695,24 @@
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rxerr.q),
+ .q (reg2hw.intr_enable.rx_error.q),
// to register interface (read)
- .qs (intr_enable_rxerr_qs)
+ .qs (intr_enable_rx_error_qs)
);
- // F[rxoverflow]: 4:4
+ // F[rx_overflow]: 4:4
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_intr_enable_rxoverflow (
+ ) u_intr_enable_rx_overflow (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
- .wd (intr_enable_rxoverflow_wd),
+ .wd (intr_enable_rx_overflow_wd),
// from internal hardware
.de (1'b0),
@@ -1720,24 +1720,24 @@
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rxoverflow.q),
+ .q (reg2hw.intr_enable.rx_overflow.q),
// to register interface (read)
- .qs (intr_enable_rxoverflow_qs)
+ .qs (intr_enable_rx_overflow_qs)
);
- // F[txunderflow]: 5:5
+ // F[tx_underflow]: 5:5
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_intr_enable_txunderflow (
+ ) u_intr_enable_tx_underflow (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
- .wd (intr_enable_txunderflow_wd),
+ .wd (intr_enable_tx_underflow_wd),
// from internal hardware
.de (1'b0),
@@ -1745,24 +1745,24 @@
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.txunderflow.q),
+ .q (reg2hw.intr_enable.tx_underflow.q),
// to register interface (read)
- .qs (intr_enable_txunderflow_qs)
+ .qs (intr_enable_tx_underflow_qs)
);
- // F[tpm_cmdaddr_notempty]: 6:6
+ // F[tpm_header_not_empty]: 6:6
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_intr_enable_tpm_cmdaddr_notempty (
+ ) u_intr_enable_tpm_header_not_empty (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
- .wd (intr_enable_tpm_cmdaddr_notempty_wd),
+ .wd (intr_enable_tpm_header_not_empty_wd),
// from internal hardware
.de (1'b0),
@@ -1770,109 +1770,109 @@
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.tpm_cmdaddr_notempty.q),
+ .q (reg2hw.intr_enable.tpm_header_not_empty.q),
// to register interface (read)
- .qs (intr_enable_tpm_cmdaddr_notempty_qs)
+ .qs (intr_enable_tpm_header_not_empty_qs)
);
// R[intr_test]: V(True)
- // F[rxf]: 0:0
+ // F[rx_full]: 0:0
prim_subreg_ext #(
.DW (1)
- ) u_intr_test_rxf (
+ ) u_intr_test_rx_full (
.re (1'b0),
.we (intr_test_we),
- .wd (intr_test_rxf_wd),
+ .wd (intr_test_rx_full_wd),
.d ('0),
.qre (),
- .qe (reg2hw.intr_test.rxf.qe),
- .q (reg2hw.intr_test.rxf.q),
+ .qe (reg2hw.intr_test.rx_full.qe),
+ .q (reg2hw.intr_test.rx_full.q),
.qs ()
);
- // F[rxlvl]: 1:1
+ // F[rx_watermark]: 1:1
prim_subreg_ext #(
.DW (1)
- ) u_intr_test_rxlvl (
+ ) u_intr_test_rx_watermark (
.re (1'b0),
.we (intr_test_we),
- .wd (intr_test_rxlvl_wd),
+ .wd (intr_test_rx_watermark_wd),
.d ('0),
.qre (),
- .qe (reg2hw.intr_test.rxlvl.qe),
- .q (reg2hw.intr_test.rxlvl.q),
+ .qe (reg2hw.intr_test.rx_watermark.qe),
+ .q (reg2hw.intr_test.rx_watermark.q),
.qs ()
);
- // F[txlvl]: 2:2
+ // F[tx_watermark]: 2:2
prim_subreg_ext #(
.DW (1)
- ) u_intr_test_txlvl (
+ ) u_intr_test_tx_watermark (
.re (1'b0),
.we (intr_test_we),
- .wd (intr_test_txlvl_wd),
+ .wd (intr_test_tx_watermark_wd),
.d ('0),
.qre (),
- .qe (reg2hw.intr_test.txlvl.qe),
- .q (reg2hw.intr_test.txlvl.q),
+ .qe (reg2hw.intr_test.tx_watermark.qe),
+ .q (reg2hw.intr_test.tx_watermark.q),
.qs ()
);
- // F[rxerr]: 3:3
+ // F[rx_error]: 3:3
prim_subreg_ext #(
.DW (1)
- ) u_intr_test_rxerr (
+ ) u_intr_test_rx_error (
.re (1'b0),
.we (intr_test_we),
- .wd (intr_test_rxerr_wd),
+ .wd (intr_test_rx_error_wd),
.d ('0),
.qre (),
- .qe (reg2hw.intr_test.rxerr.qe),
- .q (reg2hw.intr_test.rxerr.q),
+ .qe (reg2hw.intr_test.rx_error.qe),
+ .q (reg2hw.intr_test.rx_error.q),
.qs ()
);
- // F[rxoverflow]: 4:4
+ // F[rx_overflow]: 4:4
prim_subreg_ext #(
.DW (1)
- ) u_intr_test_rxoverflow (
+ ) u_intr_test_rx_overflow (
.re (1'b0),
.we (intr_test_we),
- .wd (intr_test_rxoverflow_wd),
+ .wd (intr_test_rx_overflow_wd),
.d ('0),
.qre (),
- .qe (reg2hw.intr_test.rxoverflow.qe),
- .q (reg2hw.intr_test.rxoverflow.q),
+ .qe (reg2hw.intr_test.rx_overflow.qe),
+ .q (reg2hw.intr_test.rx_overflow.q),
.qs ()
);
- // F[txunderflow]: 5:5
+ // F[tx_underflow]: 5:5
prim_subreg_ext #(
.DW (1)
- ) u_intr_test_txunderflow (
+ ) u_intr_test_tx_underflow (
.re (1'b0),
.we (intr_test_we),
- .wd (intr_test_txunderflow_wd),
+ .wd (intr_test_tx_underflow_wd),
.d ('0),
.qre (),
- .qe (reg2hw.intr_test.txunderflow.qe),
- .q (reg2hw.intr_test.txunderflow.q),
+ .qe (reg2hw.intr_test.tx_underflow.qe),
+ .q (reg2hw.intr_test.tx_underflow.q),
.qs ()
);
- // F[tpm_cmdaddr_notempty]: 6:6
+ // F[tpm_header_not_empty]: 6:6
prim_subreg_ext #(
.DW (1)
- ) u_intr_test_tpm_cmdaddr_notempty (
+ ) u_intr_test_tpm_header_not_empty (
.re (1'b0),
.we (intr_test_we),
- .wd (intr_test_tpm_cmdaddr_notempty_wd),
+ .wd (intr_test_tpm_header_not_empty_wd),
.d ('0),
.qre (),
- .qe (reg2hw.intr_test.tpm_cmdaddr_notempty.qe),
- .q (reg2hw.intr_test.tpm_cmdaddr_notempty.q),
+ .qe (reg2hw.intr_test.tpm_header_not_empty.qe),
+ .q (reg2hw.intr_test.tpm_header_not_empty.q),
.qs ()
);
@@ -16884,49 +16884,49 @@
end
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
- assign intr_state_rxf_wd = reg_wdata[0];
+ assign intr_state_rx_full_wd = reg_wdata[0];
- assign intr_state_rxlvl_wd = reg_wdata[1];
+ assign intr_state_rx_watermark_wd = reg_wdata[1];
- assign intr_state_txlvl_wd = reg_wdata[2];
+ assign intr_state_tx_watermark_wd = reg_wdata[2];
- assign intr_state_rxerr_wd = reg_wdata[3];
+ assign intr_state_rx_error_wd = reg_wdata[3];
- assign intr_state_rxoverflow_wd = reg_wdata[4];
+ assign intr_state_rx_overflow_wd = reg_wdata[4];
- assign intr_state_txunderflow_wd = reg_wdata[5];
+ assign intr_state_tx_underflow_wd = reg_wdata[5];
- assign intr_state_tpm_cmdaddr_notempty_wd = reg_wdata[6];
+ assign intr_state_tpm_header_not_empty_wd = reg_wdata[6];
assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
- assign intr_enable_rxf_wd = reg_wdata[0];
+ assign intr_enable_rx_full_wd = reg_wdata[0];
- assign intr_enable_rxlvl_wd = reg_wdata[1];
+ assign intr_enable_rx_watermark_wd = reg_wdata[1];
- assign intr_enable_txlvl_wd = reg_wdata[2];
+ assign intr_enable_tx_watermark_wd = reg_wdata[2];
- assign intr_enable_rxerr_wd = reg_wdata[3];
+ assign intr_enable_rx_error_wd = reg_wdata[3];
- assign intr_enable_rxoverflow_wd = reg_wdata[4];
+ assign intr_enable_rx_overflow_wd = reg_wdata[4];
- assign intr_enable_txunderflow_wd = reg_wdata[5];
+ assign intr_enable_tx_underflow_wd = reg_wdata[5];
- assign intr_enable_tpm_cmdaddr_notempty_wd = reg_wdata[6];
+ assign intr_enable_tpm_header_not_empty_wd = reg_wdata[6];
assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
- assign intr_test_rxf_wd = reg_wdata[0];
+ assign intr_test_rx_full_wd = reg_wdata[0];
- assign intr_test_rxlvl_wd = reg_wdata[1];
+ assign intr_test_rx_watermark_wd = reg_wdata[1];
- assign intr_test_txlvl_wd = reg_wdata[2];
+ assign intr_test_tx_watermark_wd = reg_wdata[2];
- assign intr_test_rxerr_wd = reg_wdata[3];
+ assign intr_test_rx_error_wd = reg_wdata[3];
- assign intr_test_rxoverflow_wd = reg_wdata[4];
+ assign intr_test_rx_overflow_wd = reg_wdata[4];
- assign intr_test_txunderflow_wd = reg_wdata[5];
+ assign intr_test_tx_underflow_wd = reg_wdata[5];
- assign intr_test_tpm_cmdaddr_notempty_wd = reg_wdata[6];
+ assign intr_test_tpm_header_not_empty_wd = reg_wdata[6];
assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
assign alert_test_wd = reg_wdata[0];
@@ -18134,23 +18134,23 @@
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
- reg_rdata_next[0] = intr_state_rxf_qs;
- reg_rdata_next[1] = intr_state_rxlvl_qs;
- reg_rdata_next[2] = intr_state_txlvl_qs;
- reg_rdata_next[3] = intr_state_rxerr_qs;
- reg_rdata_next[4] = intr_state_rxoverflow_qs;
- reg_rdata_next[5] = intr_state_txunderflow_qs;
- reg_rdata_next[6] = intr_state_tpm_cmdaddr_notempty_qs;
+ reg_rdata_next[0] = intr_state_rx_full_qs;
+ reg_rdata_next[1] = intr_state_rx_watermark_qs;
+ reg_rdata_next[2] = intr_state_tx_watermark_qs;
+ reg_rdata_next[3] = intr_state_rx_error_qs;
+ reg_rdata_next[4] = intr_state_rx_overflow_qs;
+ reg_rdata_next[5] = intr_state_tx_underflow_qs;
+ reg_rdata_next[6] = intr_state_tpm_header_not_empty_qs;
end
addr_hit[1]: begin
- reg_rdata_next[0] = intr_enable_rxf_qs;
- reg_rdata_next[1] = intr_enable_rxlvl_qs;
- reg_rdata_next[2] = intr_enable_txlvl_qs;
- reg_rdata_next[3] = intr_enable_rxerr_qs;
- reg_rdata_next[4] = intr_enable_rxoverflow_qs;
- reg_rdata_next[5] = intr_enable_txunderflow_qs;
- reg_rdata_next[6] = intr_enable_tpm_cmdaddr_notempty_qs;
+ reg_rdata_next[0] = intr_enable_rx_full_qs;
+ reg_rdata_next[1] = intr_enable_rx_watermark_qs;
+ reg_rdata_next[2] = intr_enable_tx_watermark_qs;
+ reg_rdata_next[3] = intr_enable_rx_error_qs;
+ reg_rdata_next[4] = intr_enable_rx_overflow_qs;
+ reg_rdata_next[5] = intr_enable_tx_underflow_qs;
+ reg_rdata_next[6] = intr_enable_tpm_header_not_empty_qs;
end
addr_hit[2]: begin
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index c0901b3..73311a8 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -12373,43 +12373,43 @@
module_name: gpio
}
{
- name: spi_device_rxf
+ name: spi_device_rx_full
width: 1
type: interrupt
module_name: spi_device
}
{
- name: spi_device_rxlvl
+ name: spi_device_rx_watermark
width: 1
type: interrupt
module_name: spi_device
}
{
- name: spi_device_txlvl
+ name: spi_device_tx_watermark
width: 1
type: interrupt
module_name: spi_device
}
{
- name: spi_device_rxerr
+ name: spi_device_rx_error
width: 1
type: interrupt
module_name: spi_device
}
{
- name: spi_device_rxoverflow
+ name: spi_device_rx_overflow
width: 1
type: interrupt
module_name: spi_device
}
{
- name: spi_device_txunderflow
+ name: spi_device_tx_underflow
width: 1
type: interrupt
module_name: spi_device
}
{
- name: spi_device_tpm_cmdaddr_notempty
+ name: spi_device_tpm_header_not_empty
width: 1
type: interrupt
module_name: spi_device
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 3b181ec..7a669d9 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -391,13 +391,13 @@
logic intr_uart3_rx_timeout;
logic intr_uart3_rx_parity_err;
logic [31:0] intr_gpio_gpio;
- logic intr_spi_device_rxf;
- logic intr_spi_device_rxlvl;
- logic intr_spi_device_txlvl;
- logic intr_spi_device_rxerr;
- logic intr_spi_device_rxoverflow;
- logic intr_spi_device_txunderflow;
- logic intr_spi_device_tpm_cmdaddr_notempty;
+ logic intr_spi_device_rx_full;
+ logic intr_spi_device_rx_watermark;
+ logic intr_spi_device_tx_watermark;
+ logic intr_spi_device_rx_error;
+ logic intr_spi_device_rx_overflow;
+ logic intr_spi_device_tx_underflow;
+ logic intr_spi_device_tpm_header_not_empty;
logic intr_spi_host0_error;
logic intr_spi_host0_spi_event;
logic intr_spi_host1_error;
@@ -1036,13 +1036,13 @@
.cio_sd_en_o (cio_spi_device_sd_en_d2p),
// Interrupt
- .intr_rxf_o (intr_spi_device_rxf),
- .intr_rxlvl_o (intr_spi_device_rxlvl),
- .intr_txlvl_o (intr_spi_device_txlvl),
- .intr_rxerr_o (intr_spi_device_rxerr),
- .intr_rxoverflow_o (intr_spi_device_rxoverflow),
- .intr_txunderflow_o (intr_spi_device_txunderflow),
- .intr_tpm_cmdaddr_notempty_o (intr_spi_device_tpm_cmdaddr_notempty),
+ .intr_rx_full_o (intr_spi_device_rx_full),
+ .intr_rx_watermark_o (intr_spi_device_rx_watermark),
+ .intr_tx_watermark_o (intr_spi_device_tx_watermark),
+ .intr_rx_error_o (intr_spi_device_rx_error),
+ .intr_rx_overflow_o (intr_spi_device_rx_overflow),
+ .intr_tx_underflow_o (intr_spi_device_tx_underflow),
+ .intr_tpm_header_not_empty_o (intr_spi_device_tpm_header_not_empty),
// [5]: fatal_fault
.alert_tx_o ( alert_tx[5:5] ),
.alert_rx_i ( alert_rx[5:5] ),
@@ -2522,13 +2522,13 @@
intr_spi_host1_error, // IDs [74 +: 1]
intr_spi_host0_spi_event, // IDs [73 +: 1]
intr_spi_host0_error, // IDs [72 +: 1]
- intr_spi_device_tpm_cmdaddr_notempty, // IDs [71 +: 1]
- intr_spi_device_txunderflow, // IDs [70 +: 1]
- intr_spi_device_rxoverflow, // IDs [69 +: 1]
- intr_spi_device_rxerr, // IDs [68 +: 1]
- intr_spi_device_txlvl, // IDs [67 +: 1]
- intr_spi_device_rxlvl, // IDs [66 +: 1]
- intr_spi_device_rxf, // IDs [65 +: 1]
+ intr_spi_device_tpm_header_not_empty, // IDs [71 +: 1]
+ intr_spi_device_tx_underflow, // IDs [70 +: 1]
+ intr_spi_device_rx_overflow, // IDs [69 +: 1]
+ intr_spi_device_rx_error, // IDs [68 +: 1]
+ intr_spi_device_tx_watermark, // IDs [67 +: 1]
+ intr_spi_device_rx_watermark, // IDs [66 +: 1]
+ intr_spi_device_rx_full, // IDs [65 +: 1]
intr_gpio_gpio, // IDs [33 +: 32]
intr_uart3_rx_parity_err, // IDs [32 +: 1]
intr_uart3_rx_timeout, // IDs [31 +: 1]
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index ee7cb98..2ddfed4 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -77,13 +77,13 @@
[kTopEarlgreyPlicIrqIdGpioGpio29] = kTopEarlgreyPlicPeripheralGpio,
[kTopEarlgreyPlicIrqIdGpioGpio30] = kTopEarlgreyPlicPeripheralGpio,
[kTopEarlgreyPlicIrqIdGpioGpio31] = kTopEarlgreyPlicPeripheralGpio,
- [kTopEarlgreyPlicIrqIdSpiDeviceRxf] = kTopEarlgreyPlicPeripheralSpiDevice,
- [kTopEarlgreyPlicIrqIdSpiDeviceRxlvl] = kTopEarlgreyPlicPeripheralSpiDevice,
- [kTopEarlgreyPlicIrqIdSpiDeviceTxlvl] = kTopEarlgreyPlicPeripheralSpiDevice,
- [kTopEarlgreyPlicIrqIdSpiDeviceRxerr] = kTopEarlgreyPlicPeripheralSpiDevice,
- [kTopEarlgreyPlicIrqIdSpiDeviceRxoverflow] = kTopEarlgreyPlicPeripheralSpiDevice,
- [kTopEarlgreyPlicIrqIdSpiDeviceTxunderflow] = kTopEarlgreyPlicPeripheralSpiDevice,
- [kTopEarlgreyPlicIrqIdSpiDeviceTpmCmdaddrNotempty] = kTopEarlgreyPlicPeripheralSpiDevice,
+ [kTopEarlgreyPlicIrqIdSpiDeviceRxFull] = kTopEarlgreyPlicPeripheralSpiDevice,
+ [kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark] = kTopEarlgreyPlicPeripheralSpiDevice,
+ [kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark] = kTopEarlgreyPlicPeripheralSpiDevice,
+ [kTopEarlgreyPlicIrqIdSpiDeviceRxError] = kTopEarlgreyPlicPeripheralSpiDevice,
+ [kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow] = kTopEarlgreyPlicPeripheralSpiDevice,
+ [kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow] = kTopEarlgreyPlicPeripheralSpiDevice,
+ [kTopEarlgreyPlicIrqIdSpiDeviceTpmHeaderNotEmpty] = kTopEarlgreyPlicPeripheralSpiDevice,
[kTopEarlgreyPlicIrqIdSpiHost0Error] = kTopEarlgreyPlicPeripheralSpiHost0,
[kTopEarlgreyPlicIrqIdSpiHost0SpiEvent] = kTopEarlgreyPlicPeripheralSpiHost0,
[kTopEarlgreyPlicIrqIdSpiHost1Error] = kTopEarlgreyPlicPeripheralSpiHost1,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index e9af27e..717f6cb 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1079,13 +1079,13 @@
kTopEarlgreyPlicIrqIdGpioGpio29 = 62, /**< gpio_gpio 29 */
kTopEarlgreyPlicIrqIdGpioGpio30 = 63, /**< gpio_gpio 30 */
kTopEarlgreyPlicIrqIdGpioGpio31 = 64, /**< gpio_gpio 31 */
- kTopEarlgreyPlicIrqIdSpiDeviceRxf = 65, /**< spi_device_rxf */
- kTopEarlgreyPlicIrqIdSpiDeviceRxlvl = 66, /**< spi_device_rxlvl */
- kTopEarlgreyPlicIrqIdSpiDeviceTxlvl = 67, /**< spi_device_txlvl */
- kTopEarlgreyPlicIrqIdSpiDeviceRxerr = 68, /**< spi_device_rxerr */
- kTopEarlgreyPlicIrqIdSpiDeviceRxoverflow = 69, /**< spi_device_rxoverflow */
- kTopEarlgreyPlicIrqIdSpiDeviceTxunderflow = 70, /**< spi_device_txunderflow */
- kTopEarlgreyPlicIrqIdSpiDeviceTpmCmdaddrNotempty = 71, /**< spi_device_tpm_cmdaddr_notempty */
+ kTopEarlgreyPlicIrqIdSpiDeviceRxFull = 65, /**< spi_device_rx_full */
+ kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark = 66, /**< spi_device_rx_watermark */
+ kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark = 67, /**< spi_device_tx_watermark */
+ kTopEarlgreyPlicIrqIdSpiDeviceRxError = 68, /**< spi_device_rx_error */
+ kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow = 69, /**< spi_device_rx_overflow */
+ kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow = 70, /**< spi_device_tx_underflow */
+ kTopEarlgreyPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 71, /**< spi_device_tpm_header_not_empty */
kTopEarlgreyPlicIrqIdSpiHost0Error = 72, /**< spi_host0_error */
kTopEarlgreyPlicIrqIdSpiHost0SpiEvent = 73, /**< spi_host0_spi_event */
kTopEarlgreyPlicIrqIdSpiHost1Error = 74, /**< spi_host1_error */
diff --git a/sw/device/lib/dif/autogen/dif_spi_device_autogen.c b/sw/device/lib/dif/autogen/dif_spi_device_autogen.c
index 0ecc4a4..ca6a400 100644
--- a/sw/device/lib/dif/autogen/dif_spi_device_autogen.c
+++ b/sw/device/lib/dif/autogen/dif_spi_device_autogen.c
@@ -16,26 +16,26 @@
static bool spi_device_get_irq_bit_index(dif_spi_device_irq_t irq,
bitfield_bit32_index_t *index_out) {
switch (irq) {
- case kDifSpiDeviceIrqRxf:
- *index_out = SPI_DEVICE_INTR_STATE_RXF_BIT;
+ case kDifSpiDeviceIrqRxFull:
+ *index_out = SPI_DEVICE_INTR_STATE_RX_FULL_BIT;
break;
- case kDifSpiDeviceIrqRxlvl:
- *index_out = SPI_DEVICE_INTR_STATE_RXLVL_BIT;
+ case kDifSpiDeviceIrqRxWatermark:
+ *index_out = SPI_DEVICE_INTR_STATE_RX_WATERMARK_BIT;
break;
- case kDifSpiDeviceIrqTxlvl:
- *index_out = SPI_DEVICE_INTR_STATE_TXLVL_BIT;
+ case kDifSpiDeviceIrqTxWatermark:
+ *index_out = SPI_DEVICE_INTR_STATE_TX_WATERMARK_BIT;
break;
- case kDifSpiDeviceIrqRxerr:
- *index_out = SPI_DEVICE_INTR_STATE_RXERR_BIT;
+ case kDifSpiDeviceIrqRxError:
+ *index_out = SPI_DEVICE_INTR_STATE_RX_ERROR_BIT;
break;
- case kDifSpiDeviceIrqRxoverflow:
- *index_out = SPI_DEVICE_INTR_STATE_RXOVERFLOW_BIT;
+ case kDifSpiDeviceIrqRxOverflow:
+ *index_out = SPI_DEVICE_INTR_STATE_RX_OVERFLOW_BIT;
break;
- case kDifSpiDeviceIrqTxunderflow:
- *index_out = SPI_DEVICE_INTR_STATE_TXUNDERFLOW_BIT;
+ case kDifSpiDeviceIrqTxUnderflow:
+ *index_out = SPI_DEVICE_INTR_STATE_TX_UNDERFLOW_BIT;
break;
- case kDifSpiDeviceIrqTpmCmdaddrNotempty:
- *index_out = SPI_DEVICE_INTR_STATE_TPM_CMDADDR_NOTEMPTY_BIT;
+ case kDifSpiDeviceIrqTpmHeaderNotEmpty:
+ *index_out = SPI_DEVICE_INTR_STATE_TPM_HEADER_NOT_EMPTY_BIT;
break;
default:
return false;
diff --git a/sw/device/lib/dif/autogen/dif_spi_device_autogen.h b/sw/device/lib/dif/autogen/dif_spi_device_autogen.h
index ab0ef32..79c466f 100644
--- a/sw/device/lib/dif/autogen/dif_spi_device_autogen.h
+++ b/sw/device/lib/dif/autogen/dif_spi_device_autogen.h
@@ -43,31 +43,31 @@
/**
* RX SRAM FIFO Full
*/
- kDifSpiDeviceIrqRxf = 0,
+ kDifSpiDeviceIrqRxFull = 0,
/**
* RX SRAM FIFO is above the level
*/
- kDifSpiDeviceIrqRxlvl = 1,
+ kDifSpiDeviceIrqRxWatermark = 1,
/**
* TX SRAM FIFO is under the level
*/
- kDifSpiDeviceIrqTxlvl = 2,
+ kDifSpiDeviceIrqTxWatermark = 2,
/**
* SDI in FwMode has error
*/
- kDifSpiDeviceIrqRxerr = 3,
+ kDifSpiDeviceIrqRxError = 3,
/**
* RX Async FIFO overflow
*/
- kDifSpiDeviceIrqRxoverflow = 4,
+ kDifSpiDeviceIrqRxOverflow = 4,
/**
* TX Async FIFO underflow
*/
- kDifSpiDeviceIrqTxunderflow = 5,
+ kDifSpiDeviceIrqTxUnderflow = 5,
/**
- * TPM Command/Address buffer available
+ * TPM Header(Command/Address) buffer available
*/
- kDifSpiDeviceIrqTpmCmdaddrNotempty = 6,
+ kDifSpiDeviceIrqTpmHeaderNotEmpty = 6,
} dif_spi_device_irq_t;
/**
diff --git a/sw/device/lib/dif/autogen/dif_spi_device_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_spi_device_autogen_unittest.cc
index 6843e3e..2123440 100644
--- a/sw/device/lib/dif/autogen/dif_spi_device_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_spi_device_autogen_unittest.cc
@@ -59,16 +59,16 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(
- dif_spi_device_irq_is_pending(nullptr, kDifSpiDeviceIrqRxf, &is_pending),
- kDifBadArg);
+ EXPECT_EQ(dif_spi_device_irq_is_pending(nullptr, kDifSpiDeviceIrqRxFull,
+ &is_pending),
+ kDifBadArg);
+
+ EXPECT_EQ(dif_spi_device_irq_is_pending(&spi_device_, kDifSpiDeviceIrqRxFull,
+ nullptr),
+ kDifBadArg);
EXPECT_EQ(
- dif_spi_device_irq_is_pending(&spi_device_, kDifSpiDeviceIrqRxf, nullptr),
- kDifBadArg);
-
- EXPECT_EQ(
- dif_spi_device_irq_is_pending(nullptr, kDifSpiDeviceIrqRxf, nullptr),
+ dif_spi_device_irq_is_pending(nullptr, kDifSpiDeviceIrqRxFull, nullptr),
kDifBadArg);
}
@@ -87,8 +87,8 @@
// Get the first IRQ state.
irq_state = false;
EXPECT_READ32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
- {{SPI_DEVICE_INTR_STATE_RXF_BIT, true}});
- EXPECT_EQ(dif_spi_device_irq_is_pending(&spi_device_, kDifSpiDeviceIrqRxf,
+ {{SPI_DEVICE_INTR_STATE_RX_FULL_BIT, true}});
+ EXPECT_EQ(dif_spi_device_irq_is_pending(&spi_device_, kDifSpiDeviceIrqRxFull,
&irq_state),
kDifOk);
EXPECT_TRUE(irq_state);
@@ -96,9 +96,9 @@
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
- {{SPI_DEVICE_INTR_STATE_TPM_CMDADDR_NOTEMPTY_BIT, false}});
+ {{SPI_DEVICE_INTR_STATE_TPM_HEADER_NOT_EMPTY_BIT, false}});
EXPECT_EQ(dif_spi_device_irq_is_pending(
- &spi_device_, kDifSpiDeviceIrqTpmCmdaddrNotempty, &irq_state),
+ &spi_device_, kDifSpiDeviceIrqTpmHeaderNotEmpty, &irq_state),
kDifOk);
EXPECT_FALSE(irq_state);
}
@@ -106,7 +106,7 @@
class IrqAcknowledgeTest : public SpiDeviceTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_spi_device_irq_acknowledge(nullptr, kDifSpiDeviceIrqRxf),
+ EXPECT_EQ(dif_spi_device_irq_acknowledge(nullptr, kDifSpiDeviceIrqRxFull),
kDifBadArg);
}
@@ -119,15 +119,16 @@
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
- {{SPI_DEVICE_INTR_STATE_RXF_BIT, true}});
- EXPECT_EQ(dif_spi_device_irq_acknowledge(&spi_device_, kDifSpiDeviceIrqRxf),
- kDifOk);
+ {{SPI_DEVICE_INTR_STATE_RX_FULL_BIT, true}});
+ EXPECT_EQ(
+ dif_spi_device_irq_acknowledge(&spi_device_, kDifSpiDeviceIrqRxFull),
+ kDifOk);
// Clear the last IRQ state.
EXPECT_WRITE32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
- {{SPI_DEVICE_INTR_STATE_TPM_CMDADDR_NOTEMPTY_BIT, true}});
+ {{SPI_DEVICE_INTR_STATE_TPM_HEADER_NOT_EMPTY_BIT, true}});
EXPECT_EQ(dif_spi_device_irq_acknowledge(&spi_device_,
- kDifSpiDeviceIrqTpmCmdaddrNotempty),
+ kDifSpiDeviceIrqTpmHeaderNotEmpty),
kDifOk);
}
@@ -136,16 +137,16 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_spi_device_irq_get_enabled(nullptr, kDifSpiDeviceIrqRxf, &irq_state),
- kDifBadArg);
+ EXPECT_EQ(dif_spi_device_irq_get_enabled(nullptr, kDifSpiDeviceIrqRxFull,
+ &irq_state),
+ kDifBadArg);
- EXPECT_EQ(dif_spi_device_irq_get_enabled(&spi_device_, kDifSpiDeviceIrqRxf,
+ EXPECT_EQ(dif_spi_device_irq_get_enabled(&spi_device_, kDifSpiDeviceIrqRxFull,
nullptr),
kDifBadArg);
EXPECT_EQ(
- dif_spi_device_irq_get_enabled(nullptr, kDifSpiDeviceIrqRxf, nullptr),
+ dif_spi_device_irq_get_enabled(nullptr, kDifSpiDeviceIrqRxFull, nullptr),
kDifBadArg);
}
@@ -164,8 +165,8 @@
// First IRQ is enabled.
irq_state = kDifToggleDisabled;
EXPECT_READ32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
- {{SPI_DEVICE_INTR_ENABLE_RXF_BIT, true}});
- EXPECT_EQ(dif_spi_device_irq_get_enabled(&spi_device_, kDifSpiDeviceIrqRxf,
+ {{SPI_DEVICE_INTR_ENABLE_RX_FULL_BIT, true}});
+ EXPECT_EQ(dif_spi_device_irq_get_enabled(&spi_device_, kDifSpiDeviceIrqRxFull,
&irq_state),
kDifOk);
EXPECT_EQ(irq_state, kDifToggleEnabled);
@@ -173,9 +174,9 @@
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
- {{SPI_DEVICE_INTR_ENABLE_TPM_CMDADDR_NOTEMPTY_BIT, false}});
+ {{SPI_DEVICE_INTR_ENABLE_TPM_HEADER_NOT_EMPTY_BIT, false}});
EXPECT_EQ(dif_spi_device_irq_get_enabled(
- &spi_device_, kDifSpiDeviceIrqTpmCmdaddrNotempty, &irq_state),
+ &spi_device_, kDifSpiDeviceIrqTpmHeaderNotEmpty, &irq_state),
kDifOk);
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -185,9 +186,9 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(
- dif_spi_device_irq_set_enabled(nullptr, kDifSpiDeviceIrqRxf, irq_state),
- kDifBadArg);
+ EXPECT_EQ(dif_spi_device_irq_set_enabled(nullptr, kDifSpiDeviceIrqRxFull,
+ irq_state),
+ kDifBadArg);
}
TEST_F(IrqSetEnabledTest, BadIrq) {
@@ -204,8 +205,8 @@
// Enable first IRQ.
irq_state = kDifToggleEnabled;
EXPECT_MASK32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
- {{SPI_DEVICE_INTR_ENABLE_RXF_BIT, 0x1, true}});
- EXPECT_EQ(dif_spi_device_irq_set_enabled(&spi_device_, kDifSpiDeviceIrqRxf,
+ {{SPI_DEVICE_INTR_ENABLE_RX_FULL_BIT, 0x1, true}});
+ EXPECT_EQ(dif_spi_device_irq_set_enabled(&spi_device_, kDifSpiDeviceIrqRxFull,
irq_state),
kDifOk);
@@ -213,16 +214,17 @@
irq_state = kDifToggleDisabled;
EXPECT_MASK32(
SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
- {{SPI_DEVICE_INTR_ENABLE_TPM_CMDADDR_NOTEMPTY_BIT, 0x1, false}});
+ {{SPI_DEVICE_INTR_ENABLE_TPM_HEADER_NOT_EMPTY_BIT, 0x1, false}});
EXPECT_EQ(dif_spi_device_irq_set_enabled(
- &spi_device_, kDifSpiDeviceIrqTpmCmdaddrNotempty, irq_state),
+ &spi_device_, kDifSpiDeviceIrqTpmHeaderNotEmpty, irq_state),
kDifOk);
}
class IrqForceTest : public SpiDeviceTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_spi_device_irq_force(nullptr, kDifSpiDeviceIrqRxf), kDifBadArg);
+ EXPECT_EQ(dif_spi_device_irq_force(nullptr, kDifSpiDeviceIrqRxFull),
+ kDifBadArg);
}
TEST_F(IrqForceTest, BadIrq) {
@@ -234,16 +236,16 @@
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(SPI_DEVICE_INTR_TEST_REG_OFFSET,
- {{SPI_DEVICE_INTR_TEST_RXF_BIT, true}});
- EXPECT_EQ(dif_spi_device_irq_force(&spi_device_, kDifSpiDeviceIrqRxf),
+ {{SPI_DEVICE_INTR_TEST_RX_FULL_BIT, true}});
+ EXPECT_EQ(dif_spi_device_irq_force(&spi_device_, kDifSpiDeviceIrqRxFull),
kDifOk);
// Force last IRQ.
EXPECT_WRITE32(SPI_DEVICE_INTR_TEST_REG_OFFSET,
- {{SPI_DEVICE_INTR_TEST_TPM_CMDADDR_NOTEMPTY_BIT, true}});
- EXPECT_EQ(dif_spi_device_irq_force(&spi_device_,
- kDifSpiDeviceIrqTpmCmdaddrNotempty),
- kDifOk);
+ {{SPI_DEVICE_INTR_TEST_TPM_HEADER_NOT_EMPTY_BIT, true}});
+ EXPECT_EQ(
+ dif_spi_device_irq_force(&spi_device_, kDifSpiDeviceIrqTpmHeaderNotEmpty),
+ kDifOk);
}
class IrqDisableAllTest : public SpiDeviceTest {};
diff --git a/sw/device/tests/autogen/plic_all_irqs_test.c b/sw/device/tests/autogen/plic_all_irqs_test.c
index a966d71..60c2dde 100644
--- a/sw/device/tests/autogen/plic_all_irqs_test.c
+++ b/sw/device/tests/autogen/plic_all_irqs_test.c
@@ -219,7 +219,7 @@
// kTopEarlgreyPlicIrqIdRvTimerTimerExpired0_0); break;
// case kTopEarlgreyPlicPeripheralSpiDevice:
// PERIPHERAL_ISR(spi_device, spi_device,
- // kTopEarlgreyPlicIrqIdSpiDeviceRxf); break;
+ // kTopEarlgreyPlicIrqIdSpiDeviceRxFull); break;
// case kTopEarlgreyPlicPeripheralSpiHost0:
// PERIPHERAL_ISR(spi_host, spi_host0,
// kTopEarlgreyPlicIrqIdSpiHost0Error); break;
@@ -437,8 +437,8 @@
// kDifRvTimerIrqTimerExpired0_0);
// PERIPHERAL_IRQS_TRIGGER(spi_device, spi_device,
// kTopEarlgreyPlicPeripheralSpiDevice,
- // kDifSpiDeviceIrqRxf,
- // kDifSpiDeviceIrqTpmCmdaddrNotempty);
+ // kDifSpiDeviceIrqRxFull,
+ // kDifSpiDeviceIrqTpmHeaderNotEmpty);
// PERIPHERAL_IRQS_TRIGGER(spi_host, spi_host0,
// kTopEarlgreyPlicPeripheralSpiHost0,
// kDifSpiHostIrqError, kDifSpiHostIrqSpiEvent);
diff --git a/sw/device/tests/sim_dv/spi_tx_rx_test.c b/sw/device/tests/sim_dv/spi_tx_rx_test.c
index 24cc362..c6c892f 100644
--- a/sw/device/tests/sim_dv/spi_tx_rx_test.c
+++ b/sw/device/tests/sim_dv/spi_tx_rx_test.c
@@ -83,30 +83,30 @@
// Correlate the interrupt fired at PLIC with SPI DEVICE.
dif_spi_device_irq_t spi_device_irq = 0;
switch (plic_irq_id) {
- case kTopEarlgreyPlicIrqIdSpiDeviceRxf:
- spi_device_irq = kDifSpiDeviceIrqRxf;
+ case kTopEarlgreyPlicIrqIdSpiDeviceRxFull:
+ spi_device_irq = kDifSpiDeviceIrqRxFull;
CHECK(expected_irqs[spi_device_irq], "Unexpected RX full interrupt");
break;
- case kTopEarlgreyPlicIrqIdSpiDeviceRxlvl:
- spi_device_irq = kDifSpiDeviceIrqRxlvl;
+ case kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark:
+ spi_device_irq = kDifSpiDeviceIrqRxWatermark;
CHECK(expected_irqs[spi_device_irq],
"Unexpected RX above level interrupt");
break;
- case kTopEarlgreyPlicIrqIdSpiDeviceTxlvl:
- spi_device_irq = kDifSpiDeviceIrqTxlvl;
+ case kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark:
+ spi_device_irq = kDifSpiDeviceIrqTxWatermark;
CHECK(expected_irqs[spi_device_irq],
"Unexpected TX below level interrupt");
break;
- case kTopEarlgreyPlicIrqIdSpiDeviceRxerr:
- spi_device_irq = kDifSpiDeviceIrqRxerr;
+ case kTopEarlgreyPlicIrqIdSpiDeviceRxError:
+ spi_device_irq = kDifSpiDeviceIrqRxError;
CHECK(expected_irqs[spi_device_irq], "Unexpected RX error interrupt");
break;
- case kTopEarlgreyPlicIrqIdSpiDeviceRxoverflow:
- spi_device_irq = kDifSpiDeviceIrqRxoverflow;
+ case kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow:
+ spi_device_irq = kDifSpiDeviceIrqRxOverflow;
CHECK(expected_irqs[spi_device_irq], "Unexpected RX overflow interrupt");
break;
- case kTopEarlgreyPlicIrqIdSpiDeviceTxunderflow:
- spi_device_irq = kDifSpiDeviceIrqTxunderflow;
+ case kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow:
+ spi_device_irq = kDifSpiDeviceIrqTxUnderflow;
CHECK(expected_irqs[spi_device_irq], "Unexpected TX underflow interrupt");
break;
default:
@@ -141,18 +141,18 @@
CHECK_DIF_OK(dif_spi_device_init(base_addr, spi_device));
CHECK_DIF_OK(dif_spi_device_configure(spi_device, spi_device_config));
- CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device, kDifSpiDeviceIrqRxf,
- kDifToggleEnabled));
- CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device, kDifSpiDeviceIrqRxlvl,
- kDifToggleEnabled));
- CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device, kDifSpiDeviceIrqTxlvl,
- kDifToggleEnabled));
- CHECK_DIF_OK(dif_spi_device_irq_set_enabled(spi_device, kDifSpiDeviceIrqRxerr,
- kDifToggleEnabled));
CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
- spi_device, kDifSpiDeviceIrqRxoverflow, kDifToggleEnabled));
+ spi_device, kDifSpiDeviceIrqRxFull, kDifToggleEnabled));
CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
- spi_device, kDifSpiDeviceIrqTxunderflow, kDifToggleEnabled));
+ spi_device, kDifSpiDeviceIrqRxWatermark, kDifToggleEnabled));
+ CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
+ spi_device, kDifSpiDeviceIrqTxWatermark, kDifToggleEnabled));
+ CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
+ spi_device, kDifSpiDeviceIrqRxError, kDifToggleEnabled));
+ CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
+ spi_device, kDifSpiDeviceIrqRxOverflow, kDifToggleEnabled));
+ CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
+ spi_device, kDifSpiDeviceIrqTxUnderflow, kDifToggleEnabled));
// Initialize the volatile irq variables.
for (int i = 0; i < SPI_DEVICE_NUM_IRQS; i++) {
@@ -173,24 +173,27 @@
// Set the priority of SPI DEVICE interrupts at PLIC to be >=1 (so ensure the
// target does get interrupted).
- CHECK(dif_rv_plic_irq_set_priority(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxf,
+ CHECK(dif_rv_plic_irq_set_priority(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxFull,
kDifRvPlicMaxPriority) == kDifRvPlicOk,
"dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxlvl,
+ CHECK(dif_rv_plic_irq_set_priority(plic,
+ kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark,
kDifRvPlicMaxPriority) == kDifRvPlicOk,
"dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic, kTopEarlgreyPlicIrqIdSpiDeviceTxlvl,
+ CHECK(dif_rv_plic_irq_set_priority(plic,
+ kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark,
kDifRvPlicMaxPriority) == kDifRvPlicOk,
, "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxerr,
+ CHECK(
+ dif_rv_plic_irq_set_priority(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxError,
+ kDifRvPlicMaxPriority) == kDifRvPlicOk,
+ "dif_rv_plic_irq_set_priority failed");
+ CHECK(dif_rv_plic_irq_set_priority(plic,
+ kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow,
kDifRvPlicMaxPriority) == kDifRvPlicOk,
"dif_rv_plic_irq_set_priority failed");
CHECK(dif_rv_plic_irq_set_priority(plic,
- kTopEarlgreyPlicIrqIdSpiDeviceRxoverflow,
- kDifRvPlicMaxPriority) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_priority failed");
- CHECK(dif_rv_plic_irq_set_priority(plic,
- kTopEarlgreyPlicIrqIdSpiDeviceTxunderflow,
+ kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow,
kDifRvPlicMaxPriority) == kDifRvPlicOk,
"dif_rv_plic_irq_set_priority failed");
@@ -199,45 +202,47 @@
0x0) == kDifRvPlicOk,
"dif_rv_plic_target_set_threshold failed");
- CHECK(dif_rv_plic_irq_set_enabled(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxf,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
-
- CHECK(dif_rv_plic_irq_set_enabled(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxlvl,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
-
- CHECK(dif_rv_plic_irq_set_enabled(plic, kTopEarlgreyPlicIrqIdSpiDeviceTxlvl,
- kTopEarlgreyPlicTargetIbex0,
- kDifRvPlicToggleEnabled) == kDifRvPlicOk,
- "dif_rv_plic_irq_set_enabled failed");
-
- CHECK(dif_rv_plic_irq_set_enabled(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxerr,
+ CHECK(dif_rv_plic_irq_set_enabled(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxFull,
kTopEarlgreyPlicTargetIbex0,
kDifRvPlicToggleEnabled) == kDifRvPlicOk,
"dif_rv_plic_irq_set_enabled failed");
CHECK(dif_rv_plic_irq_set_enabled(plic,
- kTopEarlgreyPlicIrqIdSpiDeviceRxoverflow,
+ kTopEarlgreyPlicIrqIdSpiDeviceRxWatermark,
kTopEarlgreyPlicTargetIbex0,
kDifRvPlicToggleEnabled) == kDifRvPlicOk,
"dif_rv_plic_irq_set_enabled failed");
CHECK(dif_rv_plic_irq_set_enabled(plic,
- kTopEarlgreyPlicIrqIdSpiDeviceTxunderflow,
+ kTopEarlgreyPlicIrqIdSpiDeviceTxWatermark,
+ kTopEarlgreyPlicTargetIbex0,
+ kDifRvPlicToggleEnabled) == kDifRvPlicOk,
+ "dif_rv_plic_irq_set_enabled failed");
+
+ CHECK(dif_rv_plic_irq_set_enabled(plic, kTopEarlgreyPlicIrqIdSpiDeviceRxError,
+ kTopEarlgreyPlicTargetIbex0,
+ kDifRvPlicToggleEnabled) == kDifRvPlicOk,
+ "dif_rv_plic_irq_set_enabled failed");
+
+ CHECK(dif_rv_plic_irq_set_enabled(plic,
+ kTopEarlgreyPlicIrqIdSpiDeviceRxOverflow,
+ kTopEarlgreyPlicTargetIbex0,
+ kDifRvPlicToggleEnabled) == kDifRvPlicOk,
+ "dif_rv_plic_irq_set_enabled failed");
+
+ CHECK(dif_rv_plic_irq_set_enabled(plic,
+ kTopEarlgreyPlicIrqIdSpiDeviceTxUnderflow,
kTopEarlgreyPlicTargetIbex0,
kDifRvPlicToggleEnabled) == kDifRvPlicOk,
"dif_rv_plic_irq_set_enabled failed");
}
static bool exp_irqs_fired(void) {
- return fired_irqs[kDifSpiDeviceIrqRxlvl] &&
- fired_irqs[kDifSpiDeviceIrqTxlvl] &&
- fired_irqs[kDifSpiDeviceIrqRxoverflow] &&
- fired_irqs[kDifSpiDeviceIrqTxunderflow] &&
- fired_irqs[kDifSpiDeviceIrqRxf];
+ return fired_irqs[kDifSpiDeviceIrqRxWatermark] &&
+ fired_irqs[kDifSpiDeviceIrqTxWatermark] &&
+ fired_irqs[kDifSpiDeviceIrqRxOverflow] &&
+ fired_irqs[kDifSpiDeviceIrqTxUnderflow] &&
+ fired_irqs[kDifSpiDeviceIrqRxFull];
}
static bool execute_test(const dif_spi_device_t *spi_device,
@@ -258,30 +263,30 @@
CHECK_DIF_OK(dif_spi_device_set_irq_levels(
spi_device, SPI_DEVICE_DATASET_SIZE, SPI_DEVICE_DATASET_SIZE / 2));
- expected_irqs[kDifSpiDeviceIrqTxlvl] = true;
+ expected_irqs[kDifSpiDeviceIrqTxWatermark] = true;
bool read_rx_fifo_done = false;
while (!read_rx_fifo_done || !exp_irqs_fired()) {
// set rx tx level back to default value so TxBelowLevel irq won't trigger
- if (fired_irqs[kDifSpiDeviceIrqTxlvl] &&
- expected_irqs[kDifSpiDeviceIrqTxlvl]) {
+ if (fired_irqs[kDifSpiDeviceIrqTxWatermark] &&
+ expected_irqs[kDifSpiDeviceIrqTxWatermark]) {
CHECK_DIF_OK(dif_spi_device_set_irq_levels(spi_device,
SPI_DEVICE_DATASET_SIZE, 0));
- expected_irqs[kDifSpiDeviceIrqTxlvl] = false;
- expected_irqs[kDifSpiDeviceIrqRxlvl] = true;
+ expected_irqs[kDifSpiDeviceIrqTxWatermark] = false;
+ expected_irqs[kDifSpiDeviceIrqRxWatermark] = true;
LOG_INFO("SPI_DEVICE tx_below_level interrupt fired.");
}
// wait for SPI_HOST to send 128 bytes and trigger RxAboveLevel irq
- if (fired_irqs[kDifSpiDeviceIrqRxlvl] &&
- expected_irqs[kDifSpiDeviceIrqRxlvl]) {
- expected_irqs[kDifSpiDeviceIrqRxlvl] = false;
+ if (fired_irqs[kDifSpiDeviceIrqRxWatermark] &&
+ expected_irqs[kDifSpiDeviceIrqRxWatermark]) {
+ expected_irqs[kDifSpiDeviceIrqRxWatermark] = false;
LOG_INFO("SPI_DEVICE rx_above_level interrupt fired.");
}
// when 128 bytes received in RX_FIFO from SPI_HOST,
// read out and compare against the expected data
- if (fired_irqs[kDifSpiDeviceIrqRxlvl] && !read_rx_fifo_done) {
+ if (fired_irqs[kDifSpiDeviceIrqRxWatermark] && !read_rx_fifo_done) {
size_t bytes_recved = 0;
uint8_t spi_device_rx_data[SPI_DEVICE_DATASET_SIZE];
CHECK_DIF_OK(dif_spi_device_recv(spi_device, spi_device_config,
@@ -296,8 +301,8 @@
bytes_recved, SPI_DEVICE_DATASET_SIZE);
}
// expect SPI_HOST to send another 1024 bytes to fill RX SRAM FIFO
- expected_irqs[kDifSpiDeviceIrqTxunderflow] = true;
- fired_irqs[kDifSpiDeviceIrqRxlvl] = false;
+ expected_irqs[kDifSpiDeviceIrqTxUnderflow] = true;
+ fired_irqs[kDifSpiDeviceIrqRxWatermark] = false;
// Check data consistency.
LOG_INFO("Checking the received SPI_HOST RX_FIFO data for consistency.");
@@ -308,26 +313,26 @@
}
}
- if (read_rx_fifo_done && fired_irqs[kDifSpiDeviceIrqTxunderflow]) {
- expected_irqs[kDifSpiDeviceIrqRxlvl] = true;
+ if (read_rx_fifo_done && fired_irqs[kDifSpiDeviceIrqTxUnderflow]) {
+ expected_irqs[kDifSpiDeviceIrqRxWatermark] = true;
// TxUnderflow will fire every cycle, so disable this interrupt once fired
CHECK_DIF_OK(dif_spi_device_irq_set_enabled(
- spi_device, kDifSpiDeviceIrqTxunderflow, kDifToggleDisabled));
- expected_irqs[kDifSpiDeviceIrqTxunderflow] = false;
+ spi_device, kDifSpiDeviceIrqTxUnderflow, kDifToggleDisabled));
+ expected_irqs[kDifSpiDeviceIrqTxUnderflow] = false;
LOG_INFO("SPI_DEVICE Tx Below level interrupt fired.");
}
- if (read_rx_fifo_done && fired_irqs[kDifSpiDeviceIrqRxlvl]) {
- expected_irqs[kDifSpiDeviceIrqRxlvl] = false;
- expected_irqs[kDifSpiDeviceIrqRxf] = true;
+ if (read_rx_fifo_done && fired_irqs[kDifSpiDeviceIrqRxWatermark]) {
+ expected_irqs[kDifSpiDeviceIrqRxWatermark] = false;
+ expected_irqs[kDifSpiDeviceIrqRxFull] = true;
LOG_INFO("SPI_DEVICE RX Above level interrupt fired.");
}
// After RX SRAM FIFO full, expect RX async FIFO overflow irq
- if (fired_irqs[kDifSpiDeviceIrqRxf] &&
- !fired_irqs[kDifSpiDeviceIrqRxoverflow]) {
- expected_irqs[kDifSpiDeviceIrqRxf] = false;
- expected_irqs[kDifSpiDeviceIrqRxoverflow] = true;
+ if (fired_irqs[kDifSpiDeviceIrqRxFull] &&
+ !fired_irqs[kDifSpiDeviceIrqRxOverflow]) {
+ expected_irqs[kDifSpiDeviceIrqRxFull] = false;
+ expected_irqs[kDifSpiDeviceIrqRxOverflow] = true;
LOG_INFO("SPI_DEVICE RX_FIFO full interrupt fired.");
}
