| commit | 2fee253b37bce8d297fa547563a18c23b3b8ba60 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Thu Apr 29 17:24:31 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Mon May 10 12:53:59 2021 +0100 |
| tree | 2bd117e0b003db5f8629f91fd54f99efa824f19e | |
| parent | 56a64bd2689ee26d41f24f7533aa09f53f607569 [diff] |
[verilator] Don't build chip_earlgrey_verilator with debug symbols The resulting binary shrinks from 421MiB to 80MiB. The compilation time on my laptop drops from 873s to 725s real time, and from 5715s to 4771s user time. (Both drops are roughly 17%). While we might plausibly want to debug DPI code in GDB, it seems like this won't happen often and (if we do want to) it's not particularly hard to put the -g back again. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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