| commit | 1fa3b5e0365c2e333375178f7baf6e87273839f5 | [log] [tgz] |
|---|---|---|
| author | Michael Schaffner <msf@opentitan.org> | Tue Dec 14 04:49:06 2021 -0800 |
| committer | Michael Schaffner <msf@google.com> | Tue Dec 14 23:53:34 2021 -0800 |
| tree | cbca41b99590ed8078c41125bd02b5b134287f6a | |
| parent | 8089c124b17562ac35630512abd33f13b87967a8 [diff] |
Update lowrisc_ibex to lowRISC/ibex@a33a91b2 Update code from upstream repository https://github.com/lowRISC/ibex.git to revision a33a91b2326b560c76b780d12cae200a1302fb7d * [lint] Fix some AscentLint errors (Pirmin Vogel) * [dv] Set UVM_VERBOSITY to UVM_LOW (Greg Chadwick) * [dv] Fix bad reference to instr_req_out (Greg Chadwick) * [rtl] Move PMP checking to IF stage output (Tom Roberts) * [rtl] Replace always_ff with always @(posedge .. in FPGA regfile (Pirmin Vogel) * [dv] Fix PMP error handling for icache (Greg Chadwick) * [dv] Add missing copyright header (Greg Chadwick) * [dv] Add recoverable NMI handling to cosim (Greg Chadwick) * [dv] Fix dside memory checking (Greg Chadwick) * [dv] Fix cosim memory size (Greg Chadwick) * Update google_riscv-dv to google/riscv-dv@6053014 (Michael Schaffner) * [ibex_top] Use correct ECC codeword for '0 reset in regfile (Michael Schaffner) * Update lowrisc_ip to lowRISC/opentitan@be1359d27 (Michael Schaffner) * [rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93) (Pirmin Vogel) * [rtl, bitmanip] Clarify situation around zext.[bh] pseudo- instructions (Pirmin Vogel) * [rtl] Fix typo in comment (Pirmin Vogel) * [rtl, bitmanip] Align Zbb implementation with draft v.0.93 and v.1.0.0 (Pirmin Vogel) * [rtl, bitmanip] Align Zbs implementation with draft v.0.93 and v.1.0.0 (Pirmin Vogel) * [rtl, bitmanip] Rename bext/bdep to bcompress/bdecompress (Pirmin Vogel) * Update google_riscv-dv to google/riscv-dv@ea8dd25 (Pirmin Vogel) * [secded] Switch to inverted ECC codes (Michael Schaffner) * Update lowrisc_ip to lowRISC/opentitan@34ba5e45f (Michael Schaffner) * Update lowrisc_ip to lowRISC/opentitan@3a672eb36 (Canberk Topal) * [dv/icache] Add missing window reset call (Tom Roberts) * Move NT branch addr calculation to ID stage (Sam Shahrestani) * Update lowrisc_ip to lowRISC/opentitan@ad629e3e6 (Rupert Swarbrick) * [ci] Add co-simulation testing of CoreMark (Greg Chadwick) * [coremark] Add option to coremark build to suppress pcount dump (Greg Chadwick) * [cosim] Update documentation for cosim (Greg Chadwick) * [cosim] Add Simple System with cosim (Greg Chadwick) * [simple_system] Refactor Simple System (Greg Chadwick) * [dv] Add matched instruction count to cosim (Greg Chadwick) * [dv] Adjust cosim include paths (Greg Chadwick) * [bitmanip][zba] Add support for Zba (address calculation) extension (Michael Munday) * [dv] get ibex dv co-sim to run w questa (Miguel Escobar) * [doc] Update DIT documentation for unaligned ld/st (Tom Roberts) * Change use of blocking assignment to non-blocking inside always_ff (Henner Zeller) * [dv] Add co-simulation environment support to UVM testbench (Greg Chadwick) * [rtl] RVFI changes and extensions for co-simulation (Greg Chadwick) * [dv] Add co-simulation framework (Greg Chadwick) * [rtl,dv,doc] Flip priority of fast interrupts (Greg Chadwick) * [ibex/ml] add CSR/mem_error tests to ml_testlist (Udi) * [syn] Use read_verilog -defer in yosys_run_synth.tcl (Zachary Snow) * remove unused RD in branch insn from tracer (zeeshanrafique23) * Add missing parameters to ibex_top_tracing (Rupert Swarbrick) * set verible action version to 'main' (Wojciech Sipak) * bump verible action version (Wojciech Sipak) * [rtl] Fix retired instruction counters (Greg Chadwick) * [rtl] Factor ID exceptions into instruction kill (Greg Chadwick) * [ci] Add GHA workflows to review PRs using Verible (Wojciech Sipak) * [dv] Fix transaction ordering in ibex_mem_intf_monitor (Greg Chadwick) * [rtl] Implement mvendorid/marchid/mimpid CSRs (Greg Chadwick) * [style] Indent package bodies (Philipp Wagner) * [style] Indent module header with two spaces (Philipp Wagner) * [style] Use logical operators for reset (Philipp Wagner) * [style] Fix whitespace issues around operators (Philipp Wagner) * [style] Format module instantiations in tabular format (Philipp Wagner) Signed-off-by: Michael Schaffner <msf@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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