| commit | 40f72477995d57ef4e53b1568271e6414fd9d786 | [log] [tgz] |
|---|---|---|
| author | Udi Jonnalagadda <udij@google.com> | Tue Jun 22 15:19:20 2021 -0700 |
| committer | weicaiyang <49293026+weicaiyang@users.noreply.github.com> | Sun Nov 07 21:49:17 2021 -0800 |
| tree | 9791551d07d6f0fbbb6646bfe5aa79675dae9ef3 | |
| parent | c26089ae313a0627c44ef77c4ad0e3f35f213a87 [diff] |
[dv/sram] Enable multi-ral This PR enables full multi-ral functionality in the SRAM testbench, and to that end does a couple of related things: - Adds a custom reg model for the memory primitive, this is needed since different parameterizations of the TB will be reused at the chip-level. - General updates to the scoreboard and rest of the environment to make use of the built-in TL arrays in the base env_cfg classes, and remove the explicitly defined tl_agent initially used for the memory interface. - Remove the `mem_tl_errors` test as we can now rely on the automated test suite. - Parameterize the entire SRAM testbench accordingly to allow reuse at the chip-level. Signed-off-by: Udi Jonnalagadda <udij@google.com> Signed-off-by: Weicai Yang <weicai@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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