| commit | 2ed086ff5f6667491b9c019de2e6122ad6fa2572 | [log] [tgz] |
|---|---|---|
| author | Timothy Chen <timothytim@google.com> | Tue Mar 01 16:05:16 2022 -0800 |
| committer | tjaychen <timothytim@google.com> | Wed Mar 02 09:57:52 2022 -0800 |
| tree | fa6ab847c59104c653b6f942b49b76bc9d86abfb | |
| parent | 74aec162f126cb432979a05b8914f296f841afb8 [diff] |
[tlul] adjust tlul_sram_byte enable condition Previously, the tlul_sram_byte module was enabled whenever an adapter sram allowed both byte access and checked for integrity. This is not the correct enable condition. The tlul_sram_byte is meant to generate correct integrity when the downstream memory actually stores full word integrity and requires a read modified write for byte accesses. If a module simply checks for integrity, it does not say anything about whether the downstream module stores integrity and whether byte writes require a read modified write. Instead, change the condition to byte access AND data integrity passthrough are enabled. Data integrity passthrough implies the downstream memory will make use of extra integrity in some way and thus requires correct read modified write handling on byte accesses. Signed-off-by: Timothy Chen <timothytim@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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