[sram/dv] Fix executable test and tl_err test
1. Fixed sram_ctrl_main_executable
- change to only configure CSR exec, hw_debug_en and en_sram_ifetch
at the begining of each iteration rather than randomly do it during
mem access, so that scb doesn't need to be very cycle accurate
- fix type of `a_user.instr_type`
2. Fixed tl_err test. The mem error needs to be handled separately as
instr_type may cause tl_err.
3. uncommented `req_scr_key` which was a mistake when solving conflict
Signed-off-by: Weicai Yang <weicai@google.com>
diff --git a/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_executable_vseq.sv b/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_executable_vseq.sv
index 1c49bf3..3995caf 100644
--- a/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_executable_vseq.sv
+++ b/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_executable_vseq.sv
@@ -27,15 +27,9 @@
super.pre_start();
endtask
- task body();
- `DV_SPINWAIT_EXIT(
- forever begin
- randomize_and_drive_ifetch_en();
- cfg.clk_rst_vif.wait_clks($urandom_range(100, 500));
- end
- ,
- super.body();
- )
+ task req_scr_key();
+ super.req_scr_key();
+ randomize_and_drive_ifetch_en();
endtask
task randomize_and_drive_ifetch_en();
diff --git a/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_smoke_vseq.sv b/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_smoke_vseq.sv
index 7394ffb..f35a604 100644
--- a/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_smoke_vseq.sv
+++ b/hw/ip/sram_ctrl/dv/env/seq_lib/sram_ctrl_smoke_vseq.sv
@@ -62,7 +62,7 @@
`DV_CHECK_MEMBER_RANDOMIZE_FATAL(num_ops)
// Request a new scrambling key
- // req_scr_key();
+ req_scr_key();
fork
begin
diff --git a/hw/ip/sram_ctrl/dv/env/sram_ctrl_scoreboard.sv b/hw/ip/sram_ctrl/dv/env/sram_ctrl_scoreboard.sv
index eb45f41..954de7c 100644
--- a/hw/ip/sram_ctrl/dv/env/sram_ctrl_scoreboard.sv
+++ b/hw/ip/sram_ctrl/dv/env/sram_ctrl_scoreboard.sv
@@ -172,6 +172,8 @@
// any CSRs or uvm_mems.
virtual function bit sram_predict_tl_err(tl_seq_item item, tl_channels_e channel);
bit is_tl_err;
+ tlul_pkg::tl_a_user_t a_user = tlul_pkg::tl_a_user_t'(item.a_user);
+
is_tl_err = item.get_exp_d_error();
@@ -200,7 +202,7 @@
item.get_error_size_over_max()),
UVM_HIGH)
- if (item.a_user[15:14] == prim_mubi_pkg::MuBi4True) begin
+ if (a_user.instr_type == prim_mubi_pkg::MuBi4True) begin
// 2 error cases if an InstrType transaction is seen:
// - if it is a write transaction
// - if the SRAM is not configured in executable mode
@@ -216,6 +218,14 @@
return is_tl_err;
endfunction
+ virtual function bit predict_tl_err(tl_seq_item item, tl_channels_e channel, string ral_name);
+ if (ral_name == RAL_T::type_name) begin
+ super.predict_tl_err(item, channel, ral_name);
+ end else begin
+ sram_predict_tl_err(item, channel);
+ end
+ endfunction
+
function void build_phase(uvm_phase phase);
super.build_phase(phase);
sram_tl_a_chan_fifo = new("sram_tl_a_chan_fifo", this);
@@ -707,7 +717,7 @@
`uvm_info({`gfn, "::process_completed_trans()"},
$sformatf("Checking SRAM memory transaction: %0p", trans),
- UVM_HIGH)
+ UVM_MEDIUM)
check_mem_trans(trans);
end
