commit 2df95612856b8f39db2cea5a2989720d46424982
author Timothy Chen <timothytim@google.com> Mon Aug 31 15:29:12 2020 -0700
committer tjaychen <timothytim@google.com> Fri Sep 11 10:29:02 2020 -0700
tree 491d627c4f630680b2301d3648e1c10ae8843d64
parent e6309eccbec847da73b8aa990a233575f7a949e4

[flash_ctrl] Minor fixes

- fix seed page parameter construction
- fix address mistmatch between hardware interface and software

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv

diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
index adaaab6..2ebc1bc 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_lcmgr.sv
@@ -12,7 +12,7 @@
   // interface to ctrl arb control ports
   output flash_ctrl_reg_pkg::flash_ctrl_reg2hw_control_reg_t ctrl_o,
   output logic req_o,
-  output logic [BusAddrW-1:0] addr_o,
+  output logic [top_pkg::TL_AW-1:0] addr_o,
   input done_i,
   input err_i,
 
@@ -290,7 +290,8 @@
   assign ctrl_o.erase_sel.q = erase_type;
   assign ctrl_o.partition_sel.q = part_sel;
   assign ctrl_o.num = num_words;
-  assign addr_o = addr;
+  // address is consistent with software width format (full bus)
+  assign addr_o = top_pkg::TL_AW'({addr, {BusByteWidth{1'b0}}});
   assign init_busy_o = seed_phase;
   assign req_o = seed_phase | rma_phase;
   assign rready_o = 1'b1;