[entropy_src/rtl] fixes to address issue #3511
Added ERR_CODE register and supporting logic.
General style cleanup.
Doc signal typo fixed.
Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
diff --git a/hw/ip/entropy_src/rtl/entropy_src.sv b/hw/ip/entropy_src/rtl/entropy_src.sv
index 9b2546d..15c135e 100755
--- a/hw/ip/entropy_src/rtl/entropy_src.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src.sv
@@ -7,17 +7,17 @@
module entropy_src import entropy_src_pkg::*; #(
parameter logic AlertAsyncOn = 1,
- parameter int unsigned EsFifoDepth = 2
+ parameter int EsFifoDepth = 2
) (
- input clk_i,
- input rst_ni,
+ input logic clk_i,
+ input logic rst_ni,
// Bus Interface
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
// Efuse Interface
- input efuse_es_sw_reg_en_i,
+ input logic efuse_es_sw_reg_en_i,
// Entropy Interface
input entropy_src_hw_if_req_t entropy_src_hw_if_i,
diff --git a/hw/ip/entropy_src/rtl/entropy_src_ack_sm.sv b/hw/ip/entropy_src/rtl/entropy_src_ack_sm.sv
index 66286f0..620b491 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_ack_sm.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_ack_sm.sv
@@ -37,9 +37,9 @@
AckWait = 6'b111000 // wait until the fifo has an entry
} state_e;
- state_e state_d;
+ state_e state_d, state_q;
- logic [StateWidth-1:0] state_q;
+ logic [StateWidth-1:0] state_raw_q;
// This primitive is used to place a size-only constraint on the
// flops in order to prevent FSM state encoding optimizations.
@@ -51,11 +51,13 @@
.clk_i,
.rst_ni,
.d_i ( state_d ),
- .q_o ( state_q )
+ .q_o ( state_raw_q )
);
+ assign state_q = state_e'(state_raw_q);
+
always_comb begin
- state_d = state_e'(state_q);
+ state_d = state_q;
ack_o = 1'b0;
fifo_pop_o = 1'b0;
unique case (state_q)
diff --git a/hw/ip/entropy_src/rtl/entropy_src_adaptp_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_adaptp_ht.sv
index 8dcb680..65a734a 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_adaptp_ht.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_adaptp_ht.sv
@@ -6,11 +6,11 @@
//
module entropy_src_adaptp_ht #(
- parameter int unsigned RegWidth = 16,
- parameter int unsigned RngBusWidth = 4
+ parameter int RegWidth = 16,
+ parameter int RngBusWidth = 4
) (
- input clk_i,
- input rst_ni,
+ input logic clk_i,
+ input logic rst_ni,
// ins req interface
input logic [RngBusWidth-1:0] entropy_bit_i,
@@ -19,27 +19,22 @@
input logic active_i,
input logic [RegWidth-1:0] thresh_hi_i,
input logic [RegWidth-1:0] thresh_lo_i,
- input logic [RegWidth-1:0] window_i,
+ input logic window_wrap_pulse_i,
output logic [RegWidth-1:0] test_cnt_o,
- output logic test_done_pulse_o,
output logic test_fail_hi_pulse_o,
output logic test_fail_lo_pulse_o
);
// signals
logic [RegWidth-1:0] column_cnt;
- logic window_cntr_wrap;
// flops
- logic [RegWidth-1:0] window_cntr_q, window_cntr_d;
logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
always_ff @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
- window_cntr_q <= '0;
test_cnt_q <= '0;
end else begin
- window_cntr_q <= window_cntr_d;
test_cnt_q <= test_cnt_d;
end
@@ -54,32 +49,21 @@
// Number of ones per column
- assign column_cnt = RngBusWidth'(entropy_bit_i[3]) +
- RngBusWidth'(entropy_bit_i[2]) +
- RngBusWidth'(entropy_bit_i[1]) +
- RngBusWidth'(entropy_bit_i[0]);
-
- // Window wrap condition
- assign window_cntr_wrap = (window_cntr_q == window_i);
-
- // Window counter
- assign window_cntr_d =
- clear_i ? '0 :
- window_cntr_wrap ? '0 :
- entropy_bit_vld_i ? (window_cntr_q+1) :
- window_cntr_q;
+ assign column_cnt = RegWidth'(entropy_bit_i[3]) +
+ RegWidth'(entropy_bit_i[2]) +
+ RegWidth'(entropy_bit_i[1]) +
+ RegWidth'(entropy_bit_i[0]);
// Test event counter
assign test_cnt_d =
(!active_i || clear_i) ? '0 :
- window_cntr_wrap ? '0 :
+ window_wrap_pulse_i ? '0 :
entropy_bit_vld_i ? (test_cnt_q+column_cnt) :
test_cnt_q;
// the pulses will be only one clock in length
- assign test_fail_hi_pulse_o = active_i && window_cntr_wrap && (test_cnt_q > thresh_hi_i);
- assign test_fail_lo_pulse_o = active_i && window_cntr_wrap && (test_cnt_q < thresh_lo_i);
- assign test_done_pulse_o = window_cntr_wrap;
+ assign test_fail_hi_pulse_o = active_i && window_wrap_pulse_i && (test_cnt_q > thresh_hi_i);
+ assign test_fail_lo_pulse_o = active_i && window_wrap_pulse_i && (test_cnt_q < thresh_lo_i);
assign test_cnt_o = test_cnt_q;
diff --git a/hw/ip/entropy_src/rtl/entropy_src_bucket_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_bucket_ht.sv
index ebe15f4..f986d4f 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_bucket_ht.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_bucket_ht.sv
@@ -6,11 +6,11 @@
//
module entropy_src_bucket_ht #(
- parameter int unsigned RegWidth = 16,
- parameter int unsigned RngBusWidth = 4
+ parameter int RegWidth = 16,
+ parameter int RngBusWidth = 4
) (
- input clk_i,
- input rst_ni,
+ input logic clk_i,
+ input logic rst_ni,
// ins req interface
input logic [RngBusWidth-1:0] entropy_bit_i,
@@ -18,31 +18,26 @@
input logic clear_i,
input logic active_i,
input logic [RegWidth-1:0] thresh_i,
- input logic [RegWidth-1:0] window_i,
+ input logic window_wrap_pulse_i,
output logic [RegWidth-1:0] test_cnt_o,
- output logic test_done_pulse_o,
output logic test_fail_pulse_o
);
localparam int NUM_BINS = 2**RngBusWidth;
// signals
- logic window_cntr_wrap;
logic [NUM_BINS-1:0] bin_incr;
logic [NUM_BINS-1:0] bin_cnt_exceeds_thresh;
// flops
- logic [RegWidth-1:0] window_cntr_q, window_cntr_d;
logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
logic [RegWidth-1:0] bin_cntr_q[NUM_BINS], bin_cntr_d[NUM_BINS];
always_ff @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
- window_cntr_q <= '0;
test_cnt_q <= '0;
bin_cntr_q <= '{default:0};
end else begin
- window_cntr_q <= window_cntr_d;
test_cnt_q <= test_cnt_d;
bin_cntr_q <= bin_cntr_d;
end
@@ -63,33 +58,21 @@
// set the bin incrementer if the symbol matches that bin
assign bin_incr[i] = entropy_bit_vld_i && (entropy_bit_i == i);
// use the bin incrementer to increase the bin total count
- assign bin_cntr_d[i] = window_cntr_wrap ? '0 :
+ assign bin_cntr_d[i] = window_wrap_pulse_i ? '0 :
((active_i && bin_incr[i]) ? (bin_cntr_q[i]+1) : bin_cntr_q[i]);
// use the bin incrementer to increase the bin total count
assign bin_cnt_exceeds_thresh[i] = (bin_cntr_q[i] > thresh_i);
end : gen_symbol_match
-
- // Window wrap condition
- assign window_cntr_wrap = (window_cntr_q == window_i);
-
- // Window counter
- assign window_cntr_d =
- clear_i ? '0 :
- window_cntr_wrap ? '0 :
- entropy_bit_vld_i ? (window_cntr_q+1) :
- window_cntr_q;
-
// Test event counter
assign test_cnt_d =
(!active_i || clear_i) ? '0 :
- window_cntr_wrap ? '0 :
+ window_wrap_pulse_i ? '0 :
entropy_bit_vld_i && (|bin_cnt_exceeds_thresh) ? (test_cnt_q+1) :
test_cnt_q;
// the pulses will be only one clock in length
- assign test_fail_pulse_o = active_i && window_cntr_wrap && (test_cnt_q > '0);
- assign test_done_pulse_o = window_cntr_wrap;
+ assign test_fail_pulse_o = active_i && window_wrap_pulse_i && (test_cnt_q > '0);
assign test_cnt_o = test_cnt_q;
diff --git a/hw/ip/entropy_src/rtl/entropy_src_cntr_reg.sv b/hw/ip/entropy_src/rtl/entropy_src_cntr_reg.sv
index 4846829..98fe35d 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_cntr_reg.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_cntr_reg.sv
@@ -6,7 +6,7 @@
//
module entropy_src_cntr_reg #(
- parameter int unsigned RegWidth = 16
+ parameter int RegWidth = 16
) (
input logic clk_i,
input logic rst_ni,
diff --git a/hw/ip/entropy_src/rtl/entropy_src_core.sv b/hw/ip/entropy_src/rtl/entropy_src_core.sv
index 87d2178..3ab22c3 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_core.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_core.sv
@@ -6,16 +6,16 @@
//
module entropy_src_core import entropy_src_pkg::*; #(
- parameter int unsigned EsFifoDepth = 2
+ parameter int EsFifoDepth = 2
) (
- input clk_i,
- input rst_ni,
+ input logic clk_i,
+ input logic rst_ni,
input entropy_src_reg_pkg::entropy_src_reg2hw_t reg2hw,
output entropy_src_reg_pkg::entropy_src_hw2reg_t hw2reg,
// Efuse Interface
- input efuse_es_sw_reg_en_i,
+ input logic efuse_es_sw_reg_en_i,
// Entropy Interface
@@ -40,13 +40,13 @@
import entropy_src_reg_pkg::*;
- localparam int unsigned Clog2EsFifoDepth = $clog2(EsFifoDepth);
- localparam int unsigned PostHTWidth = 64;
- localparam int unsigned RngBusWidth = 4;
- localparam int unsigned HalfRegWidth = 16;
- localparam int unsigned FullRegWidth = 32;
- localparam int unsigned EigthRegWidth = 4;
- localparam int unsigned SeedLen = 384;
+ localparam int Clog2EsFifoDepth = $clog2(EsFifoDepth);
+ localparam int PostHTWidth = 64;
+ localparam int RngBusWidth = 4;
+ localparam int HalfRegWidth = 16;
+ localparam int FullRegWidth = 32;
+ localparam int EigthRegWidth = 4;
+ localparam int SeedLen = 384;
// signals
logic [RngBusWidth-1:0] lfsr_value;
@@ -72,8 +72,9 @@
logic sfifo_esrng_push;
logic sfifo_esrng_pop;
logic sfifo_esrng_clr;
+ logic sfifo_esrng_not_full;
logic sfifo_esrng_not_empty;
- logic sfifo_esrng_err;
+ logic [2:0] sfifo_esrng_err;
logic [Clog2EsFifoDepth:0] sfifo_esfinal_depth;
logic [(1+SeedLen)-1:0] sfifo_esfinal_wdata;
@@ -83,7 +84,7 @@
logic sfifo_esfinal_clr;
logic sfifo_esfinal_not_full;
logic sfifo_esfinal_not_empty;
- logic sfifo_esfinal_err;
+ logic [2:0] sfifo_esfinal_err;
logic [SeedLen-1:0] esfinal_data;
logic esfinal_fips_flag;
@@ -153,15 +154,24 @@
logic [EigthRegWidth-1:0] bucket_fail_count;
logic bucket_fail_pulse;
- logic [HalfRegWidth-1:0] markov_fips_threshold;
- logic [HalfRegWidth-1:0] markov_bypass_threshold;
- logic [HalfRegWidth-1:0] markov_threshold;
- logic [HalfRegWidth-1:0] markov_event_cnt;
- logic [HalfRegWidth-1:0] markov_event_hwm_fips;
- logic [HalfRegWidth-1:0] markov_event_hwm_bypass;
- logic [FullRegWidth-1:0] markov_total_fails;
- logic [EigthRegWidth-1:0] markov_fail_count;
- logic markov_fail_pulse;
+ logic [HalfRegWidth-1:0] markov_hi_fips_threshold;
+ logic [HalfRegWidth-1:0] markov_hi_bypass_threshold;
+ logic [HalfRegWidth-1:0] markov_hi_threshold;
+ logic [HalfRegWidth-1:0] markov_lo_fips_threshold;
+ logic [HalfRegWidth-1:0] markov_lo_bypass_threshold;
+ logic [HalfRegWidth-1:0] markov_lo_threshold;
+ logic [HalfRegWidth-1:0] markov_hi_event_cnt;
+ logic [HalfRegWidth-1:0] markov_lo_event_cnt;
+ logic [HalfRegWidth-1:0] markov_hi_event_hwm_fips;
+ logic [HalfRegWidth-1:0] markov_hi_event_hwm_bypass;
+ logic [HalfRegWidth-1:0] markov_lo_event_hwm_fips;
+ logic [HalfRegWidth-1:0] markov_lo_event_hwm_bypass;
+ logic [FullRegWidth-1:0] markov_hi_total_fails;
+ logic [FullRegWidth-1:0] markov_lo_total_fails;
+ logic [EigthRegWidth-1:0] markov_hi_fail_count;
+ logic [EigthRegWidth-1:0] markov_lo_fail_count;
+ logic markov_hi_fail_pulse;
+ logic markov_lo_fail_pulse;
logic [HalfRegWidth-1:0] extht_hi_fips_threshold;
logic [HalfRegWidth-1:0] extht_hi_bypass_threshold;
@@ -231,6 +241,7 @@
logic ht_esbus_vld_dly2_q, ht_esbus_vld_dly2_d;
logic boot_bypass_q, boot_bypass_d;
logic ht_failed_q, ht_failed_d;
+ logic [HalfRegWidth-1:0] window_cntr_q, window_cntr_d;
always_ff @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
@@ -241,6 +252,7 @@
ht_esbus_dly_q <= '0;
ht_esbus_vld_dly_q <= '0;
ht_esbus_vld_dly2_q <= '0;
+ window_cntr_q <= '0;
end else begin
es_rate_cntr_q <= es_rate_cntr_d;
lfsr_incr_dly_q <= lfsr_incr_dly_d;
@@ -249,6 +261,7 @@
ht_esbus_dly_q <= ht_esbus_dly_d;
ht_esbus_vld_dly_q <= ht_esbus_vld_dly_d;
ht_esbus_vld_dly2_q <= ht_esbus_vld_dly2_d;
+ window_cntr_q <= window_cntr_d;
end
assign es_enable = (|reg2hw.conf.enable.q);
@@ -361,8 +374,36 @@
// set the interrupt event when enabled
assign event_es_entropy_valid = pfifo_swread_not_empty;
+
// set the interrupt sources
- assign event_es_fifo_err = sfifo_esrng_err || sfifo_esfinal_err;
+ assign event_es_fifo_err =
+ (|sfifo_esrng_err) ||
+ (sfifo_esfinal_err);
+
+ // set the err code source bits
+ assign hw2reg.err_code.sfifo_esrng_err.d = 1'b1;
+ assign hw2reg.err_code.sfifo_esrng_err.de = (|sfifo_esrng_err);
+
+ assign hw2reg.err_code.sfifo_esfinal_err.d = 1'b1;
+ assign hw2reg.err_code.sfifo_esfinal_err.de = (|sfifo_esfinal_err);
+
+
+ // set the err code type bits
+ assign hw2reg.err_code.fifo_write_err.d = 1'b1;
+ assign hw2reg.err_code.fifo_write_err.de =
+ sfifo_esrng_err[2] ||
+ sfifo_esfinal_err[2];
+
+ assign hw2reg.err_code.fifo_read_err.d = 1'b1;
+ assign hw2reg.err_code.fifo_read_err.de =
+ sfifo_esrng_err[1] ||
+ sfifo_esfinal_err[1];
+
+ assign hw2reg.err_code.fifo_state_err.d = 1'b1;
+ assign hw2reg.err_code.fifo_state_err.de =
+ sfifo_esrng_err[0] ||
+ sfifo_esfinal_err[0];
+
// set the debug status reg
assign hw2reg.debug_status.entropy_fifo_depth.d = sfifo_esfinal_depth;
@@ -382,7 +423,7 @@
.clr_i (sfifo_esrng_clr),
.wvalid_i (sfifo_esrng_push),
.wdata_i (sfifo_esrng_wdata),
- .wready_o (),
+ .wready_o (sfifo_esrng_not_full),
.rvalid_o (sfifo_esrng_not_empty),
.rdata_o (sfifo_esrng_rdata),
.rready_i (sfifo_esrng_pop),
@@ -401,7 +442,9 @@
// fifo err
assign sfifo_esrng_err =
- (sfifo_esrng_pop && !sfifo_esrng_not_empty );
+ {1'b0,
+ (sfifo_esrng_pop && !sfifo_esrng_not_empty),
+ (!sfifo_esrng_not_full && !sfifo_esrng_not_empty)};
// pack esrng bus into signal bit packer
@@ -462,17 +505,24 @@
assign repcnt_fips_threshold = reg2hw.repcnt_thresholds.fips_repcnt_thresh.q;
assign repcnt_bypass_threshold = reg2hw.repcnt_thresholds.bypass_repcnt_thresh.q;
+
assign adaptp_hi_fips_threshold = reg2hw.adaptp_hi_thresholds.fips_adaptp_hi_thresh.q;
assign adaptp_hi_bypass_threshold = reg2hw.adaptp_hi_thresholds.bypass_adaptp_hi_thresh.q;
assign adaptp_lo_fips_threshold = reg2hw.adaptp_lo_thresholds.fips_adaptp_lo_thresh.q;
assign adaptp_lo_bypass_threshold = reg2hw.adaptp_lo_thresholds.bypass_adaptp_lo_thresh.q;
+
assign bucket_fips_threshold = reg2hw.bucket_thresholds.fips_bucket_thresh.q;
assign bucket_bypass_threshold = reg2hw.bucket_thresholds.bypass_bucket_thresh.q;
- assign markov_fips_threshold = reg2hw.markov_thresholds.fips_markov_thresh.q;
- assign markov_bypass_threshold = reg2hw.markov_thresholds.bypass_markov_thresh.q;
+
+ assign markov_hi_fips_threshold = reg2hw.markov_hi_thresholds.fips_markov_hi_thresh.q;
+ assign markov_hi_bypass_threshold = reg2hw.markov_hi_thresholds.bypass_markov_hi_thresh.q;
+
+ assign markov_lo_fips_threshold = reg2hw.markov_lo_thresholds.fips_markov_lo_thresh.q;
+ assign markov_lo_bypass_threshold = reg2hw.markov_lo_thresholds.bypass_markov_lo_thresh.q;
+
assign extht_hi_fips_threshold = reg2hw.extht_hi_thresholds.fips_extht_hi_thresh.q;
assign extht_hi_bypass_threshold = reg2hw.extht_hi_thresholds.bypass_extht_hi_thresh.q;
@@ -488,7 +538,10 @@
assign adaptp_lo_threshold = es_bypass_mode ? adaptp_lo_bypass_threshold :
adaptp_lo_fips_threshold;
assign bucket_threshold = es_bypass_mode ? bucket_bypass_threshold : bucket_fips_threshold;
- assign markov_threshold = es_bypass_mode ? markov_bypass_threshold : markov_fips_threshold;
+ assign markov_hi_threshold = es_bypass_mode ? markov_hi_bypass_threshold :
+ markov_hi_fips_threshold;
+ assign markov_lo_threshold = es_bypass_mode ? markov_lo_bypass_threshold :
+ markov_lo_fips_threshold;
assign extht_hi_threshold = es_bypass_mode ? extht_hi_bypass_threshold :
extht_hi_fips_threshold;
assign extht_lo_threshold = es_bypass_mode ? extht_lo_bypass_threshold :
@@ -508,6 +561,20 @@
assign es_bypass_mode = boot_bypass_q || es_bypass_to_sw;
//--------------------------------------------
+ // common health test window counter
+ //--------------------------------------------
+
+ // Window counter
+ assign window_cntr_d =
+ health_test_clr ? '0 :
+ health_test_done_pulse ? '0 :
+ health_test_esbus_vld ? (window_cntr_q+1) :
+ window_cntr_q;
+
+ // Window wrap condition
+ assign health_test_done_pulse = (window_cntr_q == health_test_window);
+
+ //--------------------------------------------
// repetitive count test
//--------------------------------------------
@@ -522,9 +589,7 @@
.clear_i (health_test_clr),
.active_i (repcnt_active),
.thresh_i (repcnt_threshold),
- .window_i (health_test_window),
.test_cnt_o (repcnt_event_cnt),
- .test_done_pulse_o (health_test_done_pulse),
.test_fail_pulse_o (repcnt_fail_pulse)
);
@@ -585,9 +650,8 @@
.active_i (adaptp_active),
.thresh_hi_i (adaptp_hi_threshold),
.thresh_lo_i (adaptp_lo_threshold),
- .window_i (health_test_window),
+ .window_wrap_pulse_i (health_test_done_pulse),
.test_cnt_o (adaptp_event_cnt),
- .test_done_pulse_o (), // NC
.test_fail_hi_pulse_o(adaptp_hi_fail_pulse),
.test_fail_lo_pulse_o(adaptp_lo_fail_pulse)
);
@@ -693,10 +757,9 @@
.clear_i (health_test_clr),
.active_i (bucket_active),
.thresh_i (bucket_threshold),
- .window_i (health_test_window),
+ .window_wrap_pulse_i (health_test_done_pulse),
.test_cnt_o (bucket_event_cnt),
- .test_done_pulse_o (), // NC
- .test_fail_pulse_o (bucket_fail_pulse)
+ .test_fail_pulse_o (bucket_fail_pulse)
);
entropy_src_watermark_reg #(
@@ -755,53 +818,97 @@
.entropy_bit_vld_i (health_test_esbus_vld),
.clear_i (health_test_clr),
.active_i (markov_active),
- .thresh_i (markov_threshold),
- .window_i (health_test_window),
- .test_cnt_o (markov_event_cnt),
- .test_done_pulse_o (),// NC
- .test_fail_pulse_o (markov_fail_pulse)
+ .thresh_hi_i (markov_hi_threshold),
+ .thresh_lo_i (markov_lo_threshold),
+ .window_wrap_pulse_i (health_test_done_pulse),
+ .test_cnt_hi_o (markov_hi_event_cnt),
+ .test_cnt_lo_o (markov_lo_event_cnt),
+ .test_fail_hi_pulse_o (markov_hi_fail_pulse),
+ .test_fail_lo_pulse_o (markov_lo_fail_pulse)
);
entropy_src_watermark_reg #(
.RegWidth(HalfRegWidth),
.HighWatermark(1)
- ) u_entropy_src_watermark_reg_markov_fips (
+ ) u_entropy_src_watermark_reg_markov_hi_fips (
.clk_i (clk_i),
.rst_ni (rst_ni),
.clear_i (health_test_clr),
.active_i (markov_active),
- .event_i (markov_fail_pulse && !es_bypass_mode),
- .value_i (markov_event_cnt),
- .value_o (markov_event_hwm_fips)
+ .event_i (markov_hi_fail_pulse && !es_bypass_mode),
+ .value_i (markov_hi_event_cnt),
+ .value_o (markov_hi_event_hwm_fips)
);
entropy_src_watermark_reg #(
.RegWidth(HalfRegWidth),
.HighWatermark(1)
- ) u_entropy_src_watermark_reg_markov_bypass (
+ ) u_entropy_src_watermark_reg_markov_hi_bypass (
.clk_i (clk_i),
.rst_ni (rst_ni),
.clear_i (health_test_clr),
.active_i (markov_active),
- .event_i (markov_fail_pulse && es_bypass_mode),
- .value_i (markov_event_cnt),
- .value_o (markov_event_hwm_bypass)
+ .event_i (markov_hi_fail_pulse && es_bypass_mode),
+ .value_i (markov_hi_event_cnt),
+ .value_o (markov_hi_event_hwm_bypass)
);
entropy_src_cntr_reg #(
.RegWidth(FullRegWidth)
- ) u_entropy_src_cntr_reg_markov (
+ ) u_entropy_src_cntr_reg_markov_hi (
.clk_i (clk_i),
.rst_ni (rst_ni),
.clear_i (health_test_clr),
.active_i (markov_active),
- .event_i (markov_fail_pulse),
- .value_o (markov_total_fails)
+ .event_i (markov_hi_fail_pulse),
+ .value_o (markov_hi_total_fails)
);
- assign hw2reg.markov_hi_watermarks.fips_markov_hi_watermark.d = markov_event_hwm_fips;
- assign hw2reg.markov_hi_watermarks.bypass_markov_hi_watermark.d = markov_event_hwm_bypass;
- assign hw2reg.markov_total_fails.d = markov_total_fails;
+ assign hw2reg.markov_hi_watermarks.fips_markov_hi_watermark.d = markov_hi_event_hwm_fips;
+ assign hw2reg.markov_hi_watermarks.bypass_markov_hi_watermark.d = markov_hi_event_hwm_bypass;
+ assign hw2reg.markov_hi_total_fails.d = markov_hi_total_fails;
+
+
+ entropy_src_watermark_reg #(
+ .RegWidth(HalfRegWidth),
+ .HighWatermark(1)
+ ) u_entropy_src_watermark_reg_markov_lo_fips (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (markov_active),
+ .event_i (markov_lo_fail_pulse && !es_bypass_mode),
+ .value_i (markov_lo_event_cnt),
+ .value_o (markov_lo_event_hwm_fips)
+ );
+
+ entropy_src_watermark_reg #(
+ .RegWidth(HalfRegWidth),
+ .HighWatermark(1)
+ ) u_entropy_src_watermark_reg_markov_lo_bypass (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (markov_active),
+ .event_i (markov_lo_fail_pulse && es_bypass_mode),
+ .value_i (markov_lo_event_cnt),
+ .value_o (markov_lo_event_hwm_bypass)
+ );
+
+ entropy_src_cntr_reg #(
+ .RegWidth(FullRegWidth)
+ ) u_entropy_src_cntr_reg_markov_lo (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (health_test_clr),
+ .active_i (markov_active),
+ .event_i (markov_lo_fail_pulse),
+ .value_o (markov_lo_total_fails)
+ );
+
+ assign hw2reg.markov_lo_watermarks.fips_markov_lo_watermark.d = markov_lo_event_hwm_fips;
+ assign hw2reg.markov_lo_watermarks.bypass_markov_lo_watermark.d = markov_lo_event_hwm_bypass;
+ assign hw2reg.markov_lo_total_fails.d = markov_lo_total_fails;
//--------------------------------------------
@@ -925,9 +1032,15 @@
.value_o (any_fail_count)
);
- assign any_active = repcnt_active || adaptp_active || bucket_active || markov_active;
- assign any_fail_pulse = repcnt_fail_pulse || adaptp_hi_fail_pulse || adaptp_lo_fail_pulse ||
- bucket_fail_pulse || markov_fail_pulse;
+ assign any_active = repcnt_active || adaptp_active ||
+ bucket_active || markov_active || extht_active;
+
+ assign any_fail_pulse =
+ repcnt_fail_pulse ||
+ adaptp_hi_fail_pulse || adaptp_lo_fail_pulse ||
+ bucket_fail_pulse ||
+ markov_hi_fail_pulse ||markov_lo_fail_pulse ||
+ extht_hi_fail_pulse || extht_lo_fail_pulse;
assign ht_failed_d = sfifo_esfinal_push ? 1'b0 :
@@ -1002,19 +1115,32 @@
assign hw2reg.alert_fail_counts.bucket_fail_count.d = bucket_fail_count;
- // markov fail counter
+ // markov fail counter hi and lo
entropy_src_cntr_reg #(
.RegWidth(EigthRegWidth)
- ) u_entropy_src_cntr_reg_markov_alert_fails (
+ ) u_entropy_src_cntr_reg_markov_alert_hi_fails (
.clk_i (clk_i),
.rst_ni (rst_ni),
.clear_i (alert_cntrs_clr),
.active_i (markov_active),
- .event_i (markov_fail_pulse),
- .value_o (markov_fail_count)
+ .event_i (markov_hi_fail_pulse),
+ .value_o (markov_hi_fail_count)
);
- assign hw2reg.alert_fail_counts.markov_fail_count.d = markov_fail_count;
+ assign hw2reg.alert_fail_counts.markov_hi_fail_count.d = markov_hi_fail_count;
+
+ entropy_src_cntr_reg #(
+ .RegWidth(EigthRegWidth)
+ ) u_entropy_src_cntr_reg_markov_alert_lo_fails (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .clear_i (alert_cntrs_clr),
+ .active_i (markov_active),
+ .event_i (markov_lo_fail_pulse),
+ .value_o (markov_lo_fail_count)
+ );
+
+ assign hw2reg.alert_fail_counts.markov_lo_fail_count.d = markov_lo_fail_count;
// extht fail counter hi and lo
entropy_src_cntr_reg #(
@@ -1190,8 +1316,9 @@
// fifo err
assign sfifo_esfinal_err =
- (sfifo_esfinal_push && !sfifo_esfinal_not_full) |
- (sfifo_esfinal_pop && !sfifo_esfinal_not_empty );
+ {(sfifo_esfinal_push && !sfifo_esfinal_not_full),
+ (sfifo_esfinal_pop && !sfifo_esfinal_not_empty),
+ (!sfifo_esfinal_not_full && !sfifo_esfinal_not_empty)};
// drive out hw interface
assign es_hw_if_req = entropy_src_hw_if_i.es_req;
diff --git a/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv b/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
index 6435b1b..a944777 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
@@ -50,9 +50,9 @@
NormalMode = 8'b11001000 // in normal mode
} state_e;
- state_e state_d;
+ state_e state_d, state_q;
- logic [StateWidth-1:0] state_q;
+ logic [StateWidth-1:0] state_raw_q;
// This primitive is used to place a size-only constraint on the
// flops in order to prevent FSM state encoding optimizations.
@@ -63,11 +63,13 @@
.clk_i,
.rst_ni,
.d_i ( state_d ),
- .q_o ( state_q )
+ .q_o ( state_raw_q )
);
+ assign state_q = state_e'(state_raw_q);
+
always_comb begin
- state_d = state_e'(state_q);
+ state_d = state_q;
rst_bypass_mode_o = 1'b0;
rst_alert_cntr_o = 1'b0;
main_stage_pop_o = 1'b0;
diff --git a/hw/ip/entropy_src/rtl/entropy_src_markov_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_markov_ht.sv
index 29fabd2..a2bafa3 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_markov_ht.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_markov_ht.sv
@@ -6,46 +6,49 @@
//
module entropy_src_markov_ht #(
- parameter int unsigned RegWidth = 16,
- parameter int unsigned RngBusWidth = 4
+ parameter int RegWidth = 16,
+ parameter int RngBusWidth = 4
) (
- input clk_i,
- input rst_ni,
+ input logic clk_i,
+ input logic rst_ni,
// ins req interface
input logic [RngBusWidth-1:0] entropy_bit_i,
input logic entropy_bit_vld_i,
input logic clear_i,
input logic active_i,
- input logic [RegWidth-1:0] thresh_i,
- input logic [RegWidth-1:0] window_i,
- output logic [RegWidth-1:0] test_cnt_o,
- output logic test_done_pulse_o,
- output logic test_fail_pulse_o
+ input logic [RegWidth-1:0] thresh_hi_i,
+ input logic [RegWidth-1:0] thresh_lo_i,
+ input logic window_wrap_pulse_i,
+ output logic [RegWidth-1:0] test_cnt_hi_o,
+ output logic [RegWidth-1:0] test_cnt_lo_o,
+ output logic test_fail_hi_pulse_o,
+ output logic test_fail_lo_pulse_o
);
// signals
- logic window_cntr_wrap;
logic [RngBusWidth-1:0] samples_no_match_pulse;
- logic [RngBusWidth-1:0] pair_cnt_fail;
+ logic [RegWidth-1:0] pair_cntr_gt1;
+ logic [RegWidth-1:0] pair_cntr_gt2;
+ logic [RegWidth-1:0] pair_cntr_gt3;
+ logic [RegWidth-1:0] pair_cntr_lt1;
+ logic [RegWidth-1:0] pair_cntr_lt2;
+ logic [RegWidth-1:0] pair_cntr_lt3;
// flops
+ logic toggle_q, toggle_d;
logic [RngBusWidth-1:0] prev_sample_q, prev_sample_d;
logic [RegWidth-1:0] pair_cntr_q[RngBusWidth], pair_cntr_d[RngBusWidth];
- logic [RegWidth-1:0] window_cntr_q, window_cntr_d;
- logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
always_ff @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
+ toggle_q <= '0;
prev_sample_q <= '0;
pair_cntr_q <= '{default:0};
- window_cntr_q <= '0;
- test_cnt_q <= '0;
end else begin
+ toggle_q <= toggle_d;
prev_sample_q <= prev_sample_d;
pair_cntr_q <= pair_cntr_d;
- window_cntr_q <= window_cntr_d;
- test_cnt_q <= test_cnt_d;
end
@@ -60,47 +63,47 @@
// bit sampler
assign prev_sample_d[sh] = (!active_i || clear_i) ? '0 :
- window_cntr_wrap ? '0 :
+ window_wrap_pulse_i ? '0 :
entropy_bit_vld_i ? entropy_bit_i[sh] :
prev_sample_q[sh];
// pair check
- assign samples_no_match_pulse[sh] = entropy_bit_vld_i && window_cntr_q[0] &&
+ assign samples_no_match_pulse[sh] = entropy_bit_vld_i && toggle_q &&
(prev_sample_q[sh] == !entropy_bit_i[sh]);
// pair counter
assign pair_cntr_d[sh] =
(!active_i || clear_i) ? '0 :
- window_cntr_wrap ? '0 :
+ window_wrap_pulse_i ? '0 :
samples_no_match_pulse[sh] ? (pair_cntr_q[sh]+1) :
pair_cntr_q[sh];
- assign pair_cnt_fail[sh] = (pair_cntr_q[sh] >= thresh_i);
-
end : gen_cntrs
+ // create a toggle signal to sample pairs with
+ assign toggle_d =
+ (!active_i || clear_i) ? '0 :
+ window_wrap_pulse_i ? '0 :
+ entropy_bit_vld_i ? (!toggle_q) :
+ toggle_q;
- // Window wrap condition
- assign window_cntr_wrap = (window_cntr_q == window_i);
+ // determine the highest counter pair counter value
+ assign pair_cntr_gt1 = (pair_cntr_q[0] < pair_cntr_q[1]) ? pair_cntr_q[1] : pair_cntr_q[0];
+ assign pair_cntr_gt2 = (pair_cntr_gt1 < pair_cntr_q[2]) ? pair_cntr_q[2] : pair_cntr_gt1;
+ assign pair_cntr_gt3 = (pair_cntr_gt2 < pair_cntr_q[3]) ? pair_cntr_q[3] : pair_cntr_gt2;
- // Window counter
- assign window_cntr_d =
- clear_i ? '0 :
- window_cntr_wrap ? '0 :
- entropy_bit_vld_i ? (window_cntr_q+1) :
- window_cntr_q;
- // Test event counter
- assign test_cnt_d =
- (!active_i || clear_i) ? '0 :
- window_cntr_wrap ? '0 :
- entropy_bit_vld_i && (|pair_cnt_fail) ? (test_cnt_q+1) :
- test_cnt_q;
+ // determine the lowest counter pair counter value
+ assign pair_cntr_lt1 = (pair_cntr_q[0] > pair_cntr_q[1]) ? pair_cntr_q[1] : pair_cntr_q[0];
+ assign pair_cntr_lt2 = (pair_cntr_lt1 > pair_cntr_q[2]) ? pair_cntr_q[2] : pair_cntr_lt1;
+ assign pair_cntr_lt3 = (pair_cntr_lt2 > pair_cntr_q[3]) ? pair_cntr_q[3] : pair_cntr_lt2;
+
// the pulses will be only one clock in length
- assign test_fail_pulse_o = active_i && window_cntr_wrap && (test_cnt_q > '0);
- assign test_done_pulse_o = window_cntr_wrap;
- assign test_cnt_o = test_cnt_q;
+ assign test_fail_hi_pulse_o = active_i && window_wrap_pulse_i && (pair_cntr_gt3 > thresh_hi_i);
+ assign test_fail_lo_pulse_o = active_i && window_wrap_pulse_i && (pair_cntr_lt3 < thresh_lo_i);
+ assign test_cnt_hi_o = pair_cntr_gt3;
+ assign test_cnt_lo_o = pair_cntr_lt3;
endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
index b3b494d..7701949 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
@@ -160,11 +160,20 @@
typedef struct packed {
struct packed {
logic [15:0] q;
- } fips_markov_thresh;
+ } fips_markov_hi_thresh;
struct packed {
logic [15:0] q;
- } bypass_markov_thresh;
- } entropy_src_reg2hw_markov_thresholds_reg_t;
+ } bypass_markov_hi_thresh;
+ } entropy_src_reg2hw_markov_hi_thresholds_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [15:0] q;
+ } fips_markov_lo_thresh;
+ struct packed {
+ logic [15:0] q;
+ } bypass_markov_lo_thresh;
+ } entropy_src_reg2hw_markov_lo_thresholds_reg_t;
typedef struct packed {
struct packed {
@@ -276,6 +285,15 @@
} entropy_src_hw2reg_markov_hi_watermarks_reg_t;
typedef struct packed {
+ struct packed {
+ logic [15:0] d;
+ } fips_markov_lo_watermark;
+ struct packed {
+ logic [15:0] d;
+ } bypass_markov_lo_watermark;
+ } entropy_src_hw2reg_markov_lo_watermarks_reg_t;
+
+ typedef struct packed {
logic [31:0] d;
} entropy_src_hw2reg_repcnt_total_fails_reg_t;
@@ -293,7 +311,11 @@
typedef struct packed {
logic [31:0] d;
- } entropy_src_hw2reg_markov_total_fails_reg_t;
+ } entropy_src_hw2reg_markov_hi_total_fails_reg_t;
+
+ typedef struct packed {
+ logic [31:0] d;
+ } entropy_src_hw2reg_markov_lo_total_fails_reg_t;
typedef struct packed {
logic [31:0] d;
@@ -321,7 +343,10 @@
} bucket_fail_count;
struct packed {
logic [3:0] d;
- } markov_fail_count;
+ } markov_hi_fail_count;
+ struct packed {
+ logic [3:0] d;
+ } markov_lo_fail_count;
} entropy_src_hw2reg_alert_fail_counts_reg_t;
typedef struct packed {
@@ -342,26 +367,50 @@
} diag;
} entropy_src_hw2reg_debug_status_reg_t;
+ typedef struct packed {
+ struct packed {
+ logic d;
+ logic de;
+ } sfifo_esrng_err;
+ struct packed {
+ logic d;
+ logic de;
+ } sfifo_esfinal_err;
+ struct packed {
+ logic d;
+ logic de;
+ } fifo_write_err;
+ struct packed {
+ logic d;
+ logic de;
+ } fifo_read_err;
+ struct packed {
+ logic d;
+ logic de;
+ } fifo_state_err;
+ } entropy_src_hw2reg_err_code_reg_t;
+
///////////////////////////////////////
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- entropy_src_reg2hw_intr_state_reg_t intr_state; // [341:339]
- entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [338:336]
- entropy_src_reg2hw_intr_test_reg_t intr_test; // [335:330]
- entropy_src_reg2hw_alert_test_reg_t alert_test; // [329:328]
- entropy_src_reg2hw_regen_reg_t regen; // [327:327]
- entropy_src_reg2hw_conf_reg_t conf; // [326:315]
- entropy_src_reg2hw_rate_reg_t rate; // [314:299]
- entropy_src_reg2hw_entropy_control_reg_t entropy_control; // [298:297]
- entropy_src_reg2hw_entropy_data_reg_t entropy_data; // [296:264]
- entropy_src_reg2hw_health_test_windows_reg_t health_test_windows; // [263:232]
- entropy_src_reg2hw_repcnt_thresholds_reg_t repcnt_thresholds; // [231:200]
- entropy_src_reg2hw_adaptp_hi_thresholds_reg_t adaptp_hi_thresholds; // [199:168]
- entropy_src_reg2hw_adaptp_lo_thresholds_reg_t adaptp_lo_thresholds; // [167:136]
- entropy_src_reg2hw_bucket_thresholds_reg_t bucket_thresholds; // [135:104]
- entropy_src_reg2hw_markov_thresholds_reg_t markov_thresholds; // [103:72]
+ entropy_src_reg2hw_intr_state_reg_t intr_state; // [373:371]
+ entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [370:368]
+ entropy_src_reg2hw_intr_test_reg_t intr_test; // [367:362]
+ entropy_src_reg2hw_alert_test_reg_t alert_test; // [361:360]
+ entropy_src_reg2hw_regen_reg_t regen; // [359:359]
+ entropy_src_reg2hw_conf_reg_t conf; // [358:347]
+ entropy_src_reg2hw_rate_reg_t rate; // [346:331]
+ entropy_src_reg2hw_entropy_control_reg_t entropy_control; // [330:329]
+ entropy_src_reg2hw_entropy_data_reg_t entropy_data; // [328:296]
+ entropy_src_reg2hw_health_test_windows_reg_t health_test_windows; // [295:264]
+ entropy_src_reg2hw_repcnt_thresholds_reg_t repcnt_thresholds; // [263:232]
+ entropy_src_reg2hw_adaptp_hi_thresholds_reg_t adaptp_hi_thresholds; // [231:200]
+ entropy_src_reg2hw_adaptp_lo_thresholds_reg_t adaptp_lo_thresholds; // [199:168]
+ entropy_src_reg2hw_bucket_thresholds_reg_t bucket_thresholds; // [167:136]
+ entropy_src_reg2hw_markov_hi_thresholds_reg_t markov_hi_thresholds; // [135:104]
+ entropy_src_reg2hw_markov_lo_thresholds_reg_t markov_lo_thresholds; // [103:72]
entropy_src_reg2hw_extht_hi_thresholds_reg_t extht_hi_thresholds; // [71:40]
entropy_src_reg2hw_extht_lo_thresholds_reg_t extht_lo_thresholds; // [39:8]
entropy_src_reg2hw_alert_threshold_reg_t alert_threshold; // [7:4]
@@ -372,25 +421,28 @@
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- entropy_src_hw2reg_intr_state_reg_t intr_state; // [520:518]
- entropy_src_hw2reg_entropy_data_reg_t entropy_data; // [517:485]
- entropy_src_hw2reg_repcnt_hi_watermarks_reg_t repcnt_hi_watermarks; // [484:485]
- entropy_src_hw2reg_adaptp_hi_watermarks_reg_t adaptp_hi_watermarks; // [484:485]
- entropy_src_hw2reg_adaptp_lo_watermarks_reg_t adaptp_lo_watermarks; // [484:485]
- entropy_src_hw2reg_extht_hi_watermarks_reg_t extht_hi_watermarks; // [484:485]
- entropy_src_hw2reg_extht_lo_watermarks_reg_t extht_lo_watermarks; // [484:485]
- entropy_src_hw2reg_bucket_hi_watermarks_reg_t bucket_hi_watermarks; // [484:485]
- entropy_src_hw2reg_markov_hi_watermarks_reg_t markov_hi_watermarks; // [484:485]
- entropy_src_hw2reg_repcnt_total_fails_reg_t repcnt_total_fails; // [484:485]
- entropy_src_hw2reg_adaptp_hi_total_fails_reg_t adaptp_hi_total_fails; // [484:485]
- entropy_src_hw2reg_adaptp_lo_total_fails_reg_t adaptp_lo_total_fails; // [484:485]
- entropy_src_hw2reg_bucket_total_fails_reg_t bucket_total_fails; // [484:485]
- entropy_src_hw2reg_markov_total_fails_reg_t markov_total_fails; // [484:485]
- entropy_src_hw2reg_extht_hi_total_fails_reg_t extht_hi_total_fails; // [484:485]
- entropy_src_hw2reg_extht_lo_total_fails_reg_t extht_lo_total_fails; // [484:485]
- entropy_src_hw2reg_alert_fail_counts_reg_t alert_fail_counts; // [484:485]
- entropy_src_hw2reg_extht_fail_counts_reg_t extht_fail_counts; // [484:485]
- entropy_src_hw2reg_debug_status_reg_t debug_status; // [484:485]
+ entropy_src_hw2reg_intr_state_reg_t intr_state; // [598:596]
+ entropy_src_hw2reg_entropy_data_reg_t entropy_data; // [595:563]
+ entropy_src_hw2reg_repcnt_hi_watermarks_reg_t repcnt_hi_watermarks; // [562:563]
+ entropy_src_hw2reg_adaptp_hi_watermarks_reg_t adaptp_hi_watermarks; // [562:563]
+ entropy_src_hw2reg_adaptp_lo_watermarks_reg_t adaptp_lo_watermarks; // [562:563]
+ entropy_src_hw2reg_extht_hi_watermarks_reg_t extht_hi_watermarks; // [562:563]
+ entropy_src_hw2reg_extht_lo_watermarks_reg_t extht_lo_watermarks; // [562:563]
+ entropy_src_hw2reg_bucket_hi_watermarks_reg_t bucket_hi_watermarks; // [562:563]
+ entropy_src_hw2reg_markov_hi_watermarks_reg_t markov_hi_watermarks; // [562:563]
+ entropy_src_hw2reg_markov_lo_watermarks_reg_t markov_lo_watermarks; // [562:563]
+ entropy_src_hw2reg_repcnt_total_fails_reg_t repcnt_total_fails; // [562:563]
+ entropy_src_hw2reg_adaptp_hi_total_fails_reg_t adaptp_hi_total_fails; // [562:563]
+ entropy_src_hw2reg_adaptp_lo_total_fails_reg_t adaptp_lo_total_fails; // [562:563]
+ entropy_src_hw2reg_bucket_total_fails_reg_t bucket_total_fails; // [562:563]
+ entropy_src_hw2reg_markov_hi_total_fails_reg_t markov_hi_total_fails; // [562:563]
+ entropy_src_hw2reg_markov_lo_total_fails_reg_t markov_lo_total_fails; // [562:563]
+ entropy_src_hw2reg_extht_hi_total_fails_reg_t extht_hi_total_fails; // [562:563]
+ entropy_src_hw2reg_extht_lo_total_fails_reg_t extht_lo_total_fails; // [562:563]
+ entropy_src_hw2reg_alert_fail_counts_reg_t alert_fail_counts; // [562:563]
+ entropy_src_hw2reg_extht_fail_counts_reg_t extht_fail_counts; // [562:563]
+ entropy_src_hw2reg_debug_status_reg_t debug_status; // [562:563]
+ entropy_src_hw2reg_err_code_reg_t err_code; // [562:563]
} entropy_src_hw2reg_t;
// Register Address
@@ -409,28 +461,32 @@
parameter logic [7:0] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_OFFSET = 8'h 30;
parameter logic [7:0] ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_OFFSET = 8'h 34;
parameter logic [7:0] ENTROPY_SRC_BUCKET_THRESHOLDS_OFFSET = 8'h 38;
- parameter logic [7:0] ENTROPY_SRC_MARKOV_THRESHOLDS_OFFSET = 8'h 3c;
- parameter logic [7:0] ENTROPY_SRC_EXTHT_HI_THRESHOLDS_OFFSET = 8'h 40;
- parameter logic [7:0] ENTROPY_SRC_EXTHT_LO_THRESHOLDS_OFFSET = 8'h 44;
- parameter logic [7:0] ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET = 8'h 48;
- parameter logic [7:0] ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET = 8'h 4c;
- parameter logic [7:0] ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET = 8'h 50;
- parameter logic [7:0] ENTROPY_SRC_EXTHT_HI_WATERMARKS_OFFSET = 8'h 54;
- parameter logic [7:0] ENTROPY_SRC_EXTHT_LO_WATERMARKS_OFFSET = 8'h 58;
- parameter logic [7:0] ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET = 8'h 5c;
- parameter logic [7:0] ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET = 8'h 60;
- parameter logic [7:0] ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET = 8'h 64;
- parameter logic [7:0] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET = 8'h 68;
- parameter logic [7:0] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET = 8'h 6c;
- parameter logic [7:0] ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET = 8'h 70;
- parameter logic [7:0] ENTROPY_SRC_MARKOV_TOTAL_FAILS_OFFSET = 8'h 74;
- parameter logic [7:0] ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_OFFSET = 8'h 78;
- parameter logic [7:0] ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_OFFSET = 8'h 7c;
- parameter logic [7:0] ENTROPY_SRC_ALERT_THRESHOLD_OFFSET = 8'h 80;
- parameter logic [7:0] ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET = 8'h 84;
- parameter logic [7:0] ENTROPY_SRC_EXTHT_FAIL_COUNTS_OFFSET = 8'h 88;
- parameter logic [7:0] ENTROPY_SRC_DEBUG_STATUS_OFFSET = 8'h 8c;
- parameter logic [7:0] ENTROPY_SRC_SEED_OFFSET = 8'h 90;
+ parameter logic [7:0] ENTROPY_SRC_MARKOV_HI_THRESHOLDS_OFFSET = 8'h 3c;
+ parameter logic [7:0] ENTROPY_SRC_MARKOV_LO_THRESHOLDS_OFFSET = 8'h 40;
+ parameter logic [7:0] ENTROPY_SRC_EXTHT_HI_THRESHOLDS_OFFSET = 8'h 44;
+ parameter logic [7:0] ENTROPY_SRC_EXTHT_LO_THRESHOLDS_OFFSET = 8'h 48;
+ parameter logic [7:0] ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET = 8'h 4c;
+ parameter logic [7:0] ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET = 8'h 50;
+ parameter logic [7:0] ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET = 8'h 54;
+ parameter logic [7:0] ENTROPY_SRC_EXTHT_HI_WATERMARKS_OFFSET = 8'h 58;
+ parameter logic [7:0] ENTROPY_SRC_EXTHT_LO_WATERMARKS_OFFSET = 8'h 5c;
+ parameter logic [7:0] ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET = 8'h 60;
+ parameter logic [7:0] ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET = 8'h 64;
+ parameter logic [7:0] ENTROPY_SRC_MARKOV_LO_WATERMARKS_OFFSET = 8'h 68;
+ parameter logic [7:0] ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET = 8'h 6c;
+ parameter logic [7:0] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET = 8'h 70;
+ parameter logic [7:0] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET = 8'h 74;
+ parameter logic [7:0] ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET = 8'h 78;
+ parameter logic [7:0] ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_OFFSET = 8'h 7c;
+ parameter logic [7:0] ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_OFFSET = 8'h 80;
+ parameter logic [7:0] ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_OFFSET = 8'h 84;
+ parameter logic [7:0] ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_OFFSET = 8'h 88;
+ parameter logic [7:0] ENTROPY_SRC_ALERT_THRESHOLD_OFFSET = 8'h 8c;
+ parameter logic [7:0] ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET = 8'h 90;
+ parameter logic [7:0] ENTROPY_SRC_EXTHT_FAIL_COUNTS_OFFSET = 8'h 94;
+ parameter logic [7:0] ENTROPY_SRC_DEBUG_STATUS_OFFSET = 8'h 98;
+ parameter logic [7:0] ENTROPY_SRC_SEED_OFFSET = 8'h 9c;
+ parameter logic [7:0] ENTROPY_SRC_ERR_CODE_OFFSET = 8'h a0;
// Register Index
@@ -450,7 +506,8 @@
ENTROPY_SRC_ADAPTP_HI_THRESHOLDS,
ENTROPY_SRC_ADAPTP_LO_THRESHOLDS,
ENTROPY_SRC_BUCKET_THRESHOLDS,
- ENTROPY_SRC_MARKOV_THRESHOLDS,
+ ENTROPY_SRC_MARKOV_HI_THRESHOLDS,
+ ENTROPY_SRC_MARKOV_LO_THRESHOLDS,
ENTROPY_SRC_EXTHT_HI_THRESHOLDS,
ENTROPY_SRC_EXTHT_LO_THRESHOLDS,
ENTROPY_SRC_REPCNT_HI_WATERMARKS,
@@ -460,22 +517,25 @@
ENTROPY_SRC_EXTHT_LO_WATERMARKS,
ENTROPY_SRC_BUCKET_HI_WATERMARKS,
ENTROPY_SRC_MARKOV_HI_WATERMARKS,
+ ENTROPY_SRC_MARKOV_LO_WATERMARKS,
ENTROPY_SRC_REPCNT_TOTAL_FAILS,
ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS,
ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS,
ENTROPY_SRC_BUCKET_TOTAL_FAILS,
- ENTROPY_SRC_MARKOV_TOTAL_FAILS,
+ ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS,
+ ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS,
ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS,
ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS,
ENTROPY_SRC_ALERT_THRESHOLD,
ENTROPY_SRC_ALERT_FAIL_COUNTS,
ENTROPY_SRC_EXTHT_FAIL_COUNTS,
ENTROPY_SRC_DEBUG_STATUS,
- ENTROPY_SRC_SEED
+ ENTROPY_SRC_SEED,
+ ENTROPY_SRC_ERR_CODE
} entropy_src_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] ENTROPY_SRC_PERMIT [37] = '{
+ parameter logic [3:0] ENTROPY_SRC_PERMIT [41] = '{
4'b 0001, // index[ 0] ENTROPY_SRC_INTR_STATE
4'b 0001, // index[ 1] ENTROPY_SRC_INTR_ENABLE
4'b 0001, // index[ 2] ENTROPY_SRC_INTR_TEST
@@ -491,28 +551,32 @@
4'b 1111, // index[12] ENTROPY_SRC_ADAPTP_HI_THRESHOLDS
4'b 1111, // index[13] ENTROPY_SRC_ADAPTP_LO_THRESHOLDS
4'b 1111, // index[14] ENTROPY_SRC_BUCKET_THRESHOLDS
- 4'b 1111, // index[15] ENTROPY_SRC_MARKOV_THRESHOLDS
- 4'b 1111, // index[16] ENTROPY_SRC_EXTHT_HI_THRESHOLDS
- 4'b 1111, // index[17] ENTROPY_SRC_EXTHT_LO_THRESHOLDS
- 4'b 1111, // index[18] ENTROPY_SRC_REPCNT_HI_WATERMARKS
- 4'b 1111, // index[19] ENTROPY_SRC_ADAPTP_HI_WATERMARKS
- 4'b 1111, // index[20] ENTROPY_SRC_ADAPTP_LO_WATERMARKS
- 4'b 1111, // index[21] ENTROPY_SRC_EXTHT_HI_WATERMARKS
- 4'b 1111, // index[22] ENTROPY_SRC_EXTHT_LO_WATERMARKS
- 4'b 1111, // index[23] ENTROPY_SRC_BUCKET_HI_WATERMARKS
- 4'b 1111, // index[24] ENTROPY_SRC_MARKOV_HI_WATERMARKS
- 4'b 1111, // index[25] ENTROPY_SRC_REPCNT_TOTAL_FAILS
- 4'b 1111, // index[26] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS
- 4'b 1111, // index[27] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS
- 4'b 1111, // index[28] ENTROPY_SRC_BUCKET_TOTAL_FAILS
- 4'b 1111, // index[29] ENTROPY_SRC_MARKOV_TOTAL_FAILS
- 4'b 1111, // index[30] ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS
- 4'b 1111, // index[31] ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS
- 4'b 0001, // index[32] ENTROPY_SRC_ALERT_THRESHOLD
- 4'b 0111, // index[33] ENTROPY_SRC_ALERT_FAIL_COUNTS
- 4'b 0001, // index[34] ENTROPY_SRC_EXTHT_FAIL_COUNTS
- 4'b 1111, // index[35] ENTROPY_SRC_DEBUG_STATUS
- 4'b 0001 // index[36] ENTROPY_SRC_SEED
+ 4'b 1111, // index[15] ENTROPY_SRC_MARKOV_HI_THRESHOLDS
+ 4'b 1111, // index[16] ENTROPY_SRC_MARKOV_LO_THRESHOLDS
+ 4'b 1111, // index[17] ENTROPY_SRC_EXTHT_HI_THRESHOLDS
+ 4'b 1111, // index[18] ENTROPY_SRC_EXTHT_LO_THRESHOLDS
+ 4'b 1111, // index[19] ENTROPY_SRC_REPCNT_HI_WATERMARKS
+ 4'b 1111, // index[20] ENTROPY_SRC_ADAPTP_HI_WATERMARKS
+ 4'b 1111, // index[21] ENTROPY_SRC_ADAPTP_LO_WATERMARKS
+ 4'b 1111, // index[22] ENTROPY_SRC_EXTHT_HI_WATERMARKS
+ 4'b 1111, // index[23] ENTROPY_SRC_EXTHT_LO_WATERMARKS
+ 4'b 1111, // index[24] ENTROPY_SRC_BUCKET_HI_WATERMARKS
+ 4'b 1111, // index[25] ENTROPY_SRC_MARKOV_HI_WATERMARKS
+ 4'b 1111, // index[26] ENTROPY_SRC_MARKOV_LO_WATERMARKS
+ 4'b 1111, // index[27] ENTROPY_SRC_REPCNT_TOTAL_FAILS
+ 4'b 1111, // index[28] ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS
+ 4'b 1111, // index[29] ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS
+ 4'b 1111, // index[30] ENTROPY_SRC_BUCKET_TOTAL_FAILS
+ 4'b 1111, // index[31] ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS
+ 4'b 1111, // index[32] ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS
+ 4'b 1111, // index[33] ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS
+ 4'b 1111, // index[34] ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS
+ 4'b 0001, // index[35] ENTROPY_SRC_ALERT_THRESHOLD
+ 4'b 1111, // index[36] ENTROPY_SRC_ALERT_FAIL_COUNTS
+ 4'b 0001, // index[37] ENTROPY_SRC_EXTHT_FAIL_COUNTS
+ 4'b 1111, // index[38] ENTROPY_SRC_DEBUG_STATUS
+ 4'b 0001, // index[39] ENTROPY_SRC_SEED
+ 4'b 1111 // index[40] ENTROPY_SRC_ERR_CODE
};
endpackage
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
index a53144e..48ccbbd 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
@@ -174,12 +174,18 @@
logic [15:0] bucket_thresholds_bypass_bucket_thresh_qs;
logic [15:0] bucket_thresholds_bypass_bucket_thresh_wd;
logic bucket_thresholds_bypass_bucket_thresh_we;
- logic [15:0] markov_thresholds_fips_markov_thresh_qs;
- logic [15:0] markov_thresholds_fips_markov_thresh_wd;
- logic markov_thresholds_fips_markov_thresh_we;
- logic [15:0] markov_thresholds_bypass_markov_thresh_qs;
- logic [15:0] markov_thresholds_bypass_markov_thresh_wd;
- logic markov_thresholds_bypass_markov_thresh_we;
+ logic [15:0] markov_hi_thresholds_fips_markov_hi_thresh_qs;
+ logic [15:0] markov_hi_thresholds_fips_markov_hi_thresh_wd;
+ logic markov_hi_thresholds_fips_markov_hi_thresh_we;
+ logic [15:0] markov_hi_thresholds_bypass_markov_hi_thresh_qs;
+ logic [15:0] markov_hi_thresholds_bypass_markov_hi_thresh_wd;
+ logic markov_hi_thresholds_bypass_markov_hi_thresh_we;
+ logic [15:0] markov_lo_thresholds_fips_markov_lo_thresh_qs;
+ logic [15:0] markov_lo_thresholds_fips_markov_lo_thresh_wd;
+ logic markov_lo_thresholds_fips_markov_lo_thresh_we;
+ logic [15:0] markov_lo_thresholds_bypass_markov_lo_thresh_qs;
+ logic [15:0] markov_lo_thresholds_bypass_markov_lo_thresh_wd;
+ logic markov_lo_thresholds_bypass_markov_lo_thresh_we;
logic [15:0] extht_hi_thresholds_fips_extht_hi_thresh_qs;
logic [15:0] extht_hi_thresholds_fips_extht_hi_thresh_wd;
logic extht_hi_thresholds_fips_extht_hi_thresh_we;
@@ -220,6 +226,10 @@
logic markov_hi_watermarks_fips_markov_hi_watermark_re;
logic [15:0] markov_hi_watermarks_bypass_markov_hi_watermark_qs;
logic markov_hi_watermarks_bypass_markov_hi_watermark_re;
+ logic [15:0] markov_lo_watermarks_fips_markov_lo_watermark_qs;
+ logic markov_lo_watermarks_fips_markov_lo_watermark_re;
+ logic [15:0] markov_lo_watermarks_bypass_markov_lo_watermark_qs;
+ logic markov_lo_watermarks_bypass_markov_lo_watermark_re;
logic [31:0] repcnt_total_fails_qs;
logic repcnt_total_fails_re;
logic [31:0] adaptp_hi_total_fails_qs;
@@ -228,8 +238,10 @@
logic adaptp_lo_total_fails_re;
logic [31:0] bucket_total_fails_qs;
logic bucket_total_fails_re;
- logic [31:0] markov_total_fails_qs;
- logic markov_total_fails_re;
+ logic [31:0] markov_hi_total_fails_qs;
+ logic markov_hi_total_fails_re;
+ logic [31:0] markov_lo_total_fails_qs;
+ logic markov_lo_total_fails_re;
logic [31:0] extht_hi_total_fails_qs;
logic extht_hi_total_fails_re;
logic [31:0] extht_lo_total_fails_qs;
@@ -247,8 +259,10 @@
logic alert_fail_counts_adaptp_lo_fail_count_re;
logic [3:0] alert_fail_counts_bucket_fail_count_qs;
logic alert_fail_counts_bucket_fail_count_re;
- logic [3:0] alert_fail_counts_markov_fail_count_qs;
- logic alert_fail_counts_markov_fail_count_re;
+ logic [3:0] alert_fail_counts_markov_hi_fail_count_qs;
+ logic alert_fail_counts_markov_hi_fail_count_re;
+ logic [3:0] alert_fail_counts_markov_lo_fail_count_qs;
+ logic alert_fail_counts_markov_lo_fail_count_re;
logic [3:0] extht_fail_counts_extht_hi_fail_count_qs;
logic extht_fail_counts_extht_hi_fail_count_re;
logic [3:0] extht_fail_counts_extht_lo_fail_count_qs;
@@ -260,6 +274,21 @@
logic [3:0] seed_qs;
logic [3:0] seed_wd;
logic seed_we;
+ logic err_code_sfifo_esrng_err_qs;
+ logic err_code_sfifo_esrng_err_wd;
+ logic err_code_sfifo_esrng_err_we;
+ logic err_code_sfifo_esfinal_err_qs;
+ logic err_code_sfifo_esfinal_err_wd;
+ logic err_code_sfifo_esfinal_err_we;
+ logic err_code_fifo_write_err_qs;
+ logic err_code_fifo_write_err_wd;
+ logic err_code_fifo_write_err_we;
+ logic err_code_fifo_read_err_qs;
+ logic err_code_fifo_read_err_wd;
+ logic err_code_fifo_read_err_we;
+ logic err_code_fifo_state_err_qs;
+ logic err_code_fifo_state_err_wd;
+ logic err_code_fifo_state_err_we;
// Register instances
// R[intr_state]: V(False)
@@ -1158,20 +1187,20 @@
);
- // R[markov_thresholds]: V(False)
+ // R[markov_hi_thresholds]: V(False)
- // F[fips_markov_thresh]: 15:0
+ // F[fips_markov_hi_thresh]: 15:0
prim_subreg #(
.DW (16),
.SWACCESS("RW"),
.RESVAL (16'h100)
- ) u_markov_thresholds_fips_markov_thresh (
+ ) u_markov_hi_thresholds_fips_markov_hi_thresh (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (markov_thresholds_fips_markov_thresh_we & regen_qs),
- .wd (markov_thresholds_fips_markov_thresh_wd),
+ .we (markov_hi_thresholds_fips_markov_hi_thresh_we & regen_qs),
+ .wd (markov_hi_thresholds_fips_markov_hi_thresh_wd),
// from internal hardware
.de (1'b0),
@@ -1179,25 +1208,25 @@
// to internal hardware
.qe (),
- .q (reg2hw.markov_thresholds.fips_markov_thresh.q ),
+ .q (reg2hw.markov_hi_thresholds.fips_markov_hi_thresh.q ),
// to register interface (read)
- .qs (markov_thresholds_fips_markov_thresh_qs)
+ .qs (markov_hi_thresholds_fips_markov_hi_thresh_qs)
);
- // F[bypass_markov_thresh]: 31:16
+ // F[bypass_markov_hi_thresh]: 31:16
prim_subreg #(
.DW (16),
.SWACCESS("RW"),
.RESVAL (16'h60)
- ) u_markov_thresholds_bypass_markov_thresh (
+ ) u_markov_hi_thresholds_bypass_markov_hi_thresh (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (markov_thresholds_bypass_markov_thresh_we & regen_qs),
- .wd (markov_thresholds_bypass_markov_thresh_wd),
+ .we (markov_hi_thresholds_bypass_markov_hi_thresh_we & regen_qs),
+ .wd (markov_hi_thresholds_bypass_markov_hi_thresh_wd),
// from internal hardware
.de (1'b0),
@@ -1205,10 +1234,64 @@
// to internal hardware
.qe (),
- .q (reg2hw.markov_thresholds.bypass_markov_thresh.q ),
+ .q (reg2hw.markov_hi_thresholds.bypass_markov_hi_thresh.q ),
// to register interface (read)
- .qs (markov_thresholds_bypass_markov_thresh_qs)
+ .qs (markov_hi_thresholds_bypass_markov_hi_thresh_qs)
+ );
+
+
+ // R[markov_lo_thresholds]: V(False)
+
+ // F[fips_markov_lo_thresh]: 15:0
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h10)
+ ) u_markov_lo_thresholds_fips_markov_lo_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (markov_lo_thresholds_fips_markov_lo_thresh_we & regen_qs),
+ .wd (markov_lo_thresholds_fips_markov_lo_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.markov_lo_thresholds.fips_markov_lo_thresh.q ),
+
+ // to register interface (read)
+ .qs (markov_lo_thresholds_fips_markov_lo_thresh_qs)
+ );
+
+
+ // F[bypass_markov_lo_thresh]: 31:16
+ prim_subreg #(
+ .DW (16),
+ .SWACCESS("RW"),
+ .RESVAL (16'h6)
+ ) u_markov_lo_thresholds_bypass_markov_lo_thresh (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (markov_lo_thresholds_bypass_markov_lo_thresh_we & regen_qs),
+ .wd (markov_lo_thresholds_bypass_markov_lo_thresh_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.markov_lo_thresholds.bypass_markov_lo_thresh.q ),
+
+ // to register interface (read)
+ .qs (markov_lo_thresholds_bypass_markov_lo_thresh_qs)
);
@@ -1544,6 +1627,38 @@
);
+ // R[markov_lo_watermarks]: V(True)
+
+ // F[fips_markov_lo_watermark]: 15:0
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_markov_lo_watermarks_fips_markov_lo_watermark (
+ .re (markov_lo_watermarks_fips_markov_lo_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.markov_lo_watermarks.fips_markov_lo_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (markov_lo_watermarks_fips_markov_lo_watermark_qs)
+ );
+
+
+ // F[bypass_markov_lo_watermark]: 31:16
+ prim_subreg_ext #(
+ .DW (16)
+ ) u_markov_lo_watermarks_bypass_markov_lo_watermark (
+ .re (markov_lo_watermarks_bypass_markov_lo_watermark_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.markov_lo_watermarks.bypass_markov_lo_watermark.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (markov_lo_watermarks_bypass_markov_lo_watermark_qs)
+ );
+
+
// R[repcnt_total_fails]: V(True)
prim_subreg_ext #(
@@ -1608,19 +1723,35 @@
);
- // R[markov_total_fails]: V(True)
+ // R[markov_hi_total_fails]: V(True)
prim_subreg_ext #(
.DW (32)
- ) u_markov_total_fails (
- .re (markov_total_fails_re),
+ ) u_markov_hi_total_fails (
+ .re (markov_hi_total_fails_re),
.we (1'b0),
.wd ('0),
- .d (hw2reg.markov_total_fails.d),
+ .d (hw2reg.markov_hi_total_fails.d),
.qre (),
.qe (),
.q (),
- .qs (markov_total_fails_qs)
+ .qs (markov_hi_total_fails_qs)
+ );
+
+
+ // R[markov_lo_total_fails]: V(True)
+
+ prim_subreg_ext #(
+ .DW (32)
+ ) u_markov_lo_total_fails (
+ .re (markov_lo_total_fails_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.markov_lo_total_fails.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (markov_lo_total_fails_qs)
);
@@ -1760,18 +1891,33 @@
);
- // F[markov_fail_count]: 23:20
+ // F[markov_hi_fail_count]: 23:20
prim_subreg_ext #(
.DW (4)
- ) u_alert_fail_counts_markov_fail_count (
- .re (alert_fail_counts_markov_fail_count_re),
+ ) u_alert_fail_counts_markov_hi_fail_count (
+ .re (alert_fail_counts_markov_hi_fail_count_re),
.we (1'b0),
.wd ('0),
- .d (hw2reg.alert_fail_counts.markov_fail_count.d),
+ .d (hw2reg.alert_fail_counts.markov_hi_fail_count.d),
.qre (),
.qe (),
.q (),
- .qs (alert_fail_counts_markov_fail_count_qs)
+ .qs (alert_fail_counts_markov_hi_fail_count_qs)
+ );
+
+
+ // F[markov_lo_fail_count]: 27:24
+ prim_subreg_ext #(
+ .DW (4)
+ ) u_alert_fail_counts_markov_lo_fail_count (
+ .re (alert_fail_counts_markov_lo_fail_count_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.alert_fail_counts.markov_lo_fail_count.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (alert_fail_counts_markov_lo_fail_count_qs)
);
@@ -1866,9 +2012,141 @@
);
+ // R[err_code]: V(False)
+
+ // F[sfifo_esrng_err]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_err_code_sfifo_esrng_err (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (err_code_sfifo_esrng_err_we),
+ .wd (err_code_sfifo_esrng_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.sfifo_esrng_err.de),
+ .d (hw2reg.err_code.sfifo_esrng_err.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (err_code_sfifo_esrng_err_qs)
+ );
- logic [36:0] addr_hit;
+ // F[sfifo_esfinal_err]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_err_code_sfifo_esfinal_err (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (err_code_sfifo_esfinal_err_we),
+ .wd (err_code_sfifo_esfinal_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.sfifo_esfinal_err.de),
+ .d (hw2reg.err_code.sfifo_esfinal_err.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (err_code_sfifo_esfinal_err_qs)
+ );
+
+
+ // F[fifo_write_err]: 28:28
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_err_code_fifo_write_err (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (err_code_fifo_write_err_we),
+ .wd (err_code_fifo_write_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.fifo_write_err.de),
+ .d (hw2reg.err_code.fifo_write_err.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (err_code_fifo_write_err_qs)
+ );
+
+
+ // F[fifo_read_err]: 29:29
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_err_code_fifo_read_err (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (err_code_fifo_read_err_we),
+ .wd (err_code_fifo_read_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.fifo_read_err.de),
+ .d (hw2reg.err_code.fifo_read_err.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (err_code_fifo_read_err_qs)
+ );
+
+
+ // F[fifo_state_err]: 30:30
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_err_code_fifo_state_err (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (err_code_fifo_state_err_we),
+ .wd (err_code_fifo_state_err_wd),
+
+ // from internal hardware
+ .de (hw2reg.err_code.fifo_state_err.de),
+ .d (hw2reg.err_code.fifo_state_err.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (err_code_fifo_state_err_qs)
+ );
+
+
+
+
+ logic [40:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == ENTROPY_SRC_INTR_STATE_OFFSET);
@@ -1886,28 +2164,32 @@
addr_hit[12] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_THRESHOLDS_OFFSET);
addr_hit[13] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_THRESHOLDS_OFFSET);
addr_hit[14] = (reg_addr == ENTROPY_SRC_BUCKET_THRESHOLDS_OFFSET);
- addr_hit[15] = (reg_addr == ENTROPY_SRC_MARKOV_THRESHOLDS_OFFSET);
- addr_hit[16] = (reg_addr == ENTROPY_SRC_EXTHT_HI_THRESHOLDS_OFFSET);
- addr_hit[17] = (reg_addr == ENTROPY_SRC_EXTHT_LO_THRESHOLDS_OFFSET);
- addr_hit[18] = (reg_addr == ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET);
- addr_hit[19] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET);
- addr_hit[20] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET);
- addr_hit[21] = (reg_addr == ENTROPY_SRC_EXTHT_HI_WATERMARKS_OFFSET);
- addr_hit[22] = (reg_addr == ENTROPY_SRC_EXTHT_LO_WATERMARKS_OFFSET);
- addr_hit[23] = (reg_addr == ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET);
- addr_hit[24] = (reg_addr == ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET);
- addr_hit[25] = (reg_addr == ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET);
- addr_hit[26] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET);
- addr_hit[27] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET);
- addr_hit[28] = (reg_addr == ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET);
- addr_hit[29] = (reg_addr == ENTROPY_SRC_MARKOV_TOTAL_FAILS_OFFSET);
- addr_hit[30] = (reg_addr == ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_OFFSET);
- addr_hit[31] = (reg_addr == ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_OFFSET);
- addr_hit[32] = (reg_addr == ENTROPY_SRC_ALERT_THRESHOLD_OFFSET);
- addr_hit[33] = (reg_addr == ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET);
- addr_hit[34] = (reg_addr == ENTROPY_SRC_EXTHT_FAIL_COUNTS_OFFSET);
- addr_hit[35] = (reg_addr == ENTROPY_SRC_DEBUG_STATUS_OFFSET);
- addr_hit[36] = (reg_addr == ENTROPY_SRC_SEED_OFFSET);
+ addr_hit[15] = (reg_addr == ENTROPY_SRC_MARKOV_HI_THRESHOLDS_OFFSET);
+ addr_hit[16] = (reg_addr == ENTROPY_SRC_MARKOV_LO_THRESHOLDS_OFFSET);
+ addr_hit[17] = (reg_addr == ENTROPY_SRC_EXTHT_HI_THRESHOLDS_OFFSET);
+ addr_hit[18] = (reg_addr == ENTROPY_SRC_EXTHT_LO_THRESHOLDS_OFFSET);
+ addr_hit[19] = (reg_addr == ENTROPY_SRC_REPCNT_HI_WATERMARKS_OFFSET);
+ addr_hit[20] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_WATERMARKS_OFFSET);
+ addr_hit[21] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_WATERMARKS_OFFSET);
+ addr_hit[22] = (reg_addr == ENTROPY_SRC_EXTHT_HI_WATERMARKS_OFFSET);
+ addr_hit[23] = (reg_addr == ENTROPY_SRC_EXTHT_LO_WATERMARKS_OFFSET);
+ addr_hit[24] = (reg_addr == ENTROPY_SRC_BUCKET_HI_WATERMARKS_OFFSET);
+ addr_hit[25] = (reg_addr == ENTROPY_SRC_MARKOV_HI_WATERMARKS_OFFSET);
+ addr_hit[26] = (reg_addr == ENTROPY_SRC_MARKOV_LO_WATERMARKS_OFFSET);
+ addr_hit[27] = (reg_addr == ENTROPY_SRC_REPCNT_TOTAL_FAILS_OFFSET);
+ addr_hit[28] = (reg_addr == ENTROPY_SRC_ADAPTP_HI_TOTAL_FAILS_OFFSET);
+ addr_hit[29] = (reg_addr == ENTROPY_SRC_ADAPTP_LO_TOTAL_FAILS_OFFSET);
+ addr_hit[30] = (reg_addr == ENTROPY_SRC_BUCKET_TOTAL_FAILS_OFFSET);
+ addr_hit[31] = (reg_addr == ENTROPY_SRC_MARKOV_HI_TOTAL_FAILS_OFFSET);
+ addr_hit[32] = (reg_addr == ENTROPY_SRC_MARKOV_LO_TOTAL_FAILS_OFFSET);
+ addr_hit[33] = (reg_addr == ENTROPY_SRC_EXTHT_HI_TOTAL_FAILS_OFFSET);
+ addr_hit[34] = (reg_addr == ENTROPY_SRC_EXTHT_LO_TOTAL_FAILS_OFFSET);
+ addr_hit[35] = (reg_addr == ENTROPY_SRC_ALERT_THRESHOLD_OFFSET);
+ addr_hit[36] = (reg_addr == ENTROPY_SRC_ALERT_FAIL_COUNTS_OFFSET);
+ addr_hit[37] = (reg_addr == ENTROPY_SRC_EXTHT_FAIL_COUNTS_OFFSET);
+ addr_hit[38] = (reg_addr == ENTROPY_SRC_DEBUG_STATUS_OFFSET);
+ addr_hit[39] = (reg_addr == ENTROPY_SRC_SEED_OFFSET);
+ addr_hit[40] = (reg_addr == ENTROPY_SRC_ERR_CODE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -1952,6 +2234,10 @@
if (addr_hit[34] && reg_we && (ENTROPY_SRC_PERMIT[34] != (ENTROPY_SRC_PERMIT[34] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[35] && reg_we && (ENTROPY_SRC_PERMIT[35] != (ENTROPY_SRC_PERMIT[35] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[36] && reg_we && (ENTROPY_SRC_PERMIT[36] != (ENTROPY_SRC_PERMIT[36] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[37] && reg_we && (ENTROPY_SRC_PERMIT[37] != (ENTROPY_SRC_PERMIT[37] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[38] && reg_we && (ENTROPY_SRC_PERMIT[38] != (ENTROPY_SRC_PERMIT[38] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[39] && reg_we && (ENTROPY_SRC_PERMIT[39] != (ENTROPY_SRC_PERMIT[39] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[40] && reg_we && (ENTROPY_SRC_PERMIT[40] != (ENTROPY_SRC_PERMIT[40] & reg_be))) wr_err = 1'b1 ;
end
assign intr_state_es_entropy_valid_we = addr_hit[0] & reg_we & ~wr_err;
@@ -2061,92 +2347,121 @@
assign bucket_thresholds_bypass_bucket_thresh_we = addr_hit[14] & reg_we & ~wr_err;
assign bucket_thresholds_bypass_bucket_thresh_wd = reg_wdata[31:16];
- assign markov_thresholds_fips_markov_thresh_we = addr_hit[15] & reg_we & ~wr_err;
- assign markov_thresholds_fips_markov_thresh_wd = reg_wdata[15:0];
+ assign markov_hi_thresholds_fips_markov_hi_thresh_we = addr_hit[15] & reg_we & ~wr_err;
+ assign markov_hi_thresholds_fips_markov_hi_thresh_wd = reg_wdata[15:0];
- assign markov_thresholds_bypass_markov_thresh_we = addr_hit[15] & reg_we & ~wr_err;
- assign markov_thresholds_bypass_markov_thresh_wd = reg_wdata[31:16];
+ assign markov_hi_thresholds_bypass_markov_hi_thresh_we = addr_hit[15] & reg_we & ~wr_err;
+ assign markov_hi_thresholds_bypass_markov_hi_thresh_wd = reg_wdata[31:16];
- assign extht_hi_thresholds_fips_extht_hi_thresh_we = addr_hit[16] & reg_we & ~wr_err;
+ assign markov_lo_thresholds_fips_markov_lo_thresh_we = addr_hit[16] & reg_we & ~wr_err;
+ assign markov_lo_thresholds_fips_markov_lo_thresh_wd = reg_wdata[15:0];
+
+ assign markov_lo_thresholds_bypass_markov_lo_thresh_we = addr_hit[16] & reg_we & ~wr_err;
+ assign markov_lo_thresholds_bypass_markov_lo_thresh_wd = reg_wdata[31:16];
+
+ assign extht_hi_thresholds_fips_extht_hi_thresh_we = addr_hit[17] & reg_we & ~wr_err;
assign extht_hi_thresholds_fips_extht_hi_thresh_wd = reg_wdata[15:0];
- assign extht_hi_thresholds_bypass_extht_hi_thresh_we = addr_hit[16] & reg_we & ~wr_err;
+ assign extht_hi_thresholds_bypass_extht_hi_thresh_we = addr_hit[17] & reg_we & ~wr_err;
assign extht_hi_thresholds_bypass_extht_hi_thresh_wd = reg_wdata[31:16];
- assign extht_lo_thresholds_fips_extht_lo_thresh_we = addr_hit[17] & reg_we & ~wr_err;
+ assign extht_lo_thresholds_fips_extht_lo_thresh_we = addr_hit[18] & reg_we & ~wr_err;
assign extht_lo_thresholds_fips_extht_lo_thresh_wd = reg_wdata[15:0];
- assign extht_lo_thresholds_bypass_extht_lo_thresh_we = addr_hit[17] & reg_we & ~wr_err;
+ assign extht_lo_thresholds_bypass_extht_lo_thresh_we = addr_hit[18] & reg_we & ~wr_err;
assign extht_lo_thresholds_bypass_extht_lo_thresh_wd = reg_wdata[31:16];
- assign repcnt_hi_watermarks_fips_repcnt_hi_watermark_re = addr_hit[18] && reg_re;
+ assign repcnt_hi_watermarks_fips_repcnt_hi_watermark_re = addr_hit[19] && reg_re;
- assign repcnt_hi_watermarks_bypass_repcnt_hi_watermark_re = addr_hit[18] && reg_re;
+ assign repcnt_hi_watermarks_bypass_repcnt_hi_watermark_re = addr_hit[19] && reg_re;
- assign adaptp_hi_watermarks_fips_adaptp_hi_watermark_re = addr_hit[19] && reg_re;
+ assign adaptp_hi_watermarks_fips_adaptp_hi_watermark_re = addr_hit[20] && reg_re;
- assign adaptp_hi_watermarks_bypass_adaptp_hi_watermark_re = addr_hit[19] && reg_re;
+ assign adaptp_hi_watermarks_bypass_adaptp_hi_watermark_re = addr_hit[20] && reg_re;
- assign adaptp_lo_watermarks_fips_adaptp_lo_watermark_re = addr_hit[20] && reg_re;
+ assign adaptp_lo_watermarks_fips_adaptp_lo_watermark_re = addr_hit[21] && reg_re;
- assign adaptp_lo_watermarks_bypass_adaptp_lo_watermark_re = addr_hit[20] && reg_re;
+ assign adaptp_lo_watermarks_bypass_adaptp_lo_watermark_re = addr_hit[21] && reg_re;
- assign extht_hi_watermarks_fips_extht_hi_watermark_re = addr_hit[21] && reg_re;
+ assign extht_hi_watermarks_fips_extht_hi_watermark_re = addr_hit[22] && reg_re;
- assign extht_hi_watermarks_bypass_extht_hi_watermark_re = addr_hit[21] && reg_re;
+ assign extht_hi_watermarks_bypass_extht_hi_watermark_re = addr_hit[22] && reg_re;
- assign extht_lo_watermarks_fips_extht_lo_watermark_re = addr_hit[22] && reg_re;
+ assign extht_lo_watermarks_fips_extht_lo_watermark_re = addr_hit[23] && reg_re;
- assign extht_lo_watermarks_bypass_extht_lo_watermark_re = addr_hit[22] && reg_re;
+ assign extht_lo_watermarks_bypass_extht_lo_watermark_re = addr_hit[23] && reg_re;
- assign bucket_hi_watermarks_fips_bucket_hi_watermark_re = addr_hit[23] && reg_re;
+ assign bucket_hi_watermarks_fips_bucket_hi_watermark_re = addr_hit[24] && reg_re;
- assign bucket_hi_watermarks_bypass_bucket_hi_watermark_re = addr_hit[23] && reg_re;
+ assign bucket_hi_watermarks_bypass_bucket_hi_watermark_re = addr_hit[24] && reg_re;
- assign markov_hi_watermarks_fips_markov_hi_watermark_re = addr_hit[24] && reg_re;
+ assign markov_hi_watermarks_fips_markov_hi_watermark_re = addr_hit[25] && reg_re;
- assign markov_hi_watermarks_bypass_markov_hi_watermark_re = addr_hit[24] && reg_re;
+ assign markov_hi_watermarks_bypass_markov_hi_watermark_re = addr_hit[25] && reg_re;
- assign repcnt_total_fails_re = addr_hit[25] && reg_re;
+ assign markov_lo_watermarks_fips_markov_lo_watermark_re = addr_hit[26] && reg_re;
- assign adaptp_hi_total_fails_re = addr_hit[26] && reg_re;
+ assign markov_lo_watermarks_bypass_markov_lo_watermark_re = addr_hit[26] && reg_re;
- assign adaptp_lo_total_fails_re = addr_hit[27] && reg_re;
+ assign repcnt_total_fails_re = addr_hit[27] && reg_re;
- assign bucket_total_fails_re = addr_hit[28] && reg_re;
+ assign adaptp_hi_total_fails_re = addr_hit[28] && reg_re;
- assign markov_total_fails_re = addr_hit[29] && reg_re;
+ assign adaptp_lo_total_fails_re = addr_hit[29] && reg_re;
- assign extht_hi_total_fails_re = addr_hit[30] && reg_re;
+ assign bucket_total_fails_re = addr_hit[30] && reg_re;
- assign extht_lo_total_fails_re = addr_hit[31] && reg_re;
+ assign markov_hi_total_fails_re = addr_hit[31] && reg_re;
- assign alert_threshold_we = addr_hit[32] & reg_we & ~wr_err;
+ assign markov_lo_total_fails_re = addr_hit[32] && reg_re;
+
+ assign extht_hi_total_fails_re = addr_hit[33] && reg_re;
+
+ assign extht_lo_total_fails_re = addr_hit[34] && reg_re;
+
+ assign alert_threshold_we = addr_hit[35] & reg_we & ~wr_err;
assign alert_threshold_wd = reg_wdata[3:0];
- assign alert_fail_counts_any_fail_count_re = addr_hit[33] && reg_re;
+ assign alert_fail_counts_any_fail_count_re = addr_hit[36] && reg_re;
- assign alert_fail_counts_repcnt_fail_count_re = addr_hit[33] && reg_re;
+ assign alert_fail_counts_repcnt_fail_count_re = addr_hit[36] && reg_re;
- assign alert_fail_counts_adaptp_hi_fail_count_re = addr_hit[33] && reg_re;
+ assign alert_fail_counts_adaptp_hi_fail_count_re = addr_hit[36] && reg_re;
- assign alert_fail_counts_adaptp_lo_fail_count_re = addr_hit[33] && reg_re;
+ assign alert_fail_counts_adaptp_lo_fail_count_re = addr_hit[36] && reg_re;
- assign alert_fail_counts_bucket_fail_count_re = addr_hit[33] && reg_re;
+ assign alert_fail_counts_bucket_fail_count_re = addr_hit[36] && reg_re;
- assign alert_fail_counts_markov_fail_count_re = addr_hit[33] && reg_re;
+ assign alert_fail_counts_markov_hi_fail_count_re = addr_hit[36] && reg_re;
- assign extht_fail_counts_extht_hi_fail_count_re = addr_hit[34] && reg_re;
+ assign alert_fail_counts_markov_lo_fail_count_re = addr_hit[36] && reg_re;
- assign extht_fail_counts_extht_lo_fail_count_re = addr_hit[34] && reg_re;
+ assign extht_fail_counts_extht_hi_fail_count_re = addr_hit[37] && reg_re;
- assign debug_status_entropy_fifo_depth_re = addr_hit[35] && reg_re;
+ assign extht_fail_counts_extht_lo_fail_count_re = addr_hit[37] && reg_re;
- assign debug_status_diag_re = addr_hit[35] && reg_re;
+ assign debug_status_entropy_fifo_depth_re = addr_hit[38] && reg_re;
- assign seed_we = addr_hit[36] & reg_we & ~wr_err;
+ assign debug_status_diag_re = addr_hit[38] && reg_re;
+
+ assign seed_we = addr_hit[39] & reg_we & ~wr_err;
assign seed_wd = reg_wdata[3:0];
+ assign err_code_sfifo_esrng_err_we = addr_hit[40] & reg_we & ~wr_err;
+ assign err_code_sfifo_esrng_err_wd = reg_wdata[0];
+
+ assign err_code_sfifo_esfinal_err_we = addr_hit[40] & reg_we & ~wr_err;
+ assign err_code_sfifo_esfinal_err_wd = reg_wdata[1];
+
+ assign err_code_fifo_write_err_we = addr_hit[40] & reg_we & ~wr_err;
+ assign err_code_fifo_write_err_wd = reg_wdata[28];
+
+ assign err_code_fifo_read_err_we = addr_hit[40] & reg_we & ~wr_err;
+ assign err_code_fifo_read_err_wd = reg_wdata[29];
+
+ assign err_code_fifo_state_err_we = addr_hit[40] & reg_we & ~wr_err;
+ assign err_code_fifo_state_err_wd = reg_wdata[30];
+
// Read data return
always_comb begin
reg_rdata_next = '0;
@@ -2235,110 +2550,133 @@
end
addr_hit[15]: begin
- reg_rdata_next[15:0] = markov_thresholds_fips_markov_thresh_qs;
- reg_rdata_next[31:16] = markov_thresholds_bypass_markov_thresh_qs;
+ reg_rdata_next[15:0] = markov_hi_thresholds_fips_markov_hi_thresh_qs;
+ reg_rdata_next[31:16] = markov_hi_thresholds_bypass_markov_hi_thresh_qs;
end
addr_hit[16]: begin
+ reg_rdata_next[15:0] = markov_lo_thresholds_fips_markov_lo_thresh_qs;
+ reg_rdata_next[31:16] = markov_lo_thresholds_bypass_markov_lo_thresh_qs;
+ end
+
+ addr_hit[17]: begin
reg_rdata_next[15:0] = extht_hi_thresholds_fips_extht_hi_thresh_qs;
reg_rdata_next[31:16] = extht_hi_thresholds_bypass_extht_hi_thresh_qs;
end
- addr_hit[17]: begin
+ addr_hit[18]: begin
reg_rdata_next[15:0] = extht_lo_thresholds_fips_extht_lo_thresh_qs;
reg_rdata_next[31:16] = extht_lo_thresholds_bypass_extht_lo_thresh_qs;
end
- addr_hit[18]: begin
+ addr_hit[19]: begin
reg_rdata_next[15:0] = repcnt_hi_watermarks_fips_repcnt_hi_watermark_qs;
reg_rdata_next[31:16] = repcnt_hi_watermarks_bypass_repcnt_hi_watermark_qs;
end
- addr_hit[19]: begin
+ addr_hit[20]: begin
reg_rdata_next[15:0] = adaptp_hi_watermarks_fips_adaptp_hi_watermark_qs;
reg_rdata_next[31:16] = adaptp_hi_watermarks_bypass_adaptp_hi_watermark_qs;
end
- addr_hit[20]: begin
+ addr_hit[21]: begin
reg_rdata_next[15:0] = adaptp_lo_watermarks_fips_adaptp_lo_watermark_qs;
reg_rdata_next[31:16] = adaptp_lo_watermarks_bypass_adaptp_lo_watermark_qs;
end
- addr_hit[21]: begin
+ addr_hit[22]: begin
reg_rdata_next[15:0] = extht_hi_watermarks_fips_extht_hi_watermark_qs;
reg_rdata_next[31:16] = extht_hi_watermarks_bypass_extht_hi_watermark_qs;
end
- addr_hit[22]: begin
+ addr_hit[23]: begin
reg_rdata_next[15:0] = extht_lo_watermarks_fips_extht_lo_watermark_qs;
reg_rdata_next[31:16] = extht_lo_watermarks_bypass_extht_lo_watermark_qs;
end
- addr_hit[23]: begin
+ addr_hit[24]: begin
reg_rdata_next[15:0] = bucket_hi_watermarks_fips_bucket_hi_watermark_qs;
reg_rdata_next[31:16] = bucket_hi_watermarks_bypass_bucket_hi_watermark_qs;
end
- addr_hit[24]: begin
+ addr_hit[25]: begin
reg_rdata_next[15:0] = markov_hi_watermarks_fips_markov_hi_watermark_qs;
reg_rdata_next[31:16] = markov_hi_watermarks_bypass_markov_hi_watermark_qs;
end
- addr_hit[25]: begin
- reg_rdata_next[31:0] = repcnt_total_fails_qs;
- end
-
addr_hit[26]: begin
- reg_rdata_next[31:0] = adaptp_hi_total_fails_qs;
+ reg_rdata_next[15:0] = markov_lo_watermarks_fips_markov_lo_watermark_qs;
+ reg_rdata_next[31:16] = markov_lo_watermarks_bypass_markov_lo_watermark_qs;
end
addr_hit[27]: begin
- reg_rdata_next[31:0] = adaptp_lo_total_fails_qs;
+ reg_rdata_next[31:0] = repcnt_total_fails_qs;
end
addr_hit[28]: begin
- reg_rdata_next[31:0] = bucket_total_fails_qs;
+ reg_rdata_next[31:0] = adaptp_hi_total_fails_qs;
end
addr_hit[29]: begin
- reg_rdata_next[31:0] = markov_total_fails_qs;
+ reg_rdata_next[31:0] = adaptp_lo_total_fails_qs;
end
addr_hit[30]: begin
- reg_rdata_next[31:0] = extht_hi_total_fails_qs;
+ reg_rdata_next[31:0] = bucket_total_fails_qs;
end
addr_hit[31]: begin
- reg_rdata_next[31:0] = extht_lo_total_fails_qs;
+ reg_rdata_next[31:0] = markov_hi_total_fails_qs;
end
addr_hit[32]: begin
- reg_rdata_next[3:0] = alert_threshold_qs;
+ reg_rdata_next[31:0] = markov_lo_total_fails_qs;
end
addr_hit[33]: begin
+ reg_rdata_next[31:0] = extht_hi_total_fails_qs;
+ end
+
+ addr_hit[34]: begin
+ reg_rdata_next[31:0] = extht_lo_total_fails_qs;
+ end
+
+ addr_hit[35]: begin
+ reg_rdata_next[3:0] = alert_threshold_qs;
+ end
+
+ addr_hit[36]: begin
reg_rdata_next[3:0] = alert_fail_counts_any_fail_count_qs;
reg_rdata_next[7:4] = alert_fail_counts_repcnt_fail_count_qs;
reg_rdata_next[11:8] = alert_fail_counts_adaptp_hi_fail_count_qs;
reg_rdata_next[15:12] = alert_fail_counts_adaptp_lo_fail_count_qs;
reg_rdata_next[19:16] = alert_fail_counts_bucket_fail_count_qs;
- reg_rdata_next[23:20] = alert_fail_counts_markov_fail_count_qs;
+ reg_rdata_next[23:20] = alert_fail_counts_markov_hi_fail_count_qs;
+ reg_rdata_next[27:24] = alert_fail_counts_markov_lo_fail_count_qs;
end
- addr_hit[34]: begin
+ addr_hit[37]: begin
reg_rdata_next[3:0] = extht_fail_counts_extht_hi_fail_count_qs;
reg_rdata_next[7:4] = extht_fail_counts_extht_lo_fail_count_qs;
end
- addr_hit[35]: begin
+ addr_hit[38]: begin
reg_rdata_next[1:0] = debug_status_entropy_fifo_depth_qs;
reg_rdata_next[31] = debug_status_diag_qs;
end
- addr_hit[36]: begin
+ addr_hit[39]: begin
reg_rdata_next[3:0] = seed_qs;
end
+ addr_hit[40]: begin
+ reg_rdata_next[0] = err_code_sfifo_esrng_err_qs;
+ reg_rdata_next[1] = err_code_sfifo_esfinal_err_qs;
+ reg_rdata_next[28] = err_code_fifo_write_err_qs;
+ reg_rdata_next[29] = err_code_fifo_read_err_qs;
+ reg_rdata_next[30] = err_code_fifo_state_err_qs;
+ end
+
default: begin
reg_rdata_next = '1;
end
diff --git a/hw/ip/entropy_src/rtl/entropy_src_repcnt_ht.sv b/hw/ip/entropy_src/rtl/entropy_src_repcnt_ht.sv
index dc6cf66..40763a6 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_repcnt_ht.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_repcnt_ht.sv
@@ -6,11 +6,11 @@
//
module entropy_src_repcnt_ht #(
- parameter int unsigned RegWidth = 16,
- parameter int unsigned RngBusWidth = 4
+ parameter int RegWidth = 16,
+ parameter int RngBusWidth = 4
) (
- input clk_i,
- input rst_ni,
+ input logic clk_i,
+ input logic rst_ni,
// ins req interface
input logic [RngBusWidth-1:0] entropy_bit_i,
@@ -18,14 +18,11 @@
input logic clear_i,
input logic active_i,
input logic [RegWidth-1:0] thresh_i,
- input logic [RegWidth-1:0] window_i,
output logic [RegWidth-1:0] test_cnt_o,
- output logic test_done_pulse_o,
output logic test_fail_pulse_o
);
// signals
- logic window_cntr_wrap;
logic [RngBusWidth-1:0] samples_match_pulse;
logic [RngBusWidth-1:0] samples_no_match_pulse;
logic [RngBusWidth-1:0] rep_cnt_fail;
@@ -33,19 +30,16 @@
// flops
logic [RngBusWidth-1:0] prev_sample_q, prev_sample_d;
logic [RegWidth-1:0] rep_cntr_q[RngBusWidth], rep_cntr_d[RngBusWidth];
- logic [RegWidth-1:0] window_cntr_q, window_cntr_d;
logic [RegWidth-1:0] test_cnt_q, test_cnt_d;
always_ff @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
prev_sample_q <= '0;
rep_cntr_q <= '{default:0};
- window_cntr_q <= '0;
test_cnt_q <= '0;
end else begin
prev_sample_q <= prev_sample_d;
rep_cntr_q <= rep_cntr_d;
- window_cntr_q <= window_cntr_d;
test_cnt_q <= test_cnt_d;
end
@@ -61,7 +55,6 @@
// NIST A sample
assign prev_sample_d[sh] = (!active_i || clear_i) ? '0 :
- window_cntr_wrap ? '0 :
entropy_bit_vld_i ? entropy_bit_i[sh] :
prev_sample_q[sh];
@@ -73,7 +66,6 @@
// NIST B counter
assign rep_cntr_d[sh] =
(!active_i || clear_i) ? '0 :
- window_cntr_wrap ? '0 :
samples_match_pulse[sh] ? (rep_cntr_q[sh]+1) :
samples_no_match_pulse[sh] ? '0 :
rep_cntr_q[sh];
@@ -83,26 +75,14 @@
end : gen_cntrs
- // Window wrap condition
- assign window_cntr_wrap = (window_cntr_q == window_i);
-
- // Window counter
- assign window_cntr_d =
- clear_i ? '0 :
- window_cntr_wrap ? '0 :
- entropy_bit_vld_i ? (window_cntr_q+1) :
- window_cntr_q;
-
// Test event counter
assign test_cnt_d =
(!active_i || clear_i) ? '0 :
- window_cntr_wrap ? '0 :
entropy_bit_vld_i && (|rep_cnt_fail) ? (test_cnt_q+1) :
test_cnt_q;
// the pulses will be only one clock in length
- assign test_fail_pulse_o = active_i && window_cntr_wrap && (test_cnt_q > '0);
- assign test_done_pulse_o = window_cntr_wrap;
+ assign test_fail_pulse_o = active_i && (test_cnt_q > '0);
assign test_cnt_o = test_cnt_q;
diff --git a/hw/ip/entropy_src/rtl/entropy_src_watermark_reg.sv b/hw/ip/entropy_src/rtl/entropy_src_watermark_reg.sv
index aa8a12e..1de4934 100755
--- a/hw/ip/entropy_src/rtl/entropy_src_watermark_reg.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_watermark_reg.sv
@@ -6,7 +6,7 @@
//
module entropy_src_watermark_reg #(
- parameter int unsigned RegWidth = 16,
+ parameter int RegWidth = 16,
parameter bit HighWatermark = 1
) (
input logic clk_i,
