| commit | 4f0c07881432bcb87226e7b6c117fbcabaa8abb2 | [log] [tgz] |
|---|---|---|
| author | Muqing Liu <muqing.liu@wdc.com> | Mon Jul 18 12:54:06 2022 -0700 |
| committer | weicaiyang <49293026+weicaiyang@users.noreply.github.com> | Thu Jul 21 14:51:33 2022 -0700 |
| tree | 587bebb127ab283f5a346ca025d1c2a60ca9e862 | |
| parent | fa763996ee973bf647c4a41101435cd91eca9f24 [diff] |
[csrng, dv] Fix csrng_intr_vseq bug for cs_hw_inst_exc interrupt test
- The "cmd_stage_ack_sts" was forced to a wrong value so that
the cs_hw_inst_exc bug was not caught in the block verification
Signed-off-by: Muqing Liu <muqing.liu@wdc.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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