[dv/rstmgr] Add test for sw_rst and hw reset race
Create a test that sends sw_rst and hardware resets in close temporal
proximity.
Add UNR generated exclusion file.
Exclude rstmgr_cnsty_chk from coverage since it is tested separately.
Signed-off-by: Guillermo Maturana <maturana@google.com>
diff --git a/hw/ip/rstmgr/data/rstmgr_testplan.hjson b/hw/ip/rstmgr/data/rstmgr_testplan.hjson
index 8eadece..039c974 100644
--- a/hw/ip/rstmgr/data/rstmgr_testplan.hjson
+++ b/hw/ip/rstmgr/data/rstmgr_testplan.hjson
@@ -10,6 +10,7 @@
// TODO: Top-level specific Hjson imported here. This will likely be resolved
// once we move to IPgen flow.
"hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr_sec_cm_testplan.hjson"]
+
testpoints: [
{
name: smoke
@@ -81,6 +82,24 @@
tests: ["rstmgr_sw_rst"]
}
{
+ name: sw_rst_reset_race
+ desc: '''Test sw_rst and reset close in time.
+
+ Sends sw_rst and regular resets in close temporal proximity.
+
+ **Stimulus**:
+ - Write `sw_rst_ctrl_n` CSR with random values when regwen is all 1's.
+ - Send a hardware reset.
+ - Release resets.
+
+ **Checks**:
+ - Check the `reset_info` CSR.
+ - Reset behavior is checked by SVA.
+ '''
+ milestone: V2
+ tests: ["rstmgr_sw_rst_reset_race"]
+ }
+ {
name: reset_info
desc: '''Test the reporting of reset reason.
@@ -148,7 +167,7 @@
- rstmgr_sw_rst_vseq
'''
milestone: V2
- tests: []
+ tests: ["rstmgr_stress_all"]
}
]
diff --git a/hw/ip/rstmgr/dv/cov/rstmgr_cover.cfg b/hw/ip/rstmgr/dv/cov/rstmgr_cover.cfg
new file mode 100644
index 0000000..a8fbf67
--- /dev/null
+++ b/hw/ip/rstmgr/dv/cov/rstmgr_cover.cfg
@@ -0,0 +1,6 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Remove rstmgr_cnsty_chk module tree since it is a V2S.
+-moduletree rstmgr_cnsty_chk
diff --git a/hw/ip/rstmgr/dv/cov/rstmgr_unr_excl.el b/hw/ip/rstmgr/dv/cov/rstmgr_unr_excl.el
new file mode 100644
index 0000000..f26af1b
--- /dev/null
+++ b/hw/ip/rstmgr/dv/cov/rstmgr_unr_excl.el
@@ -0,0 +1,384 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Generated UNR file from Synopsys UNR tool with D2S rstmgr_cnsty_chk module
+// excluded.
+// This needs to be reviewed with designer:
+// TODO(https://github.com/lowRISC/opentitan/issues/10694)
+//
+//==================================================
+// This file contains the Excluded objects
+// Generated By User: maturana
+// Format Version: 2
+// Date: Tue Feb 8 12:30:32 2022
+// ExclMode: default
+//==================================================
+CHECKSUM: "4136145515 674809128"
+INSTANCE: tb.dut
+ANNOTATION: "VC_COV_UNR"
+Condition 2 "856994301" "(reg_intg_err || ((|cnsty_chk_errs)) || ((|shadow_cnsty_chk_errs)) || ((|fsm_errs)) || ((|shadow_fsm_errs))) 1 -1" (2 "00001")
+ANNOTATION: "VC_COV_UNR"
+Condition 2 "856994301" "(reg_intg_err || ((|cnsty_chk_errs)) || ((|shadow_cnsty_chk_errs)) || ((|fsm_errs)) || ((|shadow_fsm_errs))) 1 -1" (3 "00010")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_daon_por
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_daon_por_io
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_daon_por_io_div2
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_daon_por_io_div4
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_daon_por_usb
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_d0_lc
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_d0_lc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_daon_lc_io_div4
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_d0_lc_io_div4
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_daon_lc_io_div4_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_d0_lc_io_div4_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_daon_lc_aon
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_d0_sys
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_d0_sys_shadowed
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_daon_sys_io_div4
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_d0_sys_io_div4
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_daon_sys_aon
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1359147661"
+INSTANCE: tb.dut.u_d0_sys_aon
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10")
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11")
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_daon_por
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_daon_por_io
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_daon_por_io_div2
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_daon_por_io_div4
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_daon_por_usb
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_daon_lc_io_div4_shadowed
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_d0_lc
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_d0_lc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_daon_lc_io_div4
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_d0_lc_io_div4
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_d0_lc_io_div4_shadowed
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_daon_lc_aon
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_d0_sys
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_d0_sys_shadowed
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_daon_sys_io_div4
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_d0_sys_io_div4
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_daon_sys_aon
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "3435455202 1666455474"
+INSTANCE: tb.dut.u_d0_sys_aon
+ANNOTATION: "VC_COV_UNR"
+Block 4 "762045522" "sw_rst_req_q <= '0;"
+CHECKSUM: "4136145515 4124731032"
+INSTANCE: tb.dut
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_i2c1_n [0] "logic resets_o.rst_i2c1_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_i2c1_n [0] "logic resets_o.rst_i2c1_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_i2c0_n [0] "logic resets_o.rst_i2c0_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_i2c0_n [0] "logic resets_o.rst_i2c0_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_usbif_n [0] "logic resets_o.rst_usbif_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_usbif_n [0] "logic resets_o.rst_usbif_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_usb_n [0] "logic resets_o.rst_usb_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_usb_n [0] "logic resets_o.rst_usb_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_spi_host1_n [0] "logic resets_o.rst_spi_host1_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_spi_host1_n [0] "logic resets_o.rst_spi_host1_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_spi_host0_n [0] "logic resets_o.rst_spi_host0_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_spi_host0_n [0] "logic resets_o.rst_spi_host0_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_spi_device_n [0] "logic resets_o.rst_spi_device_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_spi_device_n [0] "logic resets_o.rst_spi_device_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_sys_n [0] "logic resets_o.rst_sys_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_sys_n [0] "logic resets_o.rst_sys_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_sys_shadowed_n [0] "logic resets_o.rst_sys_shadowed_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_sys_shadowed_n [0] "logic resets_o.rst_sys_shadowed_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_lc_aon_n [1] "logic resets_o.rst_lc_aon_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_lc_aon_n [1] "logic resets_o.rst_lc_aon_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_lc_n [0] "logic resets_o.rst_lc_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_lc_n [0] "logic resets_o.rst_lc_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_lc_shadowed_n [0] "logic resets_o.rst_lc_shadowed_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_lc_shadowed_n [0] "logic resets_o.rst_lc_shadowed_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_por_usb_n [1] "logic resets_o.rst_por_usb_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_por_usb_n [1] "logic resets_o.rst_por_usb_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_por_io_div4_n [1] "logic resets_o.rst_por_io_div4_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_por_io_div4_n [1] "logic resets_o.rst_por_io_div4_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_por_io_div2_n [1] "logic resets_o.rst_por_io_div2_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_por_io_div2_n [1] "logic resets_o.rst_por_io_div2_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_por_io_n [1] "logic resets_o.rst_por_io_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_por_io_n [1] "logic resets_o.rst_por_io_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 resets_o.rst_por_n [1] "logic resets_o.rst_por_n[1:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 resets_o.rst_por_n [1] "logic resets_o.rst_por_n[1:0]"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_daon_por
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_daon_por_io
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_daon_por_io_div2
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_daon_por_io_div4
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_daon_por_usb
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_d0_lc
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_d0_lc_shadowed
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_daon_lc_io_div4
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_d0_lc_io_div4
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_daon_lc_io_div4_shadowed
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_d0_lc_io_div4_shadowed
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_daon_lc_aon
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_d0_sys
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_d0_sys_shadowed
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_daon_sys_io_div4
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_d0_sys_io_div4
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_daon_sys_aon
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
+CHECKSUM: "3435455202 1292564160"
+INSTANCE: tb.dut.u_d0_sys_aon
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1"
diff --git a/hw/ip/rstmgr/dv/env/rstmgr_env.core b/hw/ip/rstmgr/dv/env/rstmgr_env.core
index a8519c0..ed16f1d 100644
--- a/hw/ip/rstmgr/dv/env/rstmgr_env.core
+++ b/hw/ip/rstmgr/dv/env/rstmgr_env.core
@@ -28,6 +28,7 @@
- seq_lib/rstmgr_reset_vseq.sv: {is_include_file: true}
- seq_lib/rstmgr_smoke_vseq.sv: {is_include_file: true}
- seq_lib/rstmgr_stress_all_vseq.sv: {is_include_file: true}
+ - seq_lib/rstmgr_sw_rst_reset_race_vseq.sv: {is_include_file: true}
- seq_lib/rstmgr_sw_rst_vseq.sv: {is_include_file: true}
- rstmgr_if.sv
file_type: systemVerilogSource
diff --git a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv
index a2117ee..f69a328 100644
--- a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv
+++ b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv
@@ -81,6 +81,8 @@
endfunction
function void set_pwrmgr_rst_reqs(logic rst_lc_req, logic rst_sys_req);
+ `uvm_info(`gfn, $sformatf("Setting pwr_i lc_req=%x sys_req=%x", rst_lc_req, rst_sys_req),
+ UVM_MEDIUM)
cfg.rstmgr_vif.pwr_i.rst_lc_req = {rstmgr_pkg::PowerDomains{rst_lc_req}};
cfg.rstmgr_vif.pwr_i.rst_sys_req = {rstmgr_pkg::PowerDomains{rst_sys_req}};
endfunction
@@ -208,6 +210,13 @@
check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(0));
endtask
+ task clear_sw_rst_ctrl_n();
+ const sw_rst_t sw_rst_all_ones = '1;
+ csr_wr(.ptr(ral.sw_rst_ctrl_n[0]), .value(sw_rst_all_ones));
+ csr_rd_check(.ptr(ral.sw_rst_ctrl_n[0]), .compare_value(sw_rst_all_ones),
+ .err_msg("Expected sw_rst_ctrl_n to be set"));
+ endtask
+
// Stimulate and check sw_rst_ctrl_n with a given sw_rst_regen setting.
task check_sw_rst_ctrl_n(sw_rst_t sw_rst_ctrl_n, sw_rst_t sw_rst_regen, bit erase_ctrl_n);
sw_rst_t exp_ctrl_n;
@@ -223,12 +232,7 @@
UVM_MEDIUM)
csr_rd_check(.ptr(ral.sw_rst_ctrl_n[0]), .compare_value(exp_ctrl_n),
.err_msg("Expected enabled updates in sw_rst_ctrl_n"));
- if (erase_ctrl_n) begin
- const sw_rst_t sw_rst_all_ones = '1;
- csr_wr(.ptr(ral.sw_rst_ctrl_n[0]), .value(sw_rst_all_ones));
- csr_rd_check(.ptr(ral.sw_rst_ctrl_n[0]), .compare_value(sw_rst_all_ones),
- .err_msg("Expected sw_rst_ctrl_n to be set"));
- end
+ if (erase_ctrl_n) clear_sw_rst_ctrl_n();
endtask
// Happens with hardware resets.
@@ -245,17 +249,22 @@
set_pwrmgr_rst_reqs(.rst_lc_req('0), .rst_sys_req('0));
endtask
+ task release_reset(pwrmgr_pkg::reset_cause_e reset_cause);
+ cfg.io_div4_clk_rst_vif.wait_clks(non_ndm_reset_cycles);
+ // Cause the reset to drop.
+ `uvm_info(`gfn, $sformatf("Releasing %0s reset", reset_cause.name()), UVM_LOW)
+ set_rstreqs(0);
+ reset_done();
+ endtask
+
// Sends either a low power exit or an external hardware reset request, and drops it once it
// should have caused the hardware to handle it.
task send_reset(pwrmgr_pkg::reset_cause_e reset_cause,
- logic [pwrmgr_pkg::TotalResetWidth-1:0] rstreqs);
+ logic [pwrmgr_pkg::TotalResetWidth-1:0] rstreqs, logic clear_it = 1);
`uvm_info(`gfn, $sformatf("Sending %0s reset", reset_cause.name()), UVM_LOW)
set_rstreqs(rstreqs);
reset_start(reset_cause);
- cfg.io_div4_clk_rst_vif.wait_clks(non_ndm_reset_cycles);
- // Cause the reset to drop.
- set_rstreqs(0);
- reset_done();
+ if (clear_it) release_reset(reset_cause);
endtask
task send_scan_reset();
diff --git a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_reset_race_vseq.sv b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_reset_race_vseq.sv
new file mode 100644
index 0000000..3e3cce8
--- /dev/null
+++ b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_reset_race_vseq.sv
@@ -0,0 +1,52 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Tests the software reset functionality: using `sw_rst_regen` and `sw_rst_ctrl_n` CSRs it causes
+// resets for each of the bits randomly. It also triggers lc or sys resets to verify the reset
+// transitions that cause rising upper resets but non-rising leafs.
+//
+// Then it clears specific `sw_rst_regen` bits and attempts to cause resets to determine
+// the bits with `sw_rst_regwen` cleared cannot cause a reset.
+class rstmgr_sw_rst_reset_race_vseq extends rstmgr_base_vseq;
+ `uvm_object_utils(rstmgr_sw_rst_reset_race_vseq)
+
+ `uvm_object_new
+ rand int cycles_before_sw_rst;
+ rand int cycles_before_reset;
+ constraint cycles_racing_c {
+ cycles_before_sw_rst inside {[2 : 8]};
+ cycles_before_reset inside {[2 : 8]};
+ }
+
+ constraint rstreqs_non_zero_c {rstreqs != '0;}
+
+ task body();
+ bit [NumSwResets-1:0] exp_ctrl_n;
+ bit [NumSwResets-1:0] sw_rst_regwen = '1;
+ alert_pkg::alert_crashdump_t bogus_alert_dump = '1;
+ ibex_pkg::crash_dump_t bogus_cpu_dump = '1;
+ set_alert_and_cpu_info_for_capture(bogus_alert_dump, bogus_cpu_dump);
+
+ for (int i = 0; i < num_trans; ++i) begin
+ csr_wr(.ptr(ral.reset_info), .value('1));
+
+ `DV_CHECK_RANDOMIZE_FATAL(this)
+ fork
+ begin
+ cfg.clk_rst_vif.wait_clks(cycles_before_sw_rst);
+ check_sw_rst_ctrl_n(sw_rst_ctrl_n, sw_rst_regwen, 0);
+ end
+ begin
+ cfg.clk_rst_vif.wait_clks(cycles_before_reset);
+ send_reset(.reset_cause(pwrmgr_pkg::HwReq), .rstreqs(rstreqs), .clear_it(0));
+ end
+ join
+ cfg.clk_rst_vif.wait_clks(20);
+ release_reset(pwrmgr_pkg::HwReq);
+ clear_sw_rst_ctrl_n();
+ check_reset_info({rstreqs, 4'h0}, $sformatf(
+ "expected reset_info to match 0x%x", {rstreqs, 4'h0}));
+ end
+ endtask
+endclass
diff --git a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_vseq_list.sv b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_vseq_list.sv
index 1832d8b..c35f66b 100644
--- a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_vseq_list.sv
+++ b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_vseq_list.sv
@@ -7,5 +7,6 @@
`include "rstmgr_reset_vseq.sv"
`include "rstmgr_smoke_vseq.sv"
`include "rstmgr_stress_all_vseq.sv"
+`include "rstmgr_sw_rst_reset_race_vseq.sv"
`include "rstmgr_sw_rst_vseq.sv"
`include "rstmgr_common_vseq.sv"
diff --git a/hw/ip/rstmgr/dv/rstmgr_sim_cfg.hjson b/hw/ip/rstmgr/dv/rstmgr_sim_cfg.hjson
index fb35925..def818a 100644
--- a/hw/ip/rstmgr/dv/rstmgr_sim_cfg.hjson
+++ b/hw/ip/rstmgr/dv/rstmgr_sim_cfg.hjson
@@ -36,12 +36,19 @@
"{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"
]
+ // Specific exclusion files.
+ vcs_cov_excl_files: ["{proj_root}/hw/ip/rstmgr/dv/cov/rstmgr_unr_excl.el"]
+
// Overrides
overrides: [
{
name: design_level
value: "top"
}
+ {
+ name: default_vcs_cov_cfg_file
+ value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/dv/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/ip/rstmgr/dv/cov/rstmgr_cover.cfg"
+ }
]
// Add additional tops for simulation.
@@ -69,6 +76,10 @@
uvm_test_seq: rstmgr_reset_vseq
}
{
+ name: rstmgr_sw_rst_reset_race
+ uvm_test_seq: rstmgr_sw_rst_reset_race_vseq
+ }
+ {
name: rstmgr_sw_rst
uvm_test_seq: rstmgr_sw_rst_vseq
}
diff --git a/hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv b/hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv
index 251f117..b3f091c 100644
--- a/hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv
+++ b/hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv
@@ -102,6 +102,7 @@
logic scan_reset_n;
always_comb scan_reset_n = !scanmode || scan_rst_ni;
+ // In scanmode only scan_rst_ni controls reset, so por_n_i is ignored.
logic aon_por_n_i;
always_comb aon_por_n_i = por_n_i[rstmgr_pkg::DomainAonSel] && !scanmode;
