[dv, uart_agent] Delay TX by 1ps
At the chip level, UART IOs are muxed with other IOs.
If multiple interfaces are connected to the same chip
IOs, with muxes selects selecting the function, the
IO may undergo 0->1->0 transition in the same timestep.
Since UART is an asynchronous protocol, the monitor
ends up picking up the glitch value erroneously as the
start of a new transaction. To prevent this, we delay
the incoming uart_tx by 1ps, which functionally has no
impact.
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/dv/sv/uart_agent/uart_if.sv b/hw/dv/sv/uart_agent/uart_if.sv
index 77d6b60..d15dad5 100644
--- a/hw/dv/sv/uart_agent/uart_if.sv
+++ b/hw/dv/sv/uart_agent/uart_if.sv
@@ -13,8 +13,13 @@
bit uart_rx_clk = 1'b1;
int uart_rx_clk_pulses = 0;
+ // UART TX from the DUT when signaled over muxed IOs can experience glitches in the same
+ // time-step (a simulation artifact). Delaying by 1ps eliminates them.
+ wire uart_tx_int;
+ assign #1ps uart_tx_int = uart_tx;
+
clocking mon_tx_cb @(negedge uart_tx_clk);
- input #10ns uart_tx;
+ input #10ns uart_tx_int;
endclocking
modport mon_tx_mp(clocking mon_tx_cb);
diff --git a/hw/dv/sv/uart_agent/uart_monitor.sv b/hw/dv/sv/uart_agent/uart_monitor.sv
index aa659d7..8eb4a40 100644
--- a/hw/dv/sv/uart_agent/uart_monitor.sv
+++ b/hw/dv/sv/uart_agent/uart_monitor.sv
@@ -47,19 +47,19 @@
item = uart_item::type_id::create("item");
// get the start bit
@(cfg.vif.mon_tx_mp.mon_tx_cb);
- `uvm_info(`gfn, $sformatf("tx start bit %0b", cfg.vif.uart_tx), UVM_DEBUG)
- item.start_bit = cfg.vif.uart_tx;
+ `uvm_info(`gfn, $sformatf("tx start bit %0b", cfg.vif.uart_tx_int), UVM_HIGH)
+ item.start_bit = cfg.vif.uart_tx_int;
// get the data bits
for (int i = 0; i < 8; i++) begin
@(cfg.vif.mon_tx_mp.mon_tx_cb);
- `uvm_info(`gfn, $sformatf("tx data bit[%0d] %0b", i, cfg.vif.uart_tx), UVM_DEBUG)
- item.data[i] = cfg.vif.uart_tx;
+ `uvm_info(`gfn, $sformatf("tx data bit[%0d] %0b", i, cfg.vif.uart_tx_int), UVM_DEBUG)
+ item.data[i] = cfg.vif.uart_tx_int;
end
// get the parity bit
if (cfg.vif.uart_tx_clk_pulses > 2) begin
@(cfg.vif.mon_tx_mp.mon_tx_cb);
- `uvm_info(`gfn, $sformatf("tx parity bit %0b", cfg.vif.uart_tx), UVM_DEBUG)
- item.parity = cfg.vif.uart_tx;
+ `uvm_info(`gfn, $sformatf("tx parity bit %0b", cfg.vif.uart_tx_int), UVM_DEBUG)
+ item.parity = cfg.vif.uart_tx_int;
if (cfg.en_tx_checks && item.parity != `GET_PARITY(item.data, cfg.odd_parity)) begin
`uvm_error(`gfn, "Parity failed")
end
@@ -68,10 +68,10 @@
// get the stop bit
@(cfg.vif.mon_tx_mp.mon_tx_cb);
- `uvm_info(`gfn, $sformatf("tx stop bit %0b", cfg.vif.uart_tx), UVM_DEBUG)
- item.stop_bit = cfg.vif.uart_tx;
+ `uvm_info(`gfn, $sformatf("tx stop bit %0b", cfg.vif.uart_tx_int), UVM_DEBUG)
+ item.stop_bit = cfg.vif.uart_tx_int;
// check stop bit
- if (cfg.en_tx_checks && cfg.vif.uart_tx !== 1'b1) begin
+ if (cfg.en_tx_checks && cfg.vif.uart_tx_int !== 1'b1) begin
`uvm_error(`gfn, "No stop bit when expected!")
end
`uvm_info(`gfn, $sformatf("collected uart tx txn:\n%0s", item.sprint()), UVM_HIGH)
@@ -82,7 +82,7 @@
if (cfg.en_cov) cov.uart_cg.sample(UartTx, item);
end else begin
- @(cfg.vif.uart_tx);
+ @(cfg.vif.uart_tx_int);
end
end
endtask
@@ -149,7 +149,7 @@
cfg.vif.uart_tx_clk = ~cfg.vif.uart_tx_clk;
cfg.vif.uart_tx_clk_pulses--;
end else begin
- @(cfg.vif.uart_tx, cfg.vif.uart_tx_clk_pulses);
+ @(cfg.vif.uart_tx_int, cfg.vif.uart_tx_clk_pulses);
end
end
endtask
@@ -178,7 +178,7 @@
#(cfg.vif.uart_clk_period_ns * (50 - cfg.get_max_drift_cycle_pct()) / 100);
`DV_SPINWAIT_EXIT(
begin
- @(cfg.vif.uart_tx);
+ @(cfg.vif.uart_tx_int);
`uvm_error(`gfn, $sformatf(
"Expect uart_tx stable from %0d to %0d of the period, but it's changed",
50 - cfg.get_max_drift_cycle_pct(), 50 + cfg.get_max_drift_cycle_pct()))
