[dv] Auto-gen byte write for RAL
Without update, we need to manually set partial write support for the
mem that supports it. If not, will see failure in tl_errors test.
Make it automatic to save time to debug this kind of issue
Signed-off-by: Weicai Yang <weicai@google.com>
diff --git a/util/reggen/data.py b/util/reggen/data.py
index b06164d..b14f15f 100644
--- a/util/reggen/data.py
+++ b/util/reggen/data.py
@@ -175,6 +175,7 @@
class Window():
def __init__(self):
self.base_addr = 0
+ self.byte_write = 0
self.limit_addr = 0
self.n_bits = 0
self.tags = []
diff --git a/util/reggen/gen_rtl.py b/util/reggen/gen_rtl.py
index 1454987..a3be839 100644
--- a/util/reggen/gen_rtl.py
+++ b/util/reggen/gen_rtl.py
@@ -114,6 +114,7 @@
win = Window()
win.name = obj["name"]
win.base_addr = obj["genoffset"]
+ win.byte_write = obj["genbyte-write"]
win.limit_addr = obj["genoffset"] + int(obj["items"]) * (width // 8)
win.dvrights = obj["swaccess"]
win.n_bits = obj["genvalidbits"]
diff --git a/util/reggen/uvm_reg.sv.tpl b/util/reggen/uvm_reg.sv.tpl
index ce5740b..9ba690c 100644
--- a/util/reggen/uvm_reg.sv.tpl
+++ b/util/reggen/uvm_reg.sv.tpl
@@ -160,6 +160,9 @@
string access = "${mem_right}",
int has_coverage = UVM_NO_COVERAGE);
super.new(name, size, n_bits, access, has_coverage);
+ % if w.byte_write:
+ set_mem_partial_write_support(1);
+ % endif
endfunction : new
endclass : ${gen_dv.mcname(block, w)}
diff --git a/util/topgen.py b/util/topgen.py
index da03d53..c7d29c9 100755
--- a/util/topgen.py
+++ b/util/topgen.py
@@ -815,6 +815,8 @@
mem.name = item["name"]
mem.base_addr = int(item["base_addr"], 0)
mem.limit_addr = int(item["base_addr"], 0) + int(item["size"], 0)
+ mem.byte_write = ('byte_write' in item and
+ item["byte_write"].lower() == "true")
if "swaccess" in item.keys():
mem.dvrights = item["swaccess"]
else:
