[top] Add gtech synthesis setup and batch configs
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/top_earlgrey/syn/post_elab_gtech.tcl b/hw/top_earlgrey/syn/post_elab_gtech.tcl
new file mode 100644
index 0000000..2ca9129
--- /dev/null
+++ b/hw/top_earlgrey/syn/post_elab_gtech.tcl
@@ -0,0 +1,11 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Post elab script, used in GTECH runs to modify the unmapped netlist before
+# writing it out.
+
+# Remove generic views of ram macros
+remove_design prim_generic_ram_1p_Width*
+remove_design prim_generic_ram_2p_Width*
+
diff --git a/hw/top_earlgrey/syn/top_earlgrey_batch_syn_cfg.hjson b/hw/top_earlgrey/syn/top_earlgrey_batch_syn_cfg.hjson
new file mode 100644
index 0000000..b8bf87a
--- /dev/null
+++ b/hw/top_earlgrey/syn/top_earlgrey_batch_syn_cfg.hjson
@@ -0,0 +1,26 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ // This is a cfg hjson group for synthesis.
+ // It includes all synthesis setups used in top_earlgrey.
+ name: top_earlgrey_batch_syn
+
+ import_cfgs: [// Project wide common cfg file
+ "{proj_root}/hw/data/common_project_cfg.hjson"]
+
+ flow: syn
+
+ // Maintain alphabetical order below.
+ use_cfgs: [// Block-level synthesis flows.
+ "{proj_root}/hw/ip/aes/syn/aes_syn_cfg.hjson",
+ "{proj_root}/hw/ip/keymgr/syn/keymgr_syn_cfg.hjson",
+ "{proj_root}/hw/ip/kmac/syn/kmac_syn_cfg.hjson",
+ "{proj_root}/hw/ip/lc_ctrl/syn/lc_ctrl_syn_cfg.hjson",
+ "{proj_root}/hw/ip/otbn/syn/otbn_syn_cfg.hjson",
+ "{proj_root}/hw/ip/otp_ctrl/syn/otp_ctrl_syn_cfg.hjson",
+ "{proj_root}/hw/ip/rv_core_ibex/syn/rv_core_ibex_syn_cfg.hjson",
+ // Top-level synthesis flows.
+ // TODO: align Verilator and ASIC versions.
+ "{proj_root}/hw/top_earlgrey/syn/chip_earlgrey_asic_syn_cfg.hjson"]
+}
diff --git a/hw/top_earlgrey/syn/top_earlgrey_gtech_batch_syn_cfg.hjson b/hw/top_earlgrey/syn/top_earlgrey_gtech_batch_syn_cfg.hjson
new file mode 100644
index 0000000..28ba65c
--- /dev/null
+++ b/hw/top_earlgrey/syn/top_earlgrey_gtech_batch_syn_cfg.hjson
@@ -0,0 +1,27 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ // This is a cfg hjson group for GTECH synthesis.
+ // It includes all GTECH synthesis setups used in top_earlgrey.
+ name: top_earlgrey_gtech_batch_syn
+
+ import_cfgs: [// Project wide common cfg file
+ "{proj_root}/hw/data/common_project_cfg.hjson"]
+
+ flow: syn
+
+ // Maintain alphabetical order below.
+ use_cfgs: [// Block-level GTECH synthesis flows.
+ "{proj_root}/hw/ip/aes/syn/aes_gtech_syn_cfg.hjson",
+ "{proj_root}/hw/ip/aes/syn/aes_wrap_gtech_syn_cfg.hjson",
+ "{proj_root}/hw/ip/keymgr/syn/keymgr_gtech_syn_cfg.hjson",
+ "{proj_root}/hw/ip/kmac/syn/kmac_gtech_syn_cfg.hjson",
+ "{proj_root}/hw/ip/lc_ctrl/syn/lc_ctrl_gtech_syn_cfg.hjson",
+ "{proj_root}/hw/ip/otbn/syn/otbn_gtech_syn_cfg.hjson",
+ "{proj_root}/hw/ip/otp_ctrl/syn/otp_ctrl_gtech_syn_cfg.hjson",
+ "{proj_root}/hw/ip/rv_core_ibex/syn/rv_core_ibex_gtech_syn_cfg.hjson",
+ // Top-level GTECH synthesis flows.
+ // TODO: align Verilator and ASIC versions.
+ "{proj_root}/hw/top_earlgrey/syn/top_earlgrey_gtech_syn_cfg.hjson"]
+}
diff --git a/hw/top_earlgrey/syn/top_earlgrey_gtech_syn_cfg.hjson b/hw/top_earlgrey/syn/top_earlgrey_gtech_syn_cfg.hjson
new file mode 100644
index 0000000..482543a
--- /dev/null
+++ b/hw/top_earlgrey/syn/top_earlgrey_gtech_syn_cfg.hjson
@@ -0,0 +1,24 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ // Top level dut name (sv module).
+ name: top_earlgrey
+
+ // Fusesoc core file used for building the file list.
+ fusesoc_core: lowrisc:systems:top_earlgrey:0.1
+
+ import_cfgs: [// Project wide common GTECH synthesis config file
+ "{proj_root}/hw/syn/tools/dvsim/common_gtech_syn_cfg.hjson"]
+
+ overrides: [
+ {
+ name: design_level
+ value: "top"
+ }
+ { // Deletes black-boxed hierarchies before writing out the unmapped netlist
+ name: post_elab_script
+ value: "{proj_root}/hw/top_earlgrey/syn/post_elab_gtech.tcl"
+ }
+ ]
+}
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core
index c141a90..b00b7e9 100644
--- a/hw/top_earlgrey/top_earlgrey.core
+++ b/hw/top_earlgrey/top_earlgrey.core
@@ -91,6 +91,9 @@
SYNTHESIS:
datatype: bool
paramtype: vlogdefine
+ AST_BYPASS_CLK:
+ datatype: bool
+ paramtype: vlogdefine
targets:
default: &default_target
@@ -112,6 +115,7 @@
default_tool: verilator
parameters:
- SYNTHESIS=true
+ - AST_BYPASS_CLK=true
tools:
verilator:
mode: lint-only
@@ -126,6 +130,7 @@
default_tool: icarus
parameters:
- SYNTHESIS=true
+ - AST_BYPASS_CLK=true
toplevel: top_earlgrey
formal:
