[mask_rom] Refactor alert driver to use sec_mmio
1. Update abs_mmio calls to sec_mmio calls.
2. Update the unit and functional tests.
Signed-off-by: Chris Frantz <cfrantz@google.com>
diff --git a/sw/device/silicon_creator/lib/base/mock_sec_mmio.h b/sw/device/silicon_creator/lib/base/mock_sec_mmio.h
index b55c953..d327545 100644
--- a/sw/device/silicon_creator/lib/base/mock_sec_mmio.h
+++ b/sw/device/silicon_creator/lib/base/mock_sec_mmio.h
@@ -54,17 +54,12 @@
/**
* Expect a shadowed write to the given offset with the given 32-bit value.
*
- * The value may be given as an integer, a pointer to little-endian data,
- * or a `std::initializer_list<BitField>`.
- *
- * This function is only available in tests using a fixture that derives
- * `MmioTest`.
- *
- * This expectation is sequenced with all other `EXPECT_SEC_READ` and
- * `EXPECT_SEC_WRITE` calls.
+ * @param addr Write address.
+ * @param ... Expected value to be written. May be an integer, a pointer to
+ * little-endian data, or a `std::initializer_list<BitField>`.
*/
-#define EXPECT_SEC_WRITE32_SHADOWED(mmio, addr, ...) \
- EXPECT_CALL(mmio, \
+#define EXPECT_SEC_WRITE32_SHADOWED(addr, ...) \
+ EXPECT_CALL(::mask_rom_test::MockSecMmio::Instance(), \
Write32Shadowed(addr, mock_mmio::ToInt<uint32_t>(__VA_ARGS__)));
extern "C" {
diff --git a/sw/device/silicon_creator/lib/base/sec_mmio.c b/sw/device/silicon_creator/lib/base/sec_mmio.c
index 0eb0cff..0267bc8 100644
--- a/sw/device/silicon_creator/lib/base/sec_mmio.c
+++ b/sw/device/silicon_creator/lib/base/sec_mmio.c
@@ -85,7 +85,7 @@
}
void sec_mmio_write32_shadowed(uint32_t addr, uint32_t value) {
- // Shadowed register require two writes.
+ // Shadowed registers require two writes.
abs_mmio_write32(addr, value);
abs_mmio_write32(addr, value);
uint32_t masked_value = value ^ kSecMmioMaskVal;
diff --git a/sw/device/silicon_creator/lib/base/sec_mmio.h b/sw/device/silicon_creator/lib/base/sec_mmio.h
index 631277b..af80850 100644
--- a/sw/device/silicon_creator/lib/base/sec_mmio.h
+++ b/sw/device/silicon_creator/lib/base/sec_mmio.h
@@ -158,7 +158,7 @@
* `offset`.
*
* This function implements a write-write-read-comparison operation for shadowed
- * registers.. The first write value is stored in the list of expected register
+ * registers. The first write value is stored in the list of expected register
* values for later comparison via `sec_mmio_check_values()`.
*
* On successful calls, this function will increment the internal count of
diff --git a/sw/device/silicon_creator/lib/drivers/alert.c b/sw/device/silicon_creator/lib/drivers/alert.c
index 63aa050..5f15e59 100644
--- a/sw/device/silicon_creator/lib/drivers/alert.c
+++ b/sw/device/silicon_creator/lib/drivers/alert.c
@@ -5,7 +5,7 @@
#include "sw/device/silicon_creator/lib/drivers/alert.h"
#include "sw/device/lib/base/macros.h"
-#include "sw/device/silicon_creator/lib/base/abs_mmio.h"
+#include "sw/device/silicon_creator/lib/base/sec_mmio.h"
#include "sw/device/silicon_creator/lib/error.h"
#include "alert_handler_regs.h"
@@ -24,22 +24,22 @@
switch (cls) {
case kAlertClassA:
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA);
break;
case kAlertClassB:
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB);
break;
case kAlertClassC:
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC);
break;
case kAlertClassD:
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD);
break;
@@ -54,13 +54,13 @@
break;
case kAlertEnableLocked:
// Enable, then lock.
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET + index, 1);
- abs_mmio_write32(kBase + ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET + index,
+ sec_mmio_write32(kBase + ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET + index,
0);
break;
case kAlertEnableEnabled:
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET + index, 1);
break;
default:
@@ -79,22 +79,22 @@
switch (cls) {
case kAlertClassA:
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA);
break;
case kAlertClassB:
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB);
break;
case kAlertClassC:
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC);
break;
case kAlertClassD:
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD);
break;
@@ -109,13 +109,13 @@
break;
case kAlertEnableLocked:
// Enable, then lock.
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET + index, 1);
- abs_mmio_write32(
+ sec_mmio_write32(
kBase + ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET + index, 0);
break;
case kAlertEnableEnabled:
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET + index, 1);
break;
default:
@@ -201,23 +201,23 @@
return kErrorAlertBadEscalation;
}
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET + offset, reg);
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET + offset,
config->accum_threshold);
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET + offset,
config->timeout_cycles);
for (size_t i = 0; i < 4; ++i) {
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET + offset +
i * 4,
config->phase_cycles[i]);
}
if (config->enabled == kAlertEnableLocked) {
// Lock the alert configuration if it is configured to be locked.
- abs_mmio_write32(kBase + ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET + offset,
+ sec_mmio_write32(kBase + ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET + offset,
0);
}
return kErrorOk;
@@ -225,8 +225,8 @@
rom_error_t alert_ping_enable(void) {
// Enable the ping timer, then lock it.
- abs_mmio_write32_shadowed(
+ sec_mmio_write32_shadowed(
kBase + ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET, 1);
- abs_mmio_write32(kBase + ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET, 0);
+ sec_mmio_write32(kBase + ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET, 0);
return kErrorOk;
}
diff --git a/sw/device/silicon_creator/lib/drivers/alert_functest.c b/sw/device/silicon_creator/lib/drivers/alert_functest.c
index 13e6bda..9bea697 100644
--- a/sw/device/silicon_creator/lib/drivers/alert_functest.c
+++ b/sw/device/silicon_creator/lib/drivers/alert_functest.c
@@ -12,6 +12,7 @@
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/runtime/print.h"
#include "sw/device/silicon_creator/lib/base/abs_mmio.h"
+#include "sw/device/silicon_creator/lib/base/sec_mmio.h"
#include "sw/device/silicon_creator/lib/drivers/alert.h"
#include "sw/device/silicon_creator/lib/drivers/rstmgr.h"
#include "sw/device/silicon_creator/lib/error.h"
@@ -37,6 +38,9 @@
kFlashBase = TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR,
};
+// sec_mmio (used by the alert driver) requires this symbol to be defined.
+sec_mmio_ctx_t sec_mmio_ctx;
+
rom_error_t alert_no_escalate_test(void) {
// Configure class B alerts for phase 0 only and disable NMI signalling.
alert_class_config_t config = {
diff --git a/sw/device/silicon_creator/lib/drivers/alert_unittest.cc b/sw/device/silicon_creator/lib/drivers/alert_unittest.cc
index 64607cb..d5ed258 100644
--- a/sw/device/silicon_creator/lib/drivers/alert_unittest.cc
+++ b/sw/device/silicon_creator/lib/drivers/alert_unittest.cc
@@ -6,7 +6,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
-#include "sw/device/silicon_creator/lib/base/mock_abs_mmio.h"
+#include "sw/device/silicon_creator/lib/base/mock_sec_mmio.h"
#include "alert_handler_regs.h" // Generated.
#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
@@ -17,7 +17,7 @@
class AlertTest : public mask_rom_test::MaskRomTest {
protected:
uint32_t base_ = TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR;
- mask_rom_test::MockAbsMmio mmio_;
+ mask_rom_test::MockSecMmio mmio_;
};
class InitTest : public AlertTest {};
@@ -36,8 +36,8 @@
TEST_F(InitTest, AlertConfigureAlertBadEnable) {
// We expect the alert to get configured as class A, but then to
// experience an error when evaluating the enable parameter.
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET, 0);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET, 0);
EXPECT_EQ(alert_configure(0, kAlertClassA, (alert_enable_t)-1),
kErrorAlertBadEnable);
}
@@ -51,72 +51,71 @@
}
TEST_F(InitTest, AlertConfigure0AsClassA) {
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET, 0);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET, 0);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET, 1);
EXPECT_EQ(alert_configure(0, kAlertClassA, kAlertEnableEnabled), kErrorOk);
}
TEST_F(InitTest, LocalAlertConfigure0AsClassA) {
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET, 0);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET, 0);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET, 1);
EXPECT_EQ(alert_local_configure(0, kAlertClassA, kAlertEnableEnabled),
kErrorOk);
}
TEST_F(InitTest, AlertConfigure1AsClassB) {
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET, 1);
EXPECT_EQ(alert_configure(1, kAlertClassB, kAlertEnableEnabled), kErrorOk);
}
TEST_F(InitTest, LocalAlertConfigure1AsClassB) {
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET, 1);
EXPECT_EQ(alert_local_configure(1, kAlertClassB, kAlertEnableEnabled),
kErrorOk);
}
TEST_F(InitTest, AlertConfigure2AsClassC) {
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET, 2);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET, 2);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET, 1);
EXPECT_EQ(alert_configure(2, kAlertClassC, kAlertEnableEnabled), kErrorOk);
}
TEST_F(InitTest, LocalAlertConfigure2AsClassC) {
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET, 2);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET, 2);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET, 1);
EXPECT_EQ(alert_local_configure(2, kAlertClassC, kAlertEnableEnabled),
kErrorOk);
}
TEST_F(InitTest, AlertConfigure3AsClassDLocked) {
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET, 3);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_ALERT_REGWEN_3_REG_OFFSET, 0);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET, 3);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32(base_ + ALERT_HANDLER_ALERT_REGWEN_3_REG_OFFSET, 0);
EXPECT_EQ(alert_configure(3, kAlertClassD, kAlertEnableLocked), kErrorOk);
}
TEST_F(InitTest, LocalAlertConfigure3AsClassDLocked) {
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET, 3);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET,
- 0);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET, 3);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32(base_ + ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET, 0);
EXPECT_EQ(alert_local_configure(3, kAlertClassD, kAlertEnableLocked),
kErrorOk);
}
@@ -134,8 +133,8 @@
.timeout_cycles = 2,
.phase_cycles = {1, 10, 100, 1000},
};
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET,
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET,
{
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT, true},
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT, true},
@@ -148,19 +147,19 @@
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET, 2},
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET, 3},
});
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET, 2);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET, 10);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET, 100);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET, 1000);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET, 0);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET, 2);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET, 10);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET, 100);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET, 1000);
+ EXPECT_SEC_WRITE32(base_ + ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET, 0);
EXPECT_EQ(alert_class_configure(kAlertClassA, &config), kErrorOk);
}
@@ -172,8 +171,8 @@
.timeout_cycles = 2,
.phase_cycles = {1, 10, 100, 1000},
};
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET,
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET,
{
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT, true},
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT, false},
@@ -186,18 +185,18 @@
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET, 2},
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET, 3},
});
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET, 2);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET, 10);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET, 100);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET, 1000);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET, 2);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET, 10);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET, 100);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET, 1000);
EXPECT_EQ(alert_class_configure(kAlertClassB, &config), kErrorOk);
}
@@ -209,8 +208,8 @@
.timeout_cycles = 2,
.phase_cycles = {1, 10, 100, 1000},
};
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET,
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET,
{
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT, true},
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT, false},
@@ -223,18 +222,18 @@
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET, 2},
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET, 3},
});
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET, 2);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET, 10);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET, 100);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET, 1000);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET, 2);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET, 10);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET, 100);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET, 1000);
EXPECT_EQ(alert_class_configure(kAlertClassC, &config), kErrorOk);
}
@@ -246,8 +245,8 @@
.timeout_cycles = 2,
.phase_cycles = {1, 10, 100, 1000},
};
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET,
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET,
{
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT, true},
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT, false},
@@ -260,18 +259,18 @@
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET, 2},
{ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET, 3},
});
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET, 2);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET, 10);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET, 100);
- EXPECT_ABS_WRITE32_SHADOWED(
- mmio_, base_ + ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET, 1000);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET, 2);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET, 1);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET, 10);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET, 100);
+ EXPECT_SEC_WRITE32_SHADOWED(
+ base_ + ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET, 1000);
EXPECT_EQ(alert_class_configure(kAlertClassD, &config), kErrorOk);
}
diff --git a/sw/device/silicon_creator/lib/drivers/meson.build b/sw/device/silicon_creator/lib/drivers/meson.build
index 7a05000..c81a33b 100644
--- a/sw/device/silicon_creator/lib/drivers/meson.build
+++ b/sw/device/silicon_creator/lib/drivers/meson.build
@@ -239,7 +239,7 @@
'alert.c',
],
dependencies: [
- sw_silicon_creator_lib_base_abs_mmio,
+ sw_silicon_creator_lib_base_sec_mmio,
],
),
)
@@ -253,7 +253,7 @@
],
dependencies: [
sw_vendor_gtest,
- sw_silicon_creator_lib_base_mock_abs_mmio,
+ sw_silicon_creator_lib_base_mock_sec_mmio,
],
native: true,
c_args: ['-DMOCK_ABS_MMIO'],
@@ -273,6 +273,8 @@
'alert_functest.c'
],
dependencies: [
+ sw_silicon_creator_lib_base_abs_mmio,
+ sw_silicon_creator_lib_base_sec_mmio,
sw_silicon_creator_lib_driver_alert,
sw_silicon_creator_lib_driver_rstmgr,
],
