fix(reggen): Use abs import
As recommended in:
- https://peps.python.org/pep-0008/#imports
- https://google.github.io/styleguide/pyguide.html
Use absolute path for importing intra-packge modules.
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/util/reggen/access.py b/util/reggen/access.py
index 92fd078..23de055 100644
--- a/util/reggen/access.py
+++ b/util/reggen/access.py
@@ -7,7 +7,7 @@
from enum import Enum
-from .lib import check_str
+from reggen.lib import check_str
class JsonEnum(Enum):
diff --git a/util/reggen/alert.py b/util/reggen/alert.py
index a23ff49..f8cc49f 100644
--- a/util/reggen/alert.py
+++ b/util/reggen/alert.py
@@ -4,9 +4,9 @@
from typing import Dict, List
-from .bits import Bits
-from .signal import Signal
-from .lib import check_keys, check_name, check_str, check_list
+from reggen.bits import Bits
+from reggen.signal import Signal
+from reggen.lib import check_keys, check_name, check_str, check_list
class Alert(Signal):
diff --git a/util/reggen/bits.py b/util/reggen/bits.py
index ccfc01f..46a7907 100644
--- a/util/reggen/bits.py
+++ b/util/reggen/bits.py
@@ -6,8 +6,8 @@
from typing import Tuple
-from .lib import check_str
-from .params import ReggenParams
+from reggen.lib import check_str
+from reggen.params import ReggenParams
class Bits:
diff --git a/util/reggen/bus_interfaces.py b/util/reggen/bus_interfaces.py
index 0c7c439..fbeb99c 100644
--- a/util/reggen/bus_interfaces.py
+++ b/util/reggen/bus_interfaces.py
@@ -6,8 +6,8 @@
from typing import Dict, List, Optional, Tuple
-from .inter_signal import InterSignal
-from .lib import check_list, check_keys, check_str, check_optional_str
+from reggen.inter_signal import InterSignal
+from reggen.lib import check_list, check_keys, check_str, check_optional_str
class BusInterfaces:
diff --git a/util/reggen/clocking.py b/util/reggen/clocking.py
index 3bec741..5e3a2cd 100644
--- a/util/reggen/clocking.py
+++ b/util/reggen/clocking.py
@@ -5,10 +5,10 @@
'''Code representing clocking or resets for an IP block'''
from typing import Dict, List, Optional
-
-from .lib import check_keys, check_list, check_bool, check_optional_name
import re
+from reggen.lib import check_keys, check_list, check_bool, check_optional_name
+
class ClockingItem:
def __init__(self,
diff --git a/util/reggen/countermeasure.py b/util/reggen/countermeasure.py
index c586372..6bac3c3 100644
--- a/util/reggen/countermeasure.py
+++ b/util/reggen/countermeasure.py
@@ -6,7 +6,7 @@
import logging as log
from typing import Dict, List, Sequence, Tuple
-from .lib import check_keys, check_str, check_list
+from reggen.lib import check_keys, check_str, check_list
# The documentation of assets and cm_types can be found here
# https://docs.opentitan.org/doc/rm/comportability_specification/#countermeasures
diff --git a/util/reggen/enum_entry.py b/util/reggen/enum_entry.py
index fe1e9ec..2eb2636 100644
--- a/util/reggen/enum_entry.py
+++ b/util/reggen/enum_entry.py
@@ -4,7 +4,7 @@
from typing import Dict
-from .lib import check_keys, check_str, check_int
+from reggen.lib import check_keys, check_str, check_int
REQUIRED_FIELDS = {
'name': ['s', "name of the member of the enum"],
diff --git a/util/reggen/field.py b/util/reggen/field.py
index 32ce2ec..93f6428 100644
--- a/util/reggen/field.py
+++ b/util/reggen/field.py
@@ -4,14 +4,15 @@
from typing import Dict, List, Optional
-from .access import SWAccess, HWAccess
-from .bits import Bits
-from .enum_entry import EnumEntry
-from .lib import (check_keys, check_str, check_name, check_bool,
- check_list, check_str_list, check_xint)
-from .params import ReggenParams
from design.mubi.prim_mubi import is_width_valid, mubi_value_as_int # type: ignore
+from reggen.access import SWAccess, HWAccess
+from reggen.bits import Bits
+from reggen.enum_entry import EnumEntry
+from reggen.lib import (check_keys, check_str, check_name, check_bool,
+ check_list, check_str_list, check_xint)
+from reggen.params import ReggenParams
+
REQUIRED_FIELDS = {
'bits': ['b', "bit or bit range (msb:lsb)"]
}
diff --git a/util/reggen/gen_cfg_html.py b/util/reggen/gen_cfg_html.py
index a88916d..3279b7a 100644
--- a/util/reggen/gen_cfg_html.py
+++ b/util/reggen/gen_cfg_html.py
@@ -7,9 +7,9 @@
from typing import TextIO
-from .ip_block import IpBlock
-from .html_helpers import render_td
-from .signal import Signal
+from reggen.ip_block import IpBlock
+from reggen.html_helpers import render_td
+from reggen.signal import Signal
def genout(outfile: TextIO, msg: str) -> None:
diff --git a/util/reggen/gen_cheader.py b/util/reggen/gen_cheader.py
index 981c2a9..80b6fe7 100644
--- a/util/reggen/gen_cheader.py
+++ b/util/reggen/gen_cheader.py
@@ -13,13 +13,13 @@
from typing import List, Optional, Set, TextIO
-from .field import Field
-from .ip_block import IpBlock
-from .params import LocalParam
-from .register import Register
-from .multi_register import MultiRegister
-from .signal import Signal
-from .window import Window
+from reggen.field import Field
+from reggen.ip_block import IpBlock
+from reggen.params import LocalParam
+from reggen.register import Register
+from reggen.multi_register import MultiRegister
+from reggen.signal import Signal
+from reggen.window import Window
def genout(outfile: TextIO, msg: str) -> None:
diff --git a/util/reggen/gen_dv.py b/util/reggen/gen_dv.py
index 793d1b3..9ec4427 100644
--- a/util/reggen/gen_dv.py
+++ b/util/reggen/gen_dv.py
@@ -15,10 +15,10 @@
from mako.lookup import TemplateLookup # type: ignore
from pkg_resources import resource_filename
-from .ip_block import IpBlock
-from .multi_register import MultiRegister
-from .register import Register
-from .window import Window
+from reggen.ip_block import IpBlock
+from reggen.multi_register import MultiRegister
+from reggen.register import Register
+from reggen.window import Window
class DvBaseNames:
diff --git a/util/reggen/gen_fpv.py b/util/reggen/gen_fpv.py
index 6643aa8..84941b2 100644
--- a/util/reggen/gen_fpv.py
+++ b/util/reggen/gen_fpv.py
@@ -14,7 +14,7 @@
from mako.template import Template # type: ignore
from pkg_resources import resource_filename
-from .ip_block import IpBlock
+from reggen.ip_block import IpBlock
def gen_fpv(block: IpBlock, outdir: str) -> int:
diff --git a/util/reggen/gen_html.py b/util/reggen/gen_html.py
index e0a6892..3459ed7 100644
--- a/util/reggen/gen_html.py
+++ b/util/reggen/gen_html.py
@@ -9,12 +9,12 @@
import mistletoe as mk
-from .ip_block import IpBlock
-from .html_helpers import expand_paras, render_td
-from .multi_register import MultiRegister
-from .reg_block import RegBlock
-from .register import Register
-from .window import Window
+from reggen.ip_block import IpBlock
+from reggen.html_helpers import expand_paras, render_td
+from reggen.multi_register import MultiRegister
+from reggen.reg_block import RegBlock
+from reggen.register import Register
+from reggen.window import Window
def genout(outfile: TextIO, msg: str) -> None:
diff --git a/util/reggen/gen_rtl.py b/util/reggen/gen_rtl.py
index 83aa0cd..5edc791 100644
--- a/util/reggen/gen_rtl.py
+++ b/util/reggen/gen_rtl.py
@@ -11,11 +11,11 @@
from mako.template import Template # type: ignore
from pkg_resources import resource_filename
-from .ip_block import IpBlock
-from .lib import check_int
-from .multi_register import MultiRegister
-from .reg_base import RegBase
-from .register import Register
+from reggen.ip_block import IpBlock
+from reggen.lib import check_int
+from reggen.multi_register import MultiRegister
+from reggen.reg_base import RegBase
+from reggen.register import Register
def escape_name(name: str) -> str:
diff --git a/util/reggen/gen_rust.py b/util/reggen/gen_rust.py
index 09d2f7f..cf68409 100644
--- a/util/reggen/gen_rust.py
+++ b/util/reggen/gen_rust.py
@@ -13,13 +13,13 @@
from typing import Optional, Set, TextIO
-from .field import Field
-from .ip_block import IpBlock
-from .params import LocalParam
-from .register import Register
-from .multi_register import MultiRegister
-from .signal import Signal
-from .window import Window
+from reggen.field import Field
+from reggen.ip_block import IpBlock
+from reggen.params import LocalParam
+from reggen.register import Register
+from reggen.multi_register import MultiRegister
+from reggen.signal import Signal
+from reggen.window import Window
def genout(outfile: TextIO, msg: str) -> None:
diff --git a/util/reggen/gen_sec_cm_testplan.py b/util/reggen/gen_sec_cm_testplan.py
index c91bb14..e6e9493 100644
--- a/util/reggen/gen_sec_cm_testplan.py
+++ b/util/reggen/gen_sec_cm_testplan.py
@@ -11,7 +11,7 @@
from mako.lookup import TemplateLookup # type: ignore
from pkg_resources import resource_filename
-from .ip_block import IpBlock
+from reggen.ip_block import IpBlock
def gen_sec_cm_testplan(block: IpBlock, outdir: str) -> int:
diff --git a/util/reggen/gen_selfdoc.py b/util/reggen/gen_selfdoc.py
index 5f38404..adbef66 100644
--- a/util/reggen/gen_selfdoc.py
+++ b/util/reggen/gen_selfdoc.py
@@ -5,7 +5,7 @@
Generates the documentation for the register tool
"""
-from .access import SWACCESS_PERMITTED, HWACCESS_PERMITTED
+from reggen.access import SWACCESS_PERMITTED, HWACCESS_PERMITTED
from reggen import (validate,
ip_block, enum_entry, field,
register, multi_register, window)
diff --git a/util/reggen/gen_tock.py b/util/reggen/gen_tock.py
index b62dde9..991475e 100644
--- a/util/reggen/gen_tock.py
+++ b/util/reggen/gen_tock.py
@@ -13,11 +13,11 @@
from datetime import datetime
from typing import Any, Dict, Optional, Set, TextIO
-from .ip_block import IpBlock
-from .multi_register import MultiRegister
-from .params import LocalParam
-from .register import Register
-from .window import Window
+from reggen.ip_block import IpBlock
+from reggen.multi_register import MultiRegister
+from reggen.params import LocalParam
+from reggen.register import Register
+from reggen.window import Window
REG_VISIBILITY = 'pub(crate)'
FIELD_VISIBILITY = 'pub(crate)'
diff --git a/util/reggen/inter_signal.py b/util/reggen/inter_signal.py
index cf27d51..1c749fb 100644
--- a/util/reggen/inter_signal.py
+++ b/util/reggen/inter_signal.py
@@ -4,8 +4,8 @@
from typing import Dict, Optional
-from .lib import (check_keys, check_name,
- check_str, check_optional_str, check_int)
+from reggen.lib import (check_keys, check_name,
+ check_str, check_optional_str, check_int)
class InterSignal:
diff --git a/util/reggen/ip_block.py b/util/reggen/ip_block.py
index 1091b22..cfc99de 100644
--- a/util/reggen/ip_block.py
+++ b/util/reggen/ip_block.py
@@ -8,15 +8,15 @@
import hjson # type: ignore
-from .alert import Alert
-from .bus_interfaces import BusInterfaces
-from .clocking import Clocking, ClockingItem
-from .inter_signal import InterSignal
-from .lib import (check_keys, check_name, check_int, check_bool, check_list)
-from .params import ReggenParams, LocalParam
-from .reg_block import RegBlock
-from .signal import Signal
-from .countermeasure import CounterMeasure
+from reggen.alert import Alert
+from reggen.bus_interfaces import BusInterfaces
+from reggen.clocking import Clocking, ClockingItem
+from reggen.inter_signal import InterSignal
+from reggen.lib import (check_keys, check_name, check_int, check_bool, check_list)
+from reggen.params import ReggenParams, LocalParam
+from reggen.reg_block import RegBlock
+from reggen.signal import Signal
+from reggen.countermeasure import CounterMeasure
REQUIRED_ALIAS_FIELDS = {
diff --git a/util/reggen/multi_register.py b/util/reggen/multi_register.py
index bc2ba1f..94344f0 100644
--- a/util/reggen/multi_register.py
+++ b/util/reggen/multi_register.py
@@ -5,12 +5,12 @@
from typing import Dict, List
from reggen import register
-from .clocking import Clocking
-from .field import Field
-from .lib import check_keys, check_str, check_name, check_bool
-from .params import ReggenParams
-from .reg_base import RegBase
-from .register import Register
+from reggen.clocking import Clocking
+from reggen.field import Field
+from reggen.lib import check_keys, check_str, check_name, check_bool
+from reggen.params import ReggenParams
+from reggen.reg_base import RegBase
+from reggen.register import Register
REQUIRED_FIELDS = {
'name': ['s', "base name of the registers"],
diff --git a/util/reggen/params.py b/util/reggen/params.py
index 541625b..bae0dd5 100644
--- a/util/reggen/params.py
+++ b/util/reggen/params.py
@@ -6,7 +6,7 @@
from collections.abc import MutableMapping
from typing import Dict, Iterator, List, Optional, Tuple
-from .lib import check_keys, check_str, check_int, check_bool, check_list
+from reggen.lib import check_keys, check_str, check_int, check_bool, check_list
REQUIRED_FIELDS = {
'name': ['s', "name of the item"],
diff --git a/util/reggen/reg_base.py b/util/reggen/reg_base.py
index eb88b46..03c71f8 100644
--- a/util/reggen/reg_base.py
+++ b/util/reggen/reg_base.py
@@ -4,7 +4,7 @@
from typing import List
-from .field import Field
+from reggen.field import Field
class RegBase:
diff --git a/util/reggen/reg_block.py b/util/reggen/reg_block.py
index f3b98d2..323da31 100644
--- a/util/reggen/reg_block.py
+++ b/util/reggen/reg_block.py
@@ -7,17 +7,17 @@
import re
from typing import Callable, Dict, List, Optional, Sequence, Union
-from .alert import Alert
-from .access import SWAccess, HWAccess
-from .bus_interfaces import BusInterfaces
-from .clocking import Clocking, ClockingItem
-from .field import Field
-from .signal import Signal
-from .lib import check_int, check_list, check_str_dict, check_str
-from .multi_register import MultiRegister
-from .params import ReggenParams
-from .register import Register
-from .window import Window
+from reggen.alert import Alert
+from reggen.access import SWAccess, HWAccess
+from reggen.bus_interfaces import BusInterfaces
+from reggen.clocking import Clocking, ClockingItem
+from reggen.field import Field
+from reggen.signal import Signal
+from reggen.lib import check_int, check_list, check_str_dict, check_str
+from reggen.multi_register import MultiRegister
+from reggen.params import ReggenParams
+from reggen.register import Register
+from reggen.window import Window
class RegBlock:
diff --git a/util/reggen/register.py b/util/reggen/register.py
index 249fb49..30dd65e 100644
--- a/util/reggen/register.py
+++ b/util/reggen/register.py
@@ -4,13 +4,13 @@
from typing import Dict, List, Optional
-from .access import SWAccess, HWAccess
-from .clocking import Clocking
-from .field import Field
-from .lib import (check_keys, check_str, check_name, check_bool,
- check_list, check_str_list, check_int)
-from .params import ReggenParams
-from .reg_base import RegBase
+from reggen.access import SWAccess, HWAccess
+from reggen.clocking import Clocking
+from reggen.field import Field
+from reggen.lib import (check_keys, check_str, check_name, check_bool,
+ check_list, check_str_list, check_int)
+from reggen.params import ReggenParams
+from reggen.reg_base import RegBase
import re
@@ -447,7 +447,7 @@
if self.async_clk and self.is_hw_writable():
return True
else:
- return self.needs_qe();
+ return self.needs_qe()
def needs_re(self) -> bool:
'''Return true if at least one field needs a read-enable
diff --git a/util/reggen/signal.py b/util/reggen/signal.py
index bd4d6a3..8aa3df8 100644
--- a/util/reggen/signal.py
+++ b/util/reggen/signal.py
@@ -4,8 +4,8 @@
from typing import Dict, Sequence
-from .bits import Bits
-from .lib import check_keys, check_name, check_str, check_int, check_list
+from reggen.bits import Bits
+from reggen.lib import check_keys, check_name, check_str, check_int, check_list
class Signal:
diff --git a/util/reggen/window.py b/util/reggen/window.py
index d4355c8..15b74d0 100644
--- a/util/reggen/window.py
+++ b/util/reggen/window.py
@@ -4,9 +4,9 @@
from typing import Dict
-from .access import SWAccess
-from .lib import check_keys, check_str, check_bool, check_int
-from .params import ReggenParams
+from reggen.access import SWAccess
+from reggen.lib import check_keys, check_str, check_bool, check_int
+from reggen.params import ReggenParams
REQUIRED_FIELDS = {
