[entropy_src/rtl] Fine-tune SHA3 in FW_OV mode.
The PR makes a couple of minor adjustments after #14390, notably to
revert the FIFO clear mechanism in FW_OV_INSERT_ENTROPY mode.
Both changes treat minor corner cases, yet ones that come up often
in regression.
FW_OV mode requires special treatment as the FW_OV write FIFO does
not apply any backpressure when the IP is disabled (which the
RNG mode does have), thus we cannot assume that the user will
not _try_ to insert entropy during this time. This is a narrow
corner case, and one which generates an exception, but it is
still important for the DUT to behave in a predictable fashion.
This commit also corrects the cases where the user inserts entropy
at a valid time, but then disables the DUT before the SHA3 block can
accept it. This is technically legal, and should result in the word
being accepted and remembered by the SHA3 block.
Signed-off-by: Martin Lueker-Boden <martin.lueker-boden@wdc.com>
diff --git a/hw/ip/entropy_src/rtl/entropy_src_core.sv b/hw/ip/entropy_src/rtl/entropy_src_core.sv
index 77db8a2..0a0fc84 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_core.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_core.sv
@@ -62,7 +62,7 @@
localparam int ObserveFifoDepth = 64;
localparam int PreCondWidth = 64;
localparam int Clog2ObserveFifoDepth = $clog2(ObserveFifoDepth);
- localparam int EsEnableCopies = 34;
+ localparam int EsEnableCopies = 36;
//-----------------------
// SHA3parameters
@@ -2193,9 +2193,15 @@
assign pfifo_postht_wdata = ht_esbus_dly_q;
// For verification purposes, let post-disable data continue through to the SHA engine if it has
- // made it past the health checks. This allows scoreboards to use the same data set for the
- // SHA engine and the health-checks.
- assign pfifo_postht_clr = health_test_clr;
+ // made it past the health checks, when in standard (non-fw_ov) mode. This allows scoreboards
+ // to use the same data set for computing both the SHA engine outputs and the health-check stats.
+ //
+ // In fw_ov mode it is preferable (from a verification standpoint) to clear all FIFOs whenever
+ // disabled. Given the lack of handshaking on the fw_ov register path, this is easier to predict.
+ // Also, there is no association between SHA data and health test windows in FW_OV mode, so there
+ // is no benefit in this mode to clearing the SHA FIFOs at the same time we clear the HT
+ // statistics.
+ assign pfifo_postht_clr = fw_ov_mode_entropy_insert ? !es_enable_q_fo[23] : health_test_clr;
assign pfifo_postht_pop = ht_esbus_vld_dly2_q &&
pfifo_postht_not_empty;
@@ -2246,7 +2252,7 @@
assign hw2reg.fw_ov_rd_fifo_overflow.de = 1'b1;
assign observe_fifo_thresh_met = fw_ov_mode && (observe_fifo_thresh != '0) &&
- (observe_fifo_thresh <= sfifo_observe_depth) && es_enable_q_fo[23];
+ (observe_fifo_thresh <= sfifo_observe_depth) && es_enable_q_fo[24];
assign hw2reg.observe_fifo_depth.d = sfifo_observe_depth;
@@ -2254,7 +2260,7 @@
assign sfifo_observe_push = fw_ov_mode && pfifo_postht_pop && !sfifo_observe_full &&
(sfifo_observe_gate_q || !sfifo_observe_not_empty);
- assign sfifo_observe_clr = !es_enable_q_fo[24];
+ assign sfifo_observe_clr = !es_enable_q_fo[25];
assign sfifo_observe_wdata = pfifo_postht_rdata;
@@ -2298,9 +2304,23 @@
pfifo_postht_rdata;
// For verification purposes, let post-disable data continue through to the SHA engine if it has
- // made it past the health checks. This allows scoreboards to use the same data set for the
- // SHA engine and the health-checks.
- assign pfifo_precon_clr = health_test_clr;
+ // made it past the health checks, when in standard (non-fw_ov) mode. This allows scoreboards
+ // to use the same data set for computing both the SHA engine outputs and the health-check stats.
+ //
+ // In fw_ov mode it is preferable (from a verification standpoint) to clear all FIFOs whenever
+ // disabled. Given the lack of handshaking on the fw_ov register path, this is easier to predict.
+ // Also, there is no association between SHA data and health test windows in FW_OV mode, so there
+ // is no benefit in this mode to clearing the SHA FIFOs at the same time we clear the HT
+ // statistics.
+ //
+ // Corner case: Even in FW_OV mode, if a full SHA word is ready as the disable comes in,
+ // let it stay in the FIFO until the SHA engine has picked it up, as verification has no way
+ // of knowing if a word will get stalled by SHA backpressure. This is not a problem however
+ // as the reset is only important for clearing 32-bit half-SHA-words.
+ assign pfifo_precon_clr = fw_ov_mode_entropy_insert ?
+ !es_enable_q_fo[26] & !pfifo_precon_not_empty :
+ health_test_clr;
+
assign pfifo_precon_pop = es_bypass_mode ? pfifo_precon_not_empty :
(pfifo_precon_not_empty && sha3_msgfifo_ready);
@@ -2330,8 +2350,7 @@
// The SHA3 block cannot take messages except between the
// start and process pulses (Even though in this time it still asserts ready)
- assign sha3_msg_end = fw_ov_mode_entropy_insert ? fw_ov_sha3_disable_pulse :
- sha3_process;
+ assign sha3_msg_end = sha3_process;
assign sha3_msg_rdy_mask_d = sha3_start ? 1'b1 :
sha3_msg_end ? 1'b0 :
@@ -2419,7 +2438,8 @@
assign pfifo_bypass_push = pfifo_precon_pop && es_bypass_mode;
assign pfifo_bypass_wdata = pfifo_precon_rdata;
- assign pfifo_bypass_clr = !es_enable_q_fo[25];
+ assign pfifo_bypass_clr = !es_enable_q_fo[27];
+
assign pfifo_bypass_pop =
(es_bypass_mode && fw_ov_mode_entropy_insert) ? pfifo_bypass_not_empty : bypass_stage_pop;
@@ -2438,7 +2458,7 @@
u_entropy_src_main_sm (
.clk_i (clk_i),
.rst_ni (rst_ni),
- .enable_i (es_enable_q_fo[26]),
+ .enable_i (es_enable_q_fo[28]),
.fw_ov_ent_insert_i (fw_ov_mode_entropy_insert),
.fw_ov_sha3_start_i (fw_ov_sha3_start_pfe),
.ht_done_pulse_i (ht_done_pulse_q),
@@ -2491,14 +2511,14 @@
.err_o ()
);
- assign fips_compliance = !es_bypass_mode && es_enable_q_fo[27] && !rng_bit_en;
+ assign fips_compliance = !es_bypass_mode && es_enable_q_fo[29] && !rng_bit_en;
// fifo controls
assign sfifo_esfinal_push_enable =
(es_bypass_mode && fw_ov_mode_entropy_insert) ? pfifo_bypass_not_empty : main_stage_push;
assign sfifo_esfinal_push = sfifo_esfinal_not_full && sfifo_esfinal_push_enable;
- assign sfifo_esfinal_clr = !es_enable_q_fo[28];
+ assign sfifo_esfinal_clr = !es_enable_q_fo[30];
assign sfifo_esfinal_wdata = {fips_compliance,final_es_data};
assign sfifo_esfinal_pop = es_route_to_sw ? pfifo_swread_push :
es_hw_if_fifo_pop;
@@ -2520,7 +2540,7 @@
entropy_src_ack_sm u_entropy_src_ack_sm (
.clk_i (clk_i),
.rst_ni (rst_ni),
- .enable_i (es_enable_q_fo[29]),
+ .enable_i (es_enable_q_fo[31]),
.req_i (es_hw_if_req),
.ack_o (es_hw_if_ack),
.fifo_not_empty_i (sfifo_esfinal_not_empty && !es_route_to_sw),
@@ -2544,7 +2564,7 @@
assign es_rdata_capt_d = es_rdata_capt_vld ? sfifo_esfinal_rdata[63:0] : es_rdata_capt_q;
assign es_rdata_capt_vld_d =
- !es_enable_q_fo[30] ? 1'b0 :
+ !es_enable_q_fo[32] ? 1'b0 :
es_rdata_capt_vld ? 1'b1 :
es_rdata_capt_vld_q;
@@ -2577,11 +2597,11 @@
assign pfifo_swread_push = es_route_to_sw && pfifo_swread_not_full && sfifo_esfinal_not_empty;
assign pfifo_swread_wdata = esfinal_data;
- assign pfifo_swread_clr = !(es_enable_q_fo[31] && es_data_reg_rd_en);
- assign pfifo_swread_pop = es_enable_q_fo[32] && sw_es_rd_pulse;
+ assign pfifo_swread_clr = !(es_enable_q_fo[33] && es_data_reg_rd_en);
+ assign pfifo_swread_pop = es_enable_q_fo[34] && sw_es_rd_pulse;
// set the es entropy to the read reg
- assign es_data_reg_rd_en = es_enable_q_fo[33] && efuse_es_sw_reg_en && entropy_data_reg_en_pfe;
+ assign es_data_reg_rd_en = es_enable_q_fo[35] && efuse_es_sw_reg_en && entropy_data_reg_en_pfe;
assign hw2reg.entropy_data.d = es_data_reg_rd_en ? pfifo_swread_rdata : '0;
assign sw_es_rd_pulse = es_data_reg_rd_en && reg2hw.entropy_data.re;
