commit 2816108ad9e0a477a35e99b9d9967203ca4b42b8
author Timothy Chen <timothytim@google.com> Fri Jul 30 13:14:58 2021 -0700
committer tjaychen <timothytim@google.com> Fri Aug 06 09:58:23 2021 -0700
tree e73b37355d7c890f53f36962f1625d34d2ad2596
parent 3cda18c40d6d3afaa42744e96039e2d68b89fedf

[top] Part one of verilator refactoring

Verilator at the moment uses a custom top different from the asic / fpga
templates. As a result its logic modeling can be substantially different.

This first PR pushes the more "DV" like elements into a different testbench
file.  Once this is merged, we will begin working on using chiplevel.sv.tpl
to generate the verilator top level.

Signed-off-by: Timothy Chen <timothytim@google.com>

azure-pipelines.yml

diff --git a/azure-pipelines.yml b/azure-pipelines.yml
index 290fc67..d81559c 100644
--- a/azure-pipelines.yml
+++ b/azure-pipelines.yml
@@ -239,8 +239,8 @@
         lowrisc:systems:chip_earlgrey_verilator \
         --verilator_options="--threads 4"
 
-      cp "$OBJ_DIR/hw/sim-verilator/Vchip_earlgrey_verilator" \
-        "$BIN_DIR/hw/top_earlgrey"
+      cp "$OBJ_DIR/hw/sim-verilator/Vchip_earlgrey_verilator_tb" \
+        "$BIN_DIR/hw/top_earlgrey/Vchip_earlgrey_verilator"
     displayName: Build simulation with Verilator
   - template: ci/upload-artifacts-template.yml
     parameters: