[dv] Hard code various dv connections until full hook-up

Signed-off-by: Timothy Chen <timothytim@google.com>

[dv] more dv related fixes

Signed-off-by: Timothy Chen <timothytim@google.com>

[prim] Add auto generated fpv files

Signed-off-by: Timothy Chen <timothytim@google.com>

util/reggen/reg_top.sv.tpl

diff --git a/util/reggen/reg_top.sv.tpl b/util/reggen/reg_top.sv.tpl
index 5f37a67..ebdbc6d 100644
--- a/util/reggen/reg_top.sv.tpl
+++ b/util/reggen/reg_top.sv.tpl
@@ -313,7 +313,7 @@
 
   // this is formulated as an assumption such that the FPV testbenches do disprove this
   // property by mistake
-  `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
+  //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)
 
 endmodule
 <%def name="str_bits_sv(bits)">\