[doc/rm] Crossbar Tool
Add `tlgen.py`, more generally `util/tlgen`, document to help
understanding how the crossbar is being generated in OpenTitan and its
usage.
To generate tlgen selfdoc, validate has checker logic inside. The
checking structure (control group) is slightly changed from its in
reggen. The change makes validate to run recursively and generate the
doc recursively.
This document addresses the issue #340.
diff --git a/doc/rm/crossbar_example_1.svg b/doc/rm/crossbar_example_1.svg
new file mode 100644
index 0000000..46da11a
--- /dev/null
+++ b/doc/rm/crossbar_example_1.svg
@@ -0,0 +1 @@
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\ No newline at end of file
diff --git a/doc/rm/crossbar_tool.md b/doc/rm/crossbar_tool.md
new file mode 100644
index 0000000..f206a40
--- /dev/null
+++ b/doc/rm/crossbar_tool.md
@@ -0,0 +1,166 @@
+{{% lowrisc-doc-hdr Crossbar Generation Tool }}
+
+The crossbar tool `tlgen.py` is used to build the TL-UL crossbar RTL. It is used
+standalone or invoked as part of top module generation process.
+`hw/top_earlgrey/ip/xbar/rtl/autogen/*.sv` RTLs are generated with the crossbar
+tool. This document doesn't explain its internal blocks. [Bus
+Specification](../../hw/ip/tlul/doc/tlul.md) explains the protocol and the
+components used in the crossbar.
+
+{{% toc 3 }}
+
+## Standalone tlgen.py
+
+The standalone `tlgen.py` is a python3 script to read crossbar Hjson
+configuration file and generate crossbar package, crossbar RTL, and the simple
+DV test for checking the connectivity.
+
+The `--help` flag is supported to print the usage.
+
+### Example and Results
+
+The example of the crossbar Hjson is given in
+`util/example/tlgen/xbar_main.hjson`.
+
+The package file and RTL can be created by the command below:
+
+```console
+ $ util/tlgen.py -t util/example/tlgen/xbar_main.hjson -o /tmp/
+```
+
+It creates the files in `/tmp/{rtl|dv}`. While generating the RTL, the tool
+creates the connection information into the header of the RTL.
+
+## Configuration File Format
+
+The `tlgen` reads an Hjson file containing the crossbar connections and the
+hosts and devices information. It is the description of generic Directed Acyclic
+Graph (DAG) with some additional clock information and steering information.
+
+If the tool is used in the process of top generation (`topgen.py`), a few fields
+are derived from the top Hjson configuration module structure.
+
+A description of Hjson and the recommended style is in the [Hjson Usage and
+Style Guide](hjson_usage_style.md).
+
+The tables below describe the keys for each context. The tool raises an error if
+*Required* keys are missing. *Optional* keys may be provided in the input files.
+The tool also may insert the optional keys with default value.
+
+{{% include !../../util/tlgen.py --doc }}
+
+## Fabrication process
+
+The tool fabricates a sparse crossbar from the given Hjson configuration file.
+At first, the tool creates Vertex(Node) and Edge. Then it creates internal
+building blocks such as Asynchronous FIFO, Socket 1:N, or Socket M:1 at the
+elaboration stage. Please refer to `util/tlgen/elaborate.py` for the details.
+
+### Traversing DAG
+
+The tool, after building Nodes and Edges, traverses downstream from every Host
+nodes towards downstream during elaboration. In the process of traversal, it adds
+internal blocks if necessary. If all Nodes are visited, the tool completes
+traversing then moves to RTL generation stage.
+
+1. Generates Nodes and Edges from the Hjson. Start node should be Host and end
+ node should be Device.
+2. (for loop) Visit every hosts
+3. If a node has different clock from main clock and not Async FIFO,
+ 1. (New Node) Create Async FIFO Node.
+ 2. If the Node is host, revise every edges from the node to have start node
+ in Async FIFO. (New Edge) Create an Edge from the Node to Async FIFO. Then go to Step 3
+ with Async FIFO Node. Eventually, the connection is changed to `host ->
+ async_fifo -> downstreams` from `host -> downstreams`.
+ 3. Revise every Edge to the Node to have Async FIFO as a downstream port.
+ (New Edge) Create an Edge from the Async FIFO to the Node.
+ 4. If it is not the Device, raise Error. If it is, repeat from Step 2 with
+ next item.
+4. If a Node has multiple Edges pointing it as a downstream port, `nodes -> this
+ node` and not Socket M:1,
+ 1. (New Node) Create Socket M:1.
+ 2. Revise every Edge to the Node to point Socket M:1 as a downstream port
+ 3. (New Edge) Create an Edge from Socket M:1 to the Node.
+ The new connections look like `nodes -> socket_m1 -> this node`.
+ 4. Repeat from Step 3 with the Node.
+5. If a Node has multiple Edges and not Socket 1:N,
+ 1. (New Node) Create Socket 1:N Node.
+ 2. Revise every Edge from the Node to point to Socket 1:N as an upstream port
+ 3. (New Edge) Create an Edge from the Node to Socket 1:N.
+ 4. (for loop) Repeat from Step 3 with Socket 1:N's downstream Nodes.
+
+Below shows the example of 2 Hosts and 2 Devices connection
+
+
+
+Each circle represents a Node and an arrow represents an Edge that has downward
+direction. The tool starts from `H0` Node. As the Node has two downstream Edges
+and not Socket 1:N, the tool creates Socket 1:N based on the condition #5 above.
+Then repeat the process from Socket 1:N Node's children Nodes, `D0` and `D1`.
+
+
+
+For `D0`, the tool creates Socket M:1 based on the condition #4. Then visit its
+downstream Node, `D0` again. In this case, it doesn't create Async FIFO as the
+clock is same as main clock. So it reached the terminal Node. Then visit `D1`.
+It repeats the same step (condition #4) as `D0`, which creates another Socket
+M:1.
+
+
+
+As all Nodes from `H0` have been visited, the tool repeats all steps from `H1`.
+It applies condition #3 above as `H1` has peripheral clock rather than main
+clock. So the tool creates an Asynch FIFO and moves the pointer to the Node and
+repeats.
+
+
+
+It applies #5 as Async FIFO has multiple downstream Nodes(Edges) and it is not
+Socket 1:N. The tool creates a Socket 1:N and visit every downstream Nodes.
+
+
+
+Both Nodes are processed. So no condition is hit. The tool completes traversing.
+
+### Numbering
+
+After the traversing is completed, Hosts and Devices only have one Edge and
+internal Sockets have multiple Edges. The tool assigns increasing numbers into
+each Edge starting from 0. This helps the tool to connect between Nodes.
+
+### Propagating the steering information (Address)
+
+After the numbering is done, the tool propagates the steering information,
+address from every Device Nodes to the upstream until it hits Socket 1:N. Socket
+1:N is the only module that utilizes the `base_addr` and `size_bytes`.
+
+It is assumed that at most only one Socket 1:N exists on the path from a Host to
+a Device within a crossbar. If any SoC requires multi-tiered crossbar design, it
+should have more than one crossbar communicate each other.
+
+### Connection information
+
+The tool creates DAG connections when it creates RTL to help understanding the
+fabric. The information is put in the header of the RTL. For instance, above 2x2
+example has the information below.
+
+```
+ $ util/tlgen.py -t util/example/tlgen/xbar_2x2.hjson -o /tmp/
+ $ cat /tmp/rtl/xbar_2x2.sv
+// ...
+// Interconnect
+// h0
+// -> s1n_4
+// -> sm1_5
+// -> d0
+// -> sm1_6
+// -> d1
+// h1
+// -> asf_7
+// -> s1n_8
+// -> sm1_5
+// -> d0
+// -> sm1_6
+// -> d1
+// ...
+```
diff --git a/doc/rm/index.md b/doc/rm/index.md
index cabd236..47a08f0 100644
--- a/doc/rm/index.md
+++ b/doc/rm/index.md
@@ -2,8 +2,9 @@
* [Comportability Definition and Specification](comportability_specification.md)
* Tool Guides
- * [Register Tool](register_tool.md): Describes `regtool.py` and its HJSON format source. Used to generate documentation, rtl, header files and validation files for IP Registers and toplevel.
- * [Vendor-In Tool](vendor_hw_tool.md): Describes `vendor_hw.py` and its HJSON control file. Used to pull a local copy of code maintained in other upstream repositories and apply local patch sets.
+ * [Register Tool](register_tool.md): Describes `regtool.py` and its Hjson format source. Used to generate documentation, rtl, header files and validation files for IP Registers and toplevel.
+ * [Vendor-In Tool](vendor_hw_tool.md): Describes `vendor_hw.py` and its Hjson control file. Used to pull a local copy of code maintained in other upstream repositories and apply local patch sets.
+ * [Crossbar Tool](crossbar_tool.md): Describes `tlgen.py` and its Hjson format source. Used to generate RTL and validation files for the crossbar.
* Coding Style Guides
* [Verilog Coding Style](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md)
* [Python Coding Style](python_coding_style.md)
diff --git a/util/example/tlgen/dv/device_sram.sv b/util/example/tlgen/dv/device_sram.sv
deleted file mode 100644
index 3f0037a..0000000
--- a/util/example/tlgen/dv/device_sram.sv
+++ /dev/null
@@ -1,55 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-
-module device_sram (
- input clk_i,
-
- input tlul_pkg::tl_h2d_t tl_i,
- output tlul_pkg::tl_d2h_t tl_o
-);
-
- import tlul_pkg::*;
-
- logic [31:0] storage [*];
-
- initial begin
- tl_o.a_ready = 1'b1;
- tl_o.d_valid = 1'b0;
-
- forever begin
- @(posedge clk_i iff (tl_i.a_valid == 1'b1));
- tl_o.d_error = 1'b0;
- tl_o.d_source = tl_i.a_source;
- tl_o.d_size = tl_i.a_size;
- tl_o.d_sink = 0;
- tl_o.d_param = 2'h0;
- tl_o.d_user = 'h0;
- if (tl_i.a_opcode == Get) begin
- if (storage.exists(tl_i.a_address[31:2])) begin
- tl_o.d_data = storage[tl_i.a_address[31:2]];
- end else begin
- tl_o.d_data = $urandom();
- storage[tl_i.a_address[31:2]] = tl_o.d_data;
- end
-
- tl_o.a_ready = 1'b0;
- tl_o.d_opcode = AccessAckData;
- tl_o.d_valid = 1'b1;
- @(posedge clk_i iff (tl_i.d_ready == 1'b1));
- tl_o.d_valid = 1'b0;
- tl_o.a_ready = 1'b1;
- end else if (tl_i.a_opcode == PutFullData) begin
- storage[tl_i.a_address[31:2]] = tl_i.a_data;
- tl_o.a_ready = 1'b0;
- tl_o.d_opcode = AccessAck;
- tl_o.d_valid = 1'b1;
- @(posedge clk_i iff (tl_i.d_ready == 1'b1));
- tl_o.d_valid = 1'b0;
- tl_o.a_ready = 1'b1;
- end
- end
- end
-
-endmodule
diff --git a/util/example/tlgen/xbar_2x2.hjson b/util/example/tlgen/xbar_2x2.hjson
new file mode 100644
index 0000000..7d639d5
--- /dev/null
+++ b/util/example/tlgen/xbar_2x2.hjson
@@ -0,0 +1,15 @@
+{
+ name: "2x2",
+ clock: "main",
+ nodes: [
+ { name: "h0", type: "host", clock: "main" },
+ { name: "h1", type: "host", clock: "periph" },
+ { name: "d0", type: "device", clock: "main", base_addr: "0x0000", size_byte: "0x1000" },
+ { name: "d1", type: "device", clock: "main", base_addr: "0x1000", size_byte: "0x1000" }
+ ],
+ connections: {
+ h0: ["d0", "d1"],
+ h1: ["d0", "d1"]
+ }
+}
+
diff --git a/util/example/tlgen/top_jasmine.hjson b/util/example/tlgen/xbar_main.hjson
similarity index 91%
rename from util/example/tlgen/top_jasmine.hjson
rename to util/example/tlgen/xbar_main.hjson
index 64982dd..a242d7b 100644
--- a/util/example/tlgen/top_jasmine.hjson
+++ b/util/example/tlgen/xbar_main.hjson
@@ -7,14 +7,20 @@
{ name: "ibexif",
type: "host",
clock: "main",
+
+ pipeline: "false"
},
{ name: "ibexlsu",
type: "host",
clock: "periph",
+
+ pipeline: "false"
},
{ name: "dm_sba", // DM
type: "host",
clock: "jtag",
+
+ pipeline_byp: "false"
},
{ name: "rom",
type: "device",
@@ -22,7 +28,12 @@
base_addr: "0x00000000",
size_byte: "0x10000", // 64kB
},
- { name: "debug_rom", type: "device", clock: "jtag", base_addr: "0x10040000", size_byte: "0x1000" },
+ { name: "debug_rom",
+ type: "device",
+ clock: "jtag",
+ base_addr: "0x10040000",
+ size_byte: "0x1000"
+ },
{ name: "sram",
type: "device",
clock: "main",
diff --git a/util/example/xbar/rtl/xbar.sv b/util/example/xbar/rtl/xbar.sv
deleted file mode 100644
index 89e05a4..0000000
--- a/util/example/xbar/rtl/xbar.sv
+++ /dev/null
@@ -1,61 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-module xbar(
- input clk,
- input rst_n,
-
- xbar_if.device xhif0,
- xbar_if.device xhif1,
- xbar_if.host xdif0,
- xbar_if.host xdif1,
- xbar_if.host xdif2
-);
-
- hdb_fifo_sync #(
- .ReqPass (1'b1),
- .RspPass (1'b1),
- .ReqDepth (2),
- .RspDepth (2)
- ) u_dut (
- .clk_i (xhif0.clk),
- .rst_ni (rst_n),
- .hdb_h_i (xhif0.host.h2d),
- .hdb_h_o (xhif0.host.d2h),
- .hdb_d_o (xdif0.device.h2d),
- .hdb_d_i (xdif0.device.d2h)
- );
- /*
- assign xdif0.req_valid = xhif0.req_valid;
- assign xdif0.req_addr = xhif0.req_addr ;
- assign xdif0.req_wr = xhif0.req_wr ;
- assign xdif0.req_wdata = xhif0.req_wdata;
- assign xdif0.req_wstrb = xhif0.req_wstrb;
- assign xdif0.req_attr = xhif0.req_attr ;
- assign xdif0.req_id = xhif0.req_id ;
- assign xhif0.req_ready = xdif0.req_ready;
-
- assign xhif0.rsp_valid = xdif0.rsp_valid;
- assign xhif0.rsp_rdata = xdif0.rsp_rdata;
- assign xhif0.rsp_attr = xdif0.rsp_attr ;
- assign xhif0.rsp_id = xdif0.rsp_id ;
- assign xdif0.rsp_ready = xhif0.rsp_ready;
- */
-
- hdb_fifo_async #(
- .ReqDepth (2),
- .RspDepth (2)
- ) u_dut_async (
- .clk_h_i (xhif1.clk),
- .rst_h_ni (rst_n),
- .clk_d_i (xdif1.clk),
- .rst_d_ni (rst_n),
-
- .hdb_h_i (xhif1.host.h2d),
- .hdb_h_o (xhif1.host.d2h),
- .hdb_d_o (xdif1.device.h2d),
- .hdb_d_i (xdif1.device.d2h)
- );
-
-endmodule
diff --git a/util/reggen/validate.py b/util/reggen/validate.py
index 384e142..89fed02 100644
--- a/util/reggen/validate.py
+++ b/util/reggen/validate.py
@@ -271,6 +271,8 @@
'lnw': ["name list+", 'name list that optionally contains a width'],
'lp': ["parameter list", 'parameter list having default value optionally'],
'g': ["group", "comma separated group of key:value enclosed in `{}`"],
+ 'lg': ["list of group", "comma separated group of key:value enclosed in `{}`"\
+ " the second entry of the list is the sub group format"],
's': ["string", "string, typically short"],
't': ["text", "string, may be multi-line enclosed in `'''` "\
"may use `**bold**`, `*italic*` or `!!Reg` markup"],
diff --git a/util/tlgen.py b/util/tlgen.py
index e1d2455..507c610 100755
--- a/util/tlgen.py
+++ b/util/tlgen.py
@@ -22,13 +22,15 @@
parser.add_argument('--topcfg',
'-t',
metavar='file',
- required=True,
type=argparse.FileType('r'),
help="`top_cfg.hjson` file.")
+ parser.add_argument('--doc',
+ '-d',
+ action='store_true',
+ help='Generate self html document in stdout')
parser.add_argument(
'--outdir',
'-o',
- required=True,
help=
"Target directory. tlgen needs 'rtl/' and 'dv/' directory under the target dir"
)
@@ -41,6 +43,15 @@
else:
log.basicConfig(format="%(levelname)s: %(message)s")
+ if args.doc:
+ # Generate Doc and return
+ sys.stdout.write(tlgen.selfdoc(heading=3, cmd='tlgen.py --doc'))
+ return
+
+ # Check if topcfg defined
+ if not args.topcfg or not args.outdir:
+ log.error("--topcfg option is mandatory to generate codes.")
+
# Check if outdir exists. If not, show error and exit
if not Path(args.outdir).is_dir():
log.error("'--outdir' should point to writable directory")
diff --git a/util/tlgen/__init__.py b/util/tlgen/__init__.py
index 7534400..50dfac7 100644
--- a/util/tlgen/__init__.py
+++ b/util/tlgen/__init__.py
@@ -7,3 +7,4 @@
from .item import Edge, Node, NodeType
from .validate import validate
from .xbar import Xbar
+from .doc import selfdoc
diff --git a/util/tlgen/doc.py b/util/tlgen/doc.py
new file mode 100644
index 0000000..1c0bf83
--- /dev/null
+++ b/util/tlgen/doc.py
@@ -0,0 +1,94 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+"""TileLink-Uncached Lightweight Xbar self document
+"""
+import logging as log
+
+from .validate import *
+
+doc_intro = """
+
+(start of output generated by `{}`)
+
+The tables describe each key and the type of the value. The following
+types are used:
+
+Type | Description
+---- | -----------
+"""
+
+doc_tail = """
+
+(end of output generated by `{}`)
+
+"""
+
+
+def print_control(control, heading):
+ """Print a control group and its subgroup recursively
+ """
+ subgroup = [] # added if the field hit sub control group
+
+ outstr = '#' * heading + ' ' + control['name'] + '\n'
+ outstr += '\n'
+
+ outstr += control['description']
+ outstr += '\n\n'
+
+ items = {**control['required'], **control['optional'], **control['added']}
+
+ if len(items) > 0:
+ outstr += """
+Field | Kind | Type | Description
+----- | ---- | ---- | ------------
+"""
+ for k, v in items.items():
+ if k in control['required']:
+ kind = "required"
+ elif k in control['optional']:
+ kind = "optional"
+ else:
+ kind = "added by tool"
+
+ v_type = val_types[v[0]][0]
+
+ if v[0] == 'lg':
+ subgroup.append(v[1])
+ log.error(val_types[v[0]])
+ outstr += '{} | {} | {} | List of {} group\n'.format(
+ k, kind, v_type, k)
+ continue
+ elif v[0] == 'g':
+ if not isinstance(v[1], str):
+ subgroup.append(v[1])
+ outstr += '{} | {} | {} | {} group\n'.format(
+ k, kind, v_type, k)
+ continue
+
+ # Generic string print
+ outstr += '{} | {} | {} | {}\n'.format(k, kind, v_type, v[1])
+
+ outstr += "\n\n"
+ # recursive subgroup
+ for e in subgroup:
+ outstr += print_control(e, heading)
+
+ return outstr
+
+
+def selfdoc(heading, cmd=""):
+ # heading : markdown header depth
+ # value type
+ outstr = doc_intro.format(cmd)
+
+ for k, v in val_types.items():
+ outstr += v[0] + " | " + v[1] + "\n"
+
+ # root + subgroup
+ outstr += print_control(root, heading)
+
+ # connections: Needs custom as the key are hosts (can vary)
+ outstr += doc_tail.format(cmd)
+
+ return outstr
diff --git a/util/tlgen/validate.py b/util/tlgen/validate.py
index e573a67..ce232f4 100644
--- a/util/tlgen/validate.py
+++ b/util/tlgen/validate.py
@@ -3,10 +3,154 @@
# SPDX-License-Identifier: Apache-2.0
import logging as log
from collections import OrderedDict
+from functools import partial
from .item import Edge, Node, NodeType
from .xbar import Xbar
+from reggen.validate import val_types, check_int, check_bool, check_ln
+
+# val_types = {
+# 'd': ["int", "integer (binary 0b, octal 0o, decimal, hex 0x)"],
+# 'x': ["xint", "x for undefined otherwise int"],
+# 'b': [
+# "bitrange", "bit number as decimal integer, \
+# or bit-range as decimal integers msb:lsb"
+# ],
+# 'l': ["list", "comma separated list enclosed in `[]`"],
+# 'ln': ["name list", 'comma separated list enclosed in `[]` of '\
+# 'one or more groups that have just name and dscr keys.'\
+# ' e.g. `{ name: "name", desc: "description"}`'],
+# 'lnw': ["name list+", 'name list that optionally contains a width'],
+# 'lp': ["parameter list", 'parameter list having default value optionally'],
+# 'g': ["group", "comma separated group of key:value enclosed in `{}`"],
+# 'lg': ["list of group", "comma separated group of key:value enclosed in `{}`"\
+# " the second entry of the list is the sub group format"],
+# 's': ["string", "string, typically short"],
+# 't': ["text", "string, may be multi-line enclosed in `'''` "\
+# "may use `**bold**`, `*italic*` or `!!Reg` markup"],
+# 'T': ["tuple", "tuple enclosed in ()"],
+# 'pi': ["python int", "Native python type int (generated)"],
+# 'pb': ["python Bool", "Native python type Bool (generated)"],
+# 'pl': ["python list", "Native python type list (generated)"],
+# 'pe': ["python enum", "Native python type enum (generated)"]
+# }
+node = {
+ 'name': 'Node configuration',
+ 'description': '''
+Crossbar node description. It can be host, device, or internal nodes.
+''',
+ 'required': {
+ 'name': ['s', 'Module instance name'],
+ 'type': ['s', 'Module type: {"host", "device", "async", "socket_1n", "socket_m1"}'],
+ },
+ 'optional': {
+ 'clock': ['s', 'main clock of the port'],
+ 'base_addr': ['d', 'Base address of the device'\
+ ' It is required for the device'],
+ 'size_byte': ['d', 'Memory space of the device'\
+ ' It is required for the device'],
+ 'pipeline': ['pb', 'If true, pipeline is added in front of the port'],
+ 'pipeline_byp': ['pb', 'Pipeline bypass. If true, '\
+ 'request/response are not latched']
+ },
+ 'added': {}
+}
+root = {
+ 'name': 'Top configuration',
+ 'description': '''
+Crossbar configuration format.
+''',
+ 'required': {
+ 'name': ['s', 'Name of the crossbar'],
+ 'clock': ['s', 'Main clock. Internal components use this clock.'\
+ ' If not specified, it is assumed to be in main clock domain'],
+ 'connections':
+ ['g', "List of edge. Key is host, entry in value list is device"],
+ 'nodes': ['lg', node]
+ },
+ 'optional': {
+ 'type': ['s', 'Indicate hjson type. "xbar" always if exist']
+ },
+ 'added': {
+ 'reset_connections': ['g', "Generated by topgen. Key is the reset signal inside IP"\
+ " and value is the top reset signal"],
+ }
+}
+
+
+def check_keys(obj, control, prefix=""):
+ """ Check the keys recursively.
+
+ The control parameter is a control group to check obj data structure.
+ """
+ error = 0
+
+ # required
+ for k, v in control["required"].items():
+ if not k in obj:
+ error += 1
+ log.error(prefix + " missing required key " + k)
+
+ # Check every fields' correctness
+ for k, v in obj.items():
+ checker = ['', '']
+ prefix_name = prefix + " " + k
+
+ if k in control["required"]:
+ checker = control["required"][k]
+ elif k in control["optional"]:
+ checker = control["optional"][k]
+ elif k in control["added"]:
+ log.warning(prefix + " contains generated key " + k)
+ checker = control["added"][k]
+ else:
+ log.warning(prefix + " contains extra key " + k)
+ continue
+
+ # Type and value check
+ if not checker[0] in val_types:
+ log.error(prefix +
+ " field {} is undefined type. Check val_types {}".format(
+ k, checker[0]))
+ if checker[0] == 'lg':
+ # List of subgroup
+ error += sum(
+ map(
+ partial(check_keys, control=checker[1],
+ prefix=prefix_name), obj[k]))
+ elif checker[0] == 'g':
+ # if second entry isn't string type, call recursively
+ if isinstance(checker[1], str):
+ log.info(
+ "Skipping {} as no further control group is given".format(
+ prefix_name))
+ continue
+
+ error += check_keys(obj=obj[k],
+ control=checker[1],
+ prefix=prefix_name)
+
+ elif checker[0] == 'd':
+ int_v, err = check_int(obj[k], prefix_name)
+ if err:
+ error += 1
+
+ elif checker[0] == 's' or checker[0] == 't':
+ # don't care the string
+ pass
+
+ elif checker[0] == 'pb':
+ b_v, err = check_bool(obj[k], prefix_name)
+ if err:
+ error += 1
+
+ else:
+ log.error(prefix_name +
+ " is not supported in this configuration format")
+
+ return error
+
def get_nodetype(t): # t: str -> NodeType
if t == "host":
@@ -44,6 +188,11 @@
addr_ranges = []
+ obj, err = validate_hjson(obj) # validate hjson format first
+ if err > 0:
+ log.error("Hjson structure error")
+ return
+
# Nodes
for nodeobj in obj["nodes"]:
clock = nodeobj["clock"].lower() if "clock" in nodeobj.keys(
@@ -78,9 +227,15 @@
node.pipeline = True if nodeobj["pipeline"].lower() in [
"true", "1"
] else False
+ else:
+ node.pipeline = False
+ if node.node_type in [NodeType.DEVICE, NodeType.HOST
+ ] and "pipeline_byp" in nodeobj:
node.pipeline_byp = True if nodeobj["pipeline_byp"].lower() in [
"true", "1"
] else False
+ else:
+ node.pipeline_byp = True
xbar.nodes.append(node)
# Edge
@@ -90,3 +245,19 @@
xbar.connect_nodes(host.lower(), device.lower())
return xbar
+
+
+def validate_hjson(obj):
+ if not "type" in obj:
+ obj["type"] = "xbar"
+ if not "name" in obj:
+ log.error("Component has no name. Aborting.")
+ return None, 1
+
+ component = obj["name"]
+ error = check_keys(obj, root, component)
+
+ if error > 0:
+ log.error("{} has top level error. Aborting".format(component))
+ return None, error
+ return obj, 0
