commit 260e1bde33d73722ac21935a2fb6ec1e006e9d2d
author Weicai Yang <weicai@google.com> Mon Sep 16 16:20:15 2019 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Mon Sep 16 18:10:19 2019 -0700
tree 1c55221e810bef924d3b9d443478b87a8e17926b
parent 006e2e1b0a7269f5d1c29c4264d888a8e02a0db3

[dv] Fix xcelium compile errors

1. use wire struct in tl_if
2. change uart_tx to wire
3. fix tl_device_driver hierarchy path typo

hw/dv/sv/tl_agent/tl_device_driver.sv

diff --git a/hw/dv/sv/tl_agent/tl_device_driver.sv b/hw/dv/sv/tl_agent/tl_device_driver.sv
index a023a71..5ea43d6 100644
--- a/hw/dv/sv/tl_agent/tl_device_driver.sv
+++ b/hw/dv/sv/tl_agent/tl_device_driver.sv
@@ -64,7 +64,7 @@
       end else begin
         d_valid_delay = $urandom_range(cfg.d_valid_delay_min, cfg.d_valid_delay_max);
       end
-      repeat (d_valid_delay) @(vif.host_cb);
+      repeat (d_valid_delay) @(vif.device_cb);
       vif.device_cb.d2h.d_valid  <= 1'b1;
       vif.device_cb.d2h.d_opcode <= tlul_pkg::tl_d_op_e'(rsp.d_opcode);
       vif.device_cb.d2h.d_data   <= rsp.d_data;

hw/dv/sv/tl_agent/tl_if.sv

diff --git a/hw/dv/sv/tl_agent/tl_if.sv b/hw/dv/sv/tl_agent/tl_if.sv
index dc04668..a642d12 100644
--- a/hw/dv/sv/tl_agent/tl_if.sv
+++ b/hw/dv/sv/tl_agent/tl_if.sv
@@ -7,8 +7,10 @@
 // ---------------------------------------------
 interface tl_if(input clk, input rst_n);
 
-  tlul_pkg::tl_h2d_t h2d; // req
-  tlul_pkg::tl_d2h_t d2h; // rsp
+  wire tlul_pkg::tl_h2d_t h2d; // req
+  wire tlul_pkg::tl_d2h_t d2h; // rsp
+  modport dut_host_mp(output h2d, input d2h);
+  modport dut_device_mp(input h2d, output d2h);
 
   clocking host_cb @(posedge clk);
     input  rst_n;

hw/dv/sv/uart_agent/uart_if.sv

diff --git a/hw/dv/sv/uart_agent/uart_if.sv b/hw/dv/sv/uart_agent/uart_if.sv
index b70a99c..d31985f 100644
--- a/hw/dv/sv/uart_agent/uart_if.sv
+++ b/hw/dv/sv/uart_agent/uart_if.sv
@@ -4,7 +4,7 @@
 //
 interface uart_if #(time UartDefaultClkPeriodNs = 104166.667ns) ();
   logic uart_rx;
-  logic uart_tx;
+  wire uart_tx;
   logic uart_tx_en;
 
   // generate local clk
@@ -14,11 +14,6 @@
   bit   uart_rx_clk = 1'b1;
   int   uart_rx_clk_pulses = 0;
 
-  clocking drv_tx_cb @(posedge uart_tx_clk);
-    output uart_tx;
-  endclocking
-  modport drv_tx_mp(clocking drv_tx_cb);
-
   clocking mon_tx_cb @(negedge uart_tx_clk);
     input  #10ns uart_tx;
   endclocking