[prim_ram*_adv] Update top_earlgrey and DV/Verilator memory paths

This updates all DV related hierarchical paths to the main memory, and
updates its instantiation in top-earlgrey. Note that parity is not yet
enabled for the main memory, since we still lack support for that in the
backdoor memory loading mechanisms.

Signed-off-by: Michael Schaffner <msf@google.com>

hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index b852efa..4ef2db9 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -419,7 +419,9 @@
     .Width(32),
     .Depth(16384),
     .DataBitsPerMask(8),
-    .CfgW(8)
+    .CfgW(8),
+    // TODO: enable parity once supported by the simulation infrastructure
+    .EnableParity(0)
   ) u_ram1p_ram_main (
     .clk_i   (clkmgr_clocks.clk_main_infra),
     .rst_ni   (rstmgr_resets.rst_sys_n),