| commit | 259a661278b1a5e8aa1aa3424a6bef6a7675efae | [log] [tgz] |
|---|---|---|
| author | Johnathan Van Why <jrvanwhy@google.com> | Thu Sep 08 09:46:13 2022 -0700 |
| committer | Alphan Ulusoy <alphan@google.com> | Thu Sep 15 09:38:05 2022 -0400 |
| tree | a74272e3da7ebe09db44935e9156b48182147186 | |
| parent | 4ba47bb4622ae5e9331f658d383002e806bdd51e [diff] |
Move opentitantool's set-pll and load-bitstream commands into a new fpga command group. In a future PR, I will add a new command to this group to reset the FPGA board (described in #14686). Signed-off-by: Johnathan Van Why <jrvanwhy@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).