[dv] Provide bus_params_pkg
This is done to isolate the common DV components from OpenTitan specific
design constants in top_pkg.
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/dv/sv/bus_params_pkg/README.md b/hw/dv/sv/bus_params_pkg/README.md
new file mode 100644
index 0000000..826f934
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+++ b/hw/dv/sv/bus_params_pkg/README.md
@@ -0,0 +1,10 @@
+# bus_params_pkg
+
+This package provides an isolation for all common verification components under
+`hw/dv/sv/` from the OpenTitan specific design constants provided in
+`hw/top_earlgrey/rtl/top_pkg.sv`. This mostly includes common bus parameters
+such as address and data widths.
+
+When vendoring the common DV code into another repo, the other repo must
+provide its own implementation of `bus_params_pkg` so that the
+dependency on the `top_pkg` can be avoided.
diff --git a/hw/dv/sv/bus_params_pkg/bus_params_pkg.core b/hw/dv/sv/bus_params_pkg/bus_params_pkg.core
new file mode 100644
index 0000000..3cc9fb2
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+++ b/hw/dv/sv/bus_params_pkg/bus_params_pkg.core
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+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:opentitan:bus_params_pkg"
+description: "Package holding common bus parameters such as widths."
+
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:constants:top_pkg
+ files:
+ - bus_params_pkg.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/dv/sv/bus_params_pkg/bus_params_pkg.sv b/hw/dv/sv/bus_params_pkg/bus_params_pkg.sv
new file mode 100644
index 0000000..b27f406
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+++ b/hw/dv/sv/bus_params_pkg/bus_params_pkg.sv
@@ -0,0 +1,56 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package bus_params_pkg;
+
+ // Set the bus address width.
+`ifdef BUS_AW
+ parameter int BUS_AW = `BUS_AW;
+`else
+ parameter int BUS_AW = top_pkg::TL_AW;
+`endif
+
+ // Set the bus data width.
+`ifdef BUS_DW
+ parameter int BUS_DW = `BUS_DW;
+`else
+ parameter int BUS_DW = top_pkg::TL_DW;
+`endif
+
+ // Set the bus data mask width (# of byte lanes).
+`ifdef BUS_DBW
+ parameter int BUS_DBW = `BUS_DBW;
+`else
+ parameter int BUS_DBW = top_pkg::TL_DBW;
+`endif
+
+ // Set the bus transfer size width (# of bits requred to select the # of bytes).
+`ifdef BUS_SZW
+ parameter int BUS_SZW = `BUS_SZW;
+`else
+ parameter int BUS_SZW = top_pkg::TL_SZW;
+`endif
+
+// Set the bus address info (source) width.
+`ifdef BUS_AIW
+ parameter int BUS_AIW = `BUS_AIW;
+`else
+ parameter int BUS_AIW = top_pkg::TL_AIW;
+`endif
+
+// Set the bus data info (source) width.
+`ifdef BUS_DIW
+ parameter int BUS_DIW = `BUS_DIW;
+`else
+ parameter int BUS_DIW = top_pkg::TL_DIW;
+`endif
+
+// Set the bus data user width.
+`ifdef BUS_DUW
+ parameter int BUS_DUW = `BUS_DUW;
+`else
+ parameter int BUS_DUW = top_pkg::TL_DUW;
+`endif
+
+endpackage
