[prim/edn] Fix lint error (width mismatch)
prim_edn_req asynchronous FIFO has wrong width definition. It adds
`fips` signal so, the width should be increased by 1.
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/hw/ip/prim/rtl/prim_edn_req.sv b/hw/ip/prim/rtl/prim_edn_req.sv
index 75cae9d..e76fefd 100644
--- a/hw/ip/prim/rtl/prim_edn_req.sv
+++ b/hw/ip/prim/rtl/prim_edn_req.sv
@@ -38,8 +38,9 @@
logic [edn_pkg::ENDPOINT_BUS_WIDTH-1:0] word_data;
logic word_fips;
+ localparam int SyncWidth = $bits({edn_i.edn_fips, edn_i.edn_bus});
prim_sync_reqack_data #(
- .Width(edn_pkg::ENDPOINT_BUS_WIDTH),
+ .Width(SyncWidth),
.DataSrc2Dst(1'b0),
.DataReg(1'b0)
) u_prim_sync_reqack_data (
