| commit | 24baa88a432a1822ae7d1065bbd244538f38d030 | [log] [tgz] |
|---|---|---|
| author | Pirmin Vogel <vogelpi@lowrisc.org> | Sat Oct 03 20:12:10 2020 +0200 |
| committer | Pirmin Vogel <vogelpi@lowrisc.org> | Mon Oct 05 10:56:24 2020 +0200 |
| tree | e8e74ab45b6c52b86f249598915b7d2a8feea096 | |
| parent | 04f115f6f118ecc9a8b89223a03ad5f4771cd8fb [diff] |
[spiflash] Insert additional delays for robustness, increase SPI clock This commit adds two additional delays to the SPI Flash tool: - Upon receiving the first frame, the device is expected to erase the internal Flash. The host should wait for this operation to complete before requesting the hash check. - On the host side, we need to add a delay between receiving the data over SPI and actually using it. With these two changes, the tool is much more robust and we can raise the SPI clock frequency back to 1 MHz. In addition, this commit fixes some comments and variable names (all delays are given in microseconds instead of nanoseconds.) This is related to lowRISC/OpenTitan#3606. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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