[top] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
index 4e47f4d..98ca7cc 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
@@ -74,11 +74,11 @@
package: "flash_ctrl_pkg"
},
- { struct: "edn_entropy",
- type: "uni",
+ { struct: "edn",
+ type: "req_rsp",
name: "edn",
- act: "rcv",
- package: "flash_ctrl_pkg"
+ act: "req",
+ package: "edn_pkg"
},
{ struct: "pwr_flash",
@@ -107,13 +107,26 @@
type: "flash_ctrl_pkg::flash_key_t"
randcount: "128",
randtype: "data", // randomize randcount databits
- }
+ },
{ name: "RndCnstDataKey",
desc: "Compile-time random bits for default data key",
type: "flash_ctrl_pkg::flash_key_t"
randcount: "128",
randtype: "data", // randomize randcount databits
- }
+ },
+ { name: "RndCnstLfsrSeed",
+ desc: "Compile-time random bits for initial LFSR seed",
+ type: "flash_ctrl_pkg::lfsr_seed_t"
+ randcount: "32",
+ randtype: "data",
+ },
+ { name: "RndCnstLfsrPerm",
+ desc: "Compile-time random permutation for LFSR output",
+ type: "flash_ctrl_pkg::lfsr_perm_t"
+ randcount: "32",
+ randtype: "perm",
+ },
+
{ name: "RegNumBanks",
desc: "Number of flash banks",
type: "int",
@@ -393,6 +406,26 @@
]
},
+ // erase suspend support
+ { name: "ERASE_SUSPEND",
+ desc: "Suspend erase",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ resval: "0",
+ name: "REQ",
+ desc: '''
+ When 1, request erase suspend.
+ If no erase ongoing, the request is immediately cleared by hardware
+ If erase ongoing, the request is fed to the flash_phy and cleared when the suspend is handled.
+ '''
+ },
+ ],
+ tags: [// Erase suspend must be directly tested
+ "excl:CsrAllTests:CsrExclWrite"],
+ },
+
// Data partition memory properties region setup
{ multireg: {
cname: "FLASH_CTRL",
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index 2ccdca5..e5d3835 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -9,8 +9,10 @@
`include "prim_assert.sv"
module flash_ctrl import flash_ctrl_pkg::*; #(
- parameter flash_key_t RndCnstAddrKey = RndCnstAddrKeyDefault,
- parameter flash_key_t RndCnstDataKey = RndCnstDataKeyDefault
+ parameter flash_key_t RndCnstAddrKey = RndCnstAddrKeyDefault,
+ parameter flash_key_t RndCnstDataKey = RndCnstDataKeyDefault,
+ parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
+ parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault
) (
input clk_i,
input rst_ni,
@@ -40,7 +42,8 @@
output lc_flash_rsp_t lc_o,
input pwrmgr_pkg::pwr_flash_req_t pwrmgr_i,
output pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_o,
- input edn_entropy_t edn_i,
+ output edn_pkg::edn_req_t edn_o,
+ input edn_pkg::edn_rsp_t edn_i,
output keymgr_flash_t keymgr_o,
// Interrupts
@@ -231,16 +234,19 @@
);
prim_lfsr #(
- .EntropyDw(4),
+ .EntropyDw(EdnWidth),
.LfsrDw(LfsrWidth),
- .StateOutDw(LfsrWidth)
+ .StateOutDw(LfsrWidth),
+ .DefaultSeed(RndCnstLfsrSeed),
+ .StatePermEn(1),
+ .StatePerm(RndCnstLfsrPerm)
) u_lfsr (
.clk_i,
.rst_ni,
- .seed_en_i('0),
- .seed_i('0),
+ .seed_en_i(edn_i.edn_ack),
+ .seed_i(edn_i.edn_bus),
.lfsr_en_i(lfsr_en),
- .entropy_i(edn_i.valid ? edn_i.entropy : '0),
+ .entropy_i('0),
.state_o(rand_val)
);
@@ -309,10 +315,7 @@
.phase_o(phase),
// indication that sw has been selected
- .sel_o(if_sel),
-
- // enable lfsr
- .lfsr_en_o(lfsr_en)
+ .sel_o(if_sel)
);
assign op_start = muxed_ctrl.start.q;
@@ -368,9 +371,6 @@
.rma_token_o(lc_o.rma_ack_token),
.rma_rsp_o(lc_o.rma_ack),
- // random value
- .rand_i(rand_val),
-
// outgoing seeds
.seeds_o(keymgr_o.seeds),
.seed_err_o(), // TBD hook-up to Err code register
@@ -387,10 +387,19 @@
.addr_key_o(addr_key),
.data_key_o(data_key),
+ // entropy interface
+ .edn_req_o(edn_o.edn_req),
+ .edn_ack_i(edn_i.edn_ack),
+ .lfsr_en_o(lfsr_en),
+ .rand_i(rand_val),
+
// init ongoing
.init_busy_o(ctrl_init_busy)
);
+ logic unused_edn_fips;
+ assign unused_edn_fips = edn_i.edn_fips;
+
// Program FIFO
// Since the program and read FIFOs are never used at the same time, it should really be one
// FIFO with muxed inputs and outputs. This should be addressed once the flash integration
@@ -636,6 +645,9 @@
assign flash_part_sel = op_part;
assign flash_info_sel = op_info_sel;
+ // tie off hardware clear path
+ assign hw2reg.erase_suspend.d = 1'b0;
+
// Flash memory Properties
// Memory property is page based and thus should use phy addressing
// This should move to flash_phy long term
@@ -664,6 +676,8 @@
.prog_i(prog_op),
.pg_erase_i(erase_op & (erase_flash_type == FlashErasePage)),
.bk_erase_i(erase_op & (erase_flash_type == FlashEraseBank)),
+ .erase_suspend_i(reg2hw.erase_suspend),
+ .erase_suspend_done_o(hw2reg.erase_suspend.de),
.rd_done_o(flash_rd_done),
.prog_done_o(flash_prog_done),
.erase_done_o(flash_erase_done),
@@ -679,6 +693,8 @@
.prog_o(flash_o.prog),
.pg_erase_o(flash_o.pg_erase),
.bk_erase_o(flash_o.bk_erase),
+ .erase_suspend_o(flash_o.erase_suspend),
+ .erase_suspend_done_i(flash_i.erase_suspend_done),
.rd_done_i(flash_i.rd_done),
.prog_done_i(flash_i.prog_done),
.erase_done_i(flash_i.erase_done)
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
index f76d814..a6a31ac 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
@@ -76,10 +76,24 @@
// parameters for connected components
parameter int SeedWidth = 256;
parameter int KeyWidth = 128;
- parameter int LfsrWidth = 32;
-
+ parameter int EdnWidth = edn_pkg::ENDPOINT_BUS_WIDTH;
typedef logic [KeyWidth-1:0] flash_key_t;
+ // Default Lfsr configurations
+ // These LFSR parameters have been generated with
+ // $ hw/ip/prim/util/gen-lfsr-seed.py --width 32 --seed 1274809145 --prefix ""
+ parameter int LfsrWidth = 32;
+ typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+ typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+ parameter lfsr_seed_t RndCnstLfsrSeedDefault = 32'ha8cee782;
+ parameter lfsr_perm_t RndCnstLfsrPermDefault = {
+ 160'hd60bc7d86445da9347e0ccdd05b281df95238bb5
+ };
+
+ // These LFSR parameters have been generated with
+ // $ hw/ip/prim/util/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix ""
+
+
// lcmgr phase enum
typedef enum logic [1:0] {
PhaseSeed,
@@ -265,6 +279,7 @@
logic prog;
logic pg_erase;
logic bk_erase;
+ logic erase_suspend;
flash_part_e part;
logic [InfoTypesWidth-1:0] info_sel;
logic [BusAddrW-1:0] addr;
@@ -279,24 +294,25 @@
// default value of flash_req_t (for dangling ports)
parameter flash_req_t FLASH_REQ_DEFAULT = '{
- req: '0,
- scramble_en: '0,
- ecc_en: '0,
- he_en: '0,
- rd: '0,
- prog: '0,
- pg_erase: '0,
- bk_erase: '0,
- part: FlashPartData,
- info_sel: '0,
- addr: '0,
- prog_data: '0,
- prog_last: '0,
- prog_type: FlashProgNormal,
- region_cfgs: '0,
- addr_key: RndCnstAddrKeyDefault,
- data_key: RndCnstDataKeyDefault,
- rd_buf_en: 1'b0
+ req: '0,
+ scramble_en: '0,
+ ecc_en: '0,
+ he_en: '0,
+ rd: '0,
+ prog: '0,
+ pg_erase: '0,
+ bk_erase: '0,
+ erase_suspend: '0,
+ part: FlashPartData,
+ info_sel: '0,
+ addr: '0,
+ prog_data: '0,
+ prog_last: '0,
+ prog_type: FlashProgNormal,
+ region_cfgs: '0,
+ addr_key: RndCnstAddrKeyDefault,
+ data_key: RndCnstDataKeyDefault,
+ rd_buf_en: 1'b0
};
// memory to flash controller
@@ -308,17 +324,19 @@
logic rd_err;
logic [BusWidth-1:0] rd_data;
logic init_busy;
+ logic erase_suspend_done;
} flash_rsp_t;
// default value of flash_rsp_t (for dangling ports)
parameter flash_rsp_t FLASH_RSP_DEFAULT = '{
- prog_type_avail: '{default: '1},
- rd_done: 1'b0,
- prog_done: 1'b0,
- erase_done: 1'b0,
- rd_err: '0,
- rd_data: '0,
- init_busy: 1'b0
+ prog_type_avail: '{default: '1},
+ rd_done: 1'b0,
+ prog_done: 1'b0,
+ erase_done: 1'b0,
+ rd_err: '0,
+ rd_data: '0,
+ init_busy: 1'b0,
+ erase_suspend_done: 1'b1
};
////////////////////////////
@@ -350,22 +368,11 @@
}
};
- // place holder for interface to EDN, replace with real one later
- typedef struct packed {
- logic valid;
- logic [3:0] entropy;
- } edn_entropy_t;
-
parameter lc_flash_req_t LC_FLASH_REQ_DEFAULT = '{
rma_req: 1'b0,
rma_req_token: '0
};
- parameter edn_entropy_t EDN_ENTROPY_DEFAULT = '{
- valid: 1'b1,
- entropy: '0
- };
-
// dft_en jtag selection
typedef enum logic [2:0] {
FlashLcTckSel,
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
index b89a355..8636b46 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
@@ -128,6 +128,10 @@
} flash_ctrl_reg2hw_prog_type_en_reg_t;
typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_erase_suspend_reg_t;
+
+ typedef struct packed {
struct packed {
logic q;
} en;
@@ -335,6 +339,11 @@
} flash_ctrl_hw2reg_control_reg_t;
typedef struct packed {
+ logic d;
+ logic de;
+ } flash_ctrl_hw2reg_erase_suspend_reg_t;
+
+ typedef struct packed {
struct packed {
logic d;
logic de;
@@ -392,12 +401,13 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [447:442]
- flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [441:436]
- flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [435:424]
- flash_ctrl_reg2hw_control_reg_t control; // [423:405]
- flash_ctrl_reg2hw_addr_reg_t addr; // [404:373]
- flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en; // [372:371]
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [448:443]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [442:437]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [436:425]
+ flash_ctrl_reg2hw_control_reg_t control; // [424:406]
+ flash_ctrl_reg2hw_addr_reg_t addr; // [405:374]
+ flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en; // [373:372]
+ flash_ctrl_reg2hw_erase_suspend_reg_t erase_suspend; // [371:371]
flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [370:163]
flash_ctrl_reg2hw_default_region_reg_t default_region; // [162:157]
flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t [3:0] bank0_info0_page_cfg; // [156:129]
@@ -414,9 +424,10 @@
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- flash_ctrl_hw2reg_intr_state_reg_t intr_state; // [44:33]
- flash_ctrl_hw2reg_ctrl_regwen_reg_t ctrl_regwen; // [32:32]
- flash_ctrl_hw2reg_control_reg_t control; // [31:30]
+ flash_ctrl_hw2reg_intr_state_reg_t intr_state; // [46:35]
+ flash_ctrl_hw2reg_ctrl_regwen_reg_t ctrl_regwen; // [34:34]
+ flash_ctrl_hw2reg_control_reg_t control; // [33:32]
+ flash_ctrl_hw2reg_erase_suspend_reg_t erase_suspend; // [31:30]
flash_ctrl_hw2reg_op_status_reg_t op_status; // [29:26]
flash_ctrl_hw2reg_status_reg_t status; // [25:6]
flash_ctrl_hw2reg_phy_status_reg_t phy_status; // [5:0]
@@ -430,68 +441,69 @@
parameter logic [8:0] FLASH_CTRL_CONTROL_OFFSET = 9'h 10;
parameter logic [8:0] FLASH_CTRL_ADDR_OFFSET = 9'h 14;
parameter logic [8:0] FLASH_CTRL_PROG_TYPE_EN_OFFSET = 9'h 18;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET = 9'h 1c;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET = 9'h 20;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET = 9'h 24;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET = 9'h 28;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET = 9'h 2c;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET = 9'h 30;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET = 9'h 34;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET = 9'h 38;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_0_OFFSET = 9'h 3c;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_1_OFFSET = 9'h 40;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_2_OFFSET = 9'h 44;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_3_OFFSET = 9'h 48;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_4_OFFSET = 9'h 4c;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_5_OFFSET = 9'h 50;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_6_OFFSET = 9'h 54;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_7_OFFSET = 9'h 58;
- parameter logic [8:0] FLASH_CTRL_DEFAULT_REGION_OFFSET = 9'h 5c;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET = 9'h 60;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET = 9'h 64;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET = 9'h 68;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET = 9'h 6c;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET = 9'h 70;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET = 9'h 74;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET = 9'h 78;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET = 9'h 7c;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_0_OFFSET = 9'h 80;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_1_OFFSET = 9'h 84;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_2_OFFSET = 9'h 88;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_3_OFFSET = 9'h 8c;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0_OFFSET = 9'h 90;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1_OFFSET = 9'h 94;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2_OFFSET = 9'h 98;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3_OFFSET = 9'h 9c;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET = 9'h a0;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET = 9'h a4;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET = 9'h a8;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET = 9'h ac;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET = 9'h b0;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET = 9'h b4;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET = 9'h b8;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET = 9'h bc;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_0_OFFSET = 9'h c0;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_1_OFFSET = 9'h c4;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_2_OFFSET = 9'h c8;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_3_OFFSET = 9'h cc;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0_OFFSET = 9'h d0;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1_OFFSET = 9'h d4;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2_OFFSET = 9'h d8;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3_OFFSET = 9'h dc;
- parameter logic [8:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 9'h e0;
- parameter logic [8:0] FLASH_CTRL_MP_BANK_CFG_OFFSET = 9'h e4;
- parameter logic [8:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h e8;
- parameter logic [8:0] FLASH_CTRL_STATUS_OFFSET = 9'h ec;
- parameter logic [8:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h f0;
- parameter logic [8:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h f4;
- parameter logic [8:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h f8;
- parameter logic [8:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h fc;
+ parameter logic [8:0] FLASH_CTRL_ERASE_SUSPEND_OFFSET = 9'h 1c;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET = 9'h 20;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET = 9'h 24;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET = 9'h 28;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET = 9'h 2c;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET = 9'h 30;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET = 9'h 34;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET = 9'h 38;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET = 9'h 3c;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_0_OFFSET = 9'h 40;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_1_OFFSET = 9'h 44;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_2_OFFSET = 9'h 48;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_3_OFFSET = 9'h 4c;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_4_OFFSET = 9'h 50;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_5_OFFSET = 9'h 54;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_6_OFFSET = 9'h 58;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_7_OFFSET = 9'h 5c;
+ parameter logic [8:0] FLASH_CTRL_DEFAULT_REGION_OFFSET = 9'h 60;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET = 9'h 64;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET = 9'h 68;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET = 9'h 6c;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET = 9'h 70;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET = 9'h 74;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET = 9'h 78;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET = 9'h 7c;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET = 9'h 80;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_0_OFFSET = 9'h 84;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_1_OFFSET = 9'h 88;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_2_OFFSET = 9'h 8c;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_3_OFFSET = 9'h 90;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0_OFFSET = 9'h 94;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1_OFFSET = 9'h 98;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2_OFFSET = 9'h 9c;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3_OFFSET = 9'h a0;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET = 9'h a4;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET = 9'h a8;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET = 9'h ac;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET = 9'h b0;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET = 9'h b4;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET = 9'h b8;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET = 9'h bc;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET = 9'h c0;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_0_OFFSET = 9'h c4;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_1_OFFSET = 9'h c8;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_2_OFFSET = 9'h cc;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_3_OFFSET = 9'h d0;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0_OFFSET = 9'h d4;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1_OFFSET = 9'h d8;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2_OFFSET = 9'h dc;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3_OFFSET = 9'h e0;
+ parameter logic [8:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 9'h e4;
+ parameter logic [8:0] FLASH_CTRL_MP_BANK_CFG_OFFSET = 9'h e8;
+ parameter logic [8:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h ec;
+ parameter logic [8:0] FLASH_CTRL_STATUS_OFFSET = 9'h f0;
+ parameter logic [8:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h f4;
+ parameter logic [8:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h f8;
+ parameter logic [8:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h fc;
+ parameter logic [8:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h 100;
// Window parameter
- parameter logic [8:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 100;
+ parameter logic [8:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 104;
parameter logic [8:0] FLASH_CTRL_PROG_FIFO_SIZE = 9'h 4;
- parameter logic [8:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 104;
+ parameter logic [8:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 108;
parameter logic [8:0] FLASH_CTRL_RD_FIFO_SIZE = 9'h 4;
// Register Index
@@ -503,6 +515,7 @@
FLASH_CTRL_CONTROL,
FLASH_CTRL_ADDR,
FLASH_CTRL_PROG_TYPE_EN,
+ FLASH_CTRL_ERASE_SUSPEND,
FLASH_CTRL_REGION_CFG_REGWEN_0,
FLASH_CTRL_REGION_CFG_REGWEN_1,
FLASH_CTRL_REGION_CFG_REGWEN_2,
@@ -563,7 +576,7 @@
} flash_ctrl_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] FLASH_CTRL_PERMIT [64] = '{
+ parameter logic [3:0] FLASH_CTRL_PERMIT [65] = '{
4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE
4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST
@@ -571,63 +584,64 @@
4'b 1111, // index[ 4] FLASH_CTRL_CONTROL
4'b 1111, // index[ 5] FLASH_CTRL_ADDR
4'b 0001, // index[ 6] FLASH_CTRL_PROG_TYPE_EN
- 4'b 0001, // index[ 7] FLASH_CTRL_REGION_CFG_REGWEN_0
- 4'b 0001, // index[ 8] FLASH_CTRL_REGION_CFG_REGWEN_1
- 4'b 0001, // index[ 9] FLASH_CTRL_REGION_CFG_REGWEN_2
- 4'b 0001, // index[10] FLASH_CTRL_REGION_CFG_REGWEN_3
- 4'b 0001, // index[11] FLASH_CTRL_REGION_CFG_REGWEN_4
- 4'b 0001, // index[12] FLASH_CTRL_REGION_CFG_REGWEN_5
- 4'b 0001, // index[13] FLASH_CTRL_REGION_CFG_REGWEN_6
- 4'b 0001, // index[14] FLASH_CTRL_REGION_CFG_REGWEN_7
- 4'b 1111, // index[15] FLASH_CTRL_MP_REGION_CFG_0
- 4'b 1111, // index[16] FLASH_CTRL_MP_REGION_CFG_1
- 4'b 1111, // index[17] FLASH_CTRL_MP_REGION_CFG_2
- 4'b 1111, // index[18] FLASH_CTRL_MP_REGION_CFG_3
- 4'b 1111, // index[19] FLASH_CTRL_MP_REGION_CFG_4
- 4'b 1111, // index[20] FLASH_CTRL_MP_REGION_CFG_5
- 4'b 1111, // index[21] FLASH_CTRL_MP_REGION_CFG_6
- 4'b 1111, // index[22] FLASH_CTRL_MP_REGION_CFG_7
- 4'b 0001, // index[23] FLASH_CTRL_DEFAULT_REGION
- 4'b 0001, // index[24] FLASH_CTRL_BANK0_INFO0_REGWEN_0
- 4'b 0001, // index[25] FLASH_CTRL_BANK0_INFO0_REGWEN_1
- 4'b 0001, // index[26] FLASH_CTRL_BANK0_INFO0_REGWEN_2
- 4'b 0001, // index[27] FLASH_CTRL_BANK0_INFO0_REGWEN_3
- 4'b 0001, // index[28] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0
- 4'b 0001, // index[29] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1
- 4'b 0001, // index[30] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2
- 4'b 0001, // index[31] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3
- 4'b 0001, // index[32] FLASH_CTRL_BANK0_INFO1_REGWEN_0
- 4'b 0001, // index[33] FLASH_CTRL_BANK0_INFO1_REGWEN_1
- 4'b 0001, // index[34] FLASH_CTRL_BANK0_INFO1_REGWEN_2
- 4'b 0001, // index[35] FLASH_CTRL_BANK0_INFO1_REGWEN_3
- 4'b 0001, // index[36] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0
- 4'b 0001, // index[37] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1
- 4'b 0001, // index[38] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2
- 4'b 0001, // index[39] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3
- 4'b 0001, // index[40] FLASH_CTRL_BANK1_INFO0_REGWEN_0
- 4'b 0001, // index[41] FLASH_CTRL_BANK1_INFO0_REGWEN_1
- 4'b 0001, // index[42] FLASH_CTRL_BANK1_INFO0_REGWEN_2
- 4'b 0001, // index[43] FLASH_CTRL_BANK1_INFO0_REGWEN_3
- 4'b 0001, // index[44] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0
- 4'b 0001, // index[45] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1
- 4'b 0001, // index[46] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2
- 4'b 0001, // index[47] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3
- 4'b 0001, // index[48] FLASH_CTRL_BANK1_INFO1_REGWEN_0
- 4'b 0001, // index[49] FLASH_CTRL_BANK1_INFO1_REGWEN_1
- 4'b 0001, // index[50] FLASH_CTRL_BANK1_INFO1_REGWEN_2
- 4'b 0001, // index[51] FLASH_CTRL_BANK1_INFO1_REGWEN_3
- 4'b 0001, // index[52] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0
- 4'b 0001, // index[53] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1
- 4'b 0001, // index[54] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2
- 4'b 0001, // index[55] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3
- 4'b 0001, // index[56] FLASH_CTRL_BANK_CFG_REGWEN
- 4'b 0001, // index[57] FLASH_CTRL_MP_BANK_CFG
- 4'b 0001, // index[58] FLASH_CTRL_OP_STATUS
- 4'b 0111, // index[59] FLASH_CTRL_STATUS
- 4'b 0001, // index[60] FLASH_CTRL_PHY_STATUS
- 4'b 1111, // index[61] FLASH_CTRL_SCRATCH
- 4'b 0011, // index[62] FLASH_CTRL_FIFO_LVL
- 4'b 0001 // index[63] FLASH_CTRL_FIFO_RST
+ 4'b 0001, // index[ 7] FLASH_CTRL_ERASE_SUSPEND
+ 4'b 0001, // index[ 8] FLASH_CTRL_REGION_CFG_REGWEN_0
+ 4'b 0001, // index[ 9] FLASH_CTRL_REGION_CFG_REGWEN_1
+ 4'b 0001, // index[10] FLASH_CTRL_REGION_CFG_REGWEN_2
+ 4'b 0001, // index[11] FLASH_CTRL_REGION_CFG_REGWEN_3
+ 4'b 0001, // index[12] FLASH_CTRL_REGION_CFG_REGWEN_4
+ 4'b 0001, // index[13] FLASH_CTRL_REGION_CFG_REGWEN_5
+ 4'b 0001, // index[14] FLASH_CTRL_REGION_CFG_REGWEN_6
+ 4'b 0001, // index[15] FLASH_CTRL_REGION_CFG_REGWEN_7
+ 4'b 1111, // index[16] FLASH_CTRL_MP_REGION_CFG_0
+ 4'b 1111, // index[17] FLASH_CTRL_MP_REGION_CFG_1
+ 4'b 1111, // index[18] FLASH_CTRL_MP_REGION_CFG_2
+ 4'b 1111, // index[19] FLASH_CTRL_MP_REGION_CFG_3
+ 4'b 1111, // index[20] FLASH_CTRL_MP_REGION_CFG_4
+ 4'b 1111, // index[21] FLASH_CTRL_MP_REGION_CFG_5
+ 4'b 1111, // index[22] FLASH_CTRL_MP_REGION_CFG_6
+ 4'b 1111, // index[23] FLASH_CTRL_MP_REGION_CFG_7
+ 4'b 0001, // index[24] FLASH_CTRL_DEFAULT_REGION
+ 4'b 0001, // index[25] FLASH_CTRL_BANK0_INFO0_REGWEN_0
+ 4'b 0001, // index[26] FLASH_CTRL_BANK0_INFO0_REGWEN_1
+ 4'b 0001, // index[27] FLASH_CTRL_BANK0_INFO0_REGWEN_2
+ 4'b 0001, // index[28] FLASH_CTRL_BANK0_INFO0_REGWEN_3
+ 4'b 0001, // index[29] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0
+ 4'b 0001, // index[30] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1
+ 4'b 0001, // index[31] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2
+ 4'b 0001, // index[32] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3
+ 4'b 0001, // index[33] FLASH_CTRL_BANK0_INFO1_REGWEN_0
+ 4'b 0001, // index[34] FLASH_CTRL_BANK0_INFO1_REGWEN_1
+ 4'b 0001, // index[35] FLASH_CTRL_BANK0_INFO1_REGWEN_2
+ 4'b 0001, // index[36] FLASH_CTRL_BANK0_INFO1_REGWEN_3
+ 4'b 0001, // index[37] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0
+ 4'b 0001, // index[38] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1
+ 4'b 0001, // index[39] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2
+ 4'b 0001, // index[40] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3
+ 4'b 0001, // index[41] FLASH_CTRL_BANK1_INFO0_REGWEN_0
+ 4'b 0001, // index[42] FLASH_CTRL_BANK1_INFO0_REGWEN_1
+ 4'b 0001, // index[43] FLASH_CTRL_BANK1_INFO0_REGWEN_2
+ 4'b 0001, // index[44] FLASH_CTRL_BANK1_INFO0_REGWEN_3
+ 4'b 0001, // index[45] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0
+ 4'b 0001, // index[46] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1
+ 4'b 0001, // index[47] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2
+ 4'b 0001, // index[48] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3
+ 4'b 0001, // index[49] FLASH_CTRL_BANK1_INFO1_REGWEN_0
+ 4'b 0001, // index[50] FLASH_CTRL_BANK1_INFO1_REGWEN_1
+ 4'b 0001, // index[51] FLASH_CTRL_BANK1_INFO1_REGWEN_2
+ 4'b 0001, // index[52] FLASH_CTRL_BANK1_INFO1_REGWEN_3
+ 4'b 0001, // index[53] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0
+ 4'b 0001, // index[54] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1
+ 4'b 0001, // index[55] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2
+ 4'b 0001, // index[56] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3
+ 4'b 0001, // index[57] FLASH_CTRL_BANK_CFG_REGWEN
+ 4'b 0001, // index[58] FLASH_CTRL_MP_BANK_CFG
+ 4'b 0001, // index[59] FLASH_CTRL_OP_STATUS
+ 4'b 0111, // index[60] FLASH_CTRL_STATUS
+ 4'b 0001, // index[61] FLASH_CTRL_PHY_STATUS
+ 4'b 1111, // index[62] FLASH_CTRL_SCRATCH
+ 4'b 0011, // index[63] FLASH_CTRL_FIFO_LVL
+ 4'b 0001 // index[64] FLASH_CTRL_FIFO_RST
};
endpackage
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
index a45cd51..b9b23df 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
@@ -88,10 +88,10 @@
reg_steer = 2; // Default set to register
// TODO: Can below codes be unique case () inside ?
- if (tl_i.a_address[AW-1:0] >= 256 && tl_i.a_address[AW-1:0] < 260) begin
+ if (tl_i.a_address[AW-1:0] >= 260 && tl_i.a_address[AW-1:0] < 264) begin
reg_steer = 0;
end
- if (tl_i.a_address[AW-1:0] >= 260 && tl_i.a_address[AW-1:0] < 264) begin
+ if (tl_i.a_address[AW-1:0] >= 264 && tl_i.a_address[AW-1:0] < 268) begin
reg_steer = 1;
end
end
@@ -201,6 +201,9 @@
logic prog_type_en_repair_qs;
logic prog_type_en_repair_wd;
logic prog_type_en_repair_we;
+ logic erase_suspend_qs;
+ logic erase_suspend_wd;
+ logic erase_suspend_we;
logic region_cfg_regwen_0_qs;
logic region_cfg_regwen_0_wd;
logic region_cfg_regwen_0_we;
@@ -1570,6 +1573,33 @@
);
+ // R[erase_suspend]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_erase_suspend (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (erase_suspend_we),
+ .wd (erase_suspend_wd),
+
+ // from internal hardware
+ .de (hw2reg.erase_suspend.de),
+ .d (hw2reg.erase_suspend.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.erase_suspend.q ),
+
+ // to register interface (read)
+ .qs (erase_suspend_qs)
+ );
+
+
// Subregister 0 of Multireg region_cfg_regwen
// R[region_cfg_regwen_0]: V(False)
@@ -7729,7 +7759,7 @@
- logic [63:0] addr_hit;
+ logic [64:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
@@ -7739,63 +7769,64 @@
addr_hit[ 4] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET);
addr_hit[ 5] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
addr_hit[ 6] = (reg_addr == FLASH_CTRL_PROG_TYPE_EN_OFFSET);
- addr_hit[ 7] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET);
- addr_hit[ 8] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET);
- addr_hit[ 9] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET);
- addr_hit[10] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET);
- addr_hit[11] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET);
- addr_hit[12] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET);
- addr_hit[13] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET);
- addr_hit[14] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET);
- addr_hit[15] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_0_OFFSET);
- addr_hit[16] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_1_OFFSET);
- addr_hit[17] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_2_OFFSET);
- addr_hit[18] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_3_OFFSET);
- addr_hit[19] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_4_OFFSET);
- addr_hit[20] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_5_OFFSET);
- addr_hit[21] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_6_OFFSET);
- addr_hit[22] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_7_OFFSET);
- addr_hit[23] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
- addr_hit[24] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET);
- addr_hit[25] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET);
- addr_hit[26] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET);
- addr_hit[27] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET);
- addr_hit[28] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET);
- addr_hit[29] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET);
- addr_hit[30] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET);
- addr_hit[31] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET);
- addr_hit[32] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_0_OFFSET);
- addr_hit[33] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_1_OFFSET);
- addr_hit[34] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_2_OFFSET);
- addr_hit[35] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_3_OFFSET);
- addr_hit[36] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0_OFFSET);
- addr_hit[37] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1_OFFSET);
- addr_hit[38] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2_OFFSET);
- addr_hit[39] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3_OFFSET);
- addr_hit[40] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET);
- addr_hit[41] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET);
- addr_hit[42] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET);
- addr_hit[43] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET);
- addr_hit[44] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET);
- addr_hit[45] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET);
- addr_hit[46] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET);
- addr_hit[47] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET);
- addr_hit[48] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_0_OFFSET);
- addr_hit[49] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_1_OFFSET);
- addr_hit[50] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_2_OFFSET);
- addr_hit[51] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_3_OFFSET);
- addr_hit[52] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0_OFFSET);
- addr_hit[53] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1_OFFSET);
- addr_hit[54] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2_OFFSET);
- addr_hit[55] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3_OFFSET);
- addr_hit[56] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET);
- addr_hit[57] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET);
- addr_hit[58] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
- addr_hit[59] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
- addr_hit[60] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
- addr_hit[61] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
- addr_hit[62] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
- addr_hit[63] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
+ addr_hit[ 7] = (reg_addr == FLASH_CTRL_ERASE_SUSPEND_OFFSET);
+ addr_hit[ 8] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET);
+ addr_hit[ 9] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET);
+ addr_hit[10] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET);
+ addr_hit[11] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET);
+ addr_hit[12] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET);
+ addr_hit[13] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET);
+ addr_hit[14] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET);
+ addr_hit[15] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET);
+ addr_hit[16] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_0_OFFSET);
+ addr_hit[17] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_1_OFFSET);
+ addr_hit[18] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_2_OFFSET);
+ addr_hit[19] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_3_OFFSET);
+ addr_hit[20] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_4_OFFSET);
+ addr_hit[21] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_5_OFFSET);
+ addr_hit[22] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_6_OFFSET);
+ addr_hit[23] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_7_OFFSET);
+ addr_hit[24] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
+ addr_hit[25] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET);
+ addr_hit[26] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET);
+ addr_hit[27] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET);
+ addr_hit[28] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET);
+ addr_hit[29] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET);
+ addr_hit[30] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET);
+ addr_hit[31] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET);
+ addr_hit[32] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET);
+ addr_hit[33] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_0_OFFSET);
+ addr_hit[34] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_1_OFFSET);
+ addr_hit[35] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_2_OFFSET);
+ addr_hit[36] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_3_OFFSET);
+ addr_hit[37] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0_OFFSET);
+ addr_hit[38] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1_OFFSET);
+ addr_hit[39] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2_OFFSET);
+ addr_hit[40] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3_OFFSET);
+ addr_hit[41] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET);
+ addr_hit[42] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET);
+ addr_hit[43] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET);
+ addr_hit[44] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET);
+ addr_hit[45] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET);
+ addr_hit[46] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET);
+ addr_hit[47] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET);
+ addr_hit[48] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET);
+ addr_hit[49] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_0_OFFSET);
+ addr_hit[50] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_1_OFFSET);
+ addr_hit[51] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_2_OFFSET);
+ addr_hit[52] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_3_OFFSET);
+ addr_hit[53] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0_OFFSET);
+ addr_hit[54] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1_OFFSET);
+ addr_hit[55] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2_OFFSET);
+ addr_hit[56] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3_OFFSET);
+ addr_hit[57] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET);
+ addr_hit[58] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET);
+ addr_hit[59] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
+ addr_hit[60] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
+ addr_hit[61] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
+ addr_hit[62] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
+ addr_hit[63] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
+ addr_hit[64] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -7867,6 +7898,7 @@
if (addr_hit[61] && reg_we && (FLASH_CTRL_PERMIT[61] != (FLASH_CTRL_PERMIT[61] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[62] && reg_we && (FLASH_CTRL_PERMIT[62] != (FLASH_CTRL_PERMIT[62] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[63] && reg_we && (FLASH_CTRL_PERMIT[63] != (FLASH_CTRL_PERMIT[63] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[64] && reg_we && (FLASH_CTRL_PERMIT[64] != (FLASH_CTRL_PERMIT[64] & reg_be))) wr_err = 1'b1 ;
end
assign intr_state_prog_empty_we = addr_hit[0] & reg_we & ~wr_err;
@@ -7955,661 +7987,664 @@
assign prog_type_en_repair_we = addr_hit[6] & reg_we & ~wr_err;
assign prog_type_en_repair_wd = reg_wdata[1];
- assign region_cfg_regwen_0_we = addr_hit[7] & reg_we & ~wr_err;
+ assign erase_suspend_we = addr_hit[7] & reg_we & ~wr_err;
+ assign erase_suspend_wd = reg_wdata[0];
+
+ assign region_cfg_regwen_0_we = addr_hit[8] & reg_we & ~wr_err;
assign region_cfg_regwen_0_wd = reg_wdata[0];
- assign region_cfg_regwen_1_we = addr_hit[8] & reg_we & ~wr_err;
+ assign region_cfg_regwen_1_we = addr_hit[9] & reg_we & ~wr_err;
assign region_cfg_regwen_1_wd = reg_wdata[0];
- assign region_cfg_regwen_2_we = addr_hit[9] & reg_we & ~wr_err;
+ assign region_cfg_regwen_2_we = addr_hit[10] & reg_we & ~wr_err;
assign region_cfg_regwen_2_wd = reg_wdata[0];
- assign region_cfg_regwen_3_we = addr_hit[10] & reg_we & ~wr_err;
+ assign region_cfg_regwen_3_we = addr_hit[11] & reg_we & ~wr_err;
assign region_cfg_regwen_3_wd = reg_wdata[0];
- assign region_cfg_regwen_4_we = addr_hit[11] & reg_we & ~wr_err;
+ assign region_cfg_regwen_4_we = addr_hit[12] & reg_we & ~wr_err;
assign region_cfg_regwen_4_wd = reg_wdata[0];
- assign region_cfg_regwen_5_we = addr_hit[12] & reg_we & ~wr_err;
+ assign region_cfg_regwen_5_we = addr_hit[13] & reg_we & ~wr_err;
assign region_cfg_regwen_5_wd = reg_wdata[0];
- assign region_cfg_regwen_6_we = addr_hit[13] & reg_we & ~wr_err;
+ assign region_cfg_regwen_6_we = addr_hit[14] & reg_we & ~wr_err;
assign region_cfg_regwen_6_wd = reg_wdata[0];
- assign region_cfg_regwen_7_we = addr_hit[14] & reg_we & ~wr_err;
+ assign region_cfg_regwen_7_we = addr_hit[15] & reg_we & ~wr_err;
assign region_cfg_regwen_7_wd = reg_wdata[0];
- assign mp_region_cfg_0_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_en_0_wd = reg_wdata[0];
- assign mp_region_cfg_0_rd_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_rd_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_rd_en_0_wd = reg_wdata[1];
- assign mp_region_cfg_0_prog_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_prog_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_prog_en_0_wd = reg_wdata[2];
- assign mp_region_cfg_0_erase_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_erase_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_erase_en_0_wd = reg_wdata[3];
- assign mp_region_cfg_0_scramble_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_scramble_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_scramble_en_0_wd = reg_wdata[4];
- assign mp_region_cfg_0_ecc_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_ecc_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_ecc_en_0_wd = reg_wdata[5];
- assign mp_region_cfg_0_he_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_he_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_he_en_0_wd = reg_wdata[6];
- assign mp_region_cfg_0_base_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_base_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_base_0_wd = reg_wdata[16:8];
- assign mp_region_cfg_0_size_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_size_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_size_0_wd = reg_wdata[29:20];
- assign mp_region_cfg_1_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_en_1_wd = reg_wdata[0];
- assign mp_region_cfg_1_rd_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_rd_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_rd_en_1_wd = reg_wdata[1];
- assign mp_region_cfg_1_prog_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_prog_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_prog_en_1_wd = reg_wdata[2];
- assign mp_region_cfg_1_erase_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_erase_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_erase_en_1_wd = reg_wdata[3];
- assign mp_region_cfg_1_scramble_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_scramble_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_scramble_en_1_wd = reg_wdata[4];
- assign mp_region_cfg_1_ecc_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_ecc_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_ecc_en_1_wd = reg_wdata[5];
- assign mp_region_cfg_1_he_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_he_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_he_en_1_wd = reg_wdata[6];
- assign mp_region_cfg_1_base_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_base_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_base_1_wd = reg_wdata[16:8];
- assign mp_region_cfg_1_size_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_size_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_size_1_wd = reg_wdata[29:20];
- assign mp_region_cfg_2_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_en_2_wd = reg_wdata[0];
- assign mp_region_cfg_2_rd_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_rd_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_rd_en_2_wd = reg_wdata[1];
- assign mp_region_cfg_2_prog_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_prog_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_prog_en_2_wd = reg_wdata[2];
- assign mp_region_cfg_2_erase_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_erase_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_erase_en_2_wd = reg_wdata[3];
- assign mp_region_cfg_2_scramble_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_scramble_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_scramble_en_2_wd = reg_wdata[4];
- assign mp_region_cfg_2_ecc_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_ecc_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_ecc_en_2_wd = reg_wdata[5];
- assign mp_region_cfg_2_he_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_he_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_he_en_2_wd = reg_wdata[6];
- assign mp_region_cfg_2_base_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_base_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_base_2_wd = reg_wdata[16:8];
- assign mp_region_cfg_2_size_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_size_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_size_2_wd = reg_wdata[29:20];
- assign mp_region_cfg_3_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_en_3_wd = reg_wdata[0];
- assign mp_region_cfg_3_rd_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_rd_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_rd_en_3_wd = reg_wdata[1];
- assign mp_region_cfg_3_prog_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_prog_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_prog_en_3_wd = reg_wdata[2];
- assign mp_region_cfg_3_erase_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_erase_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_erase_en_3_wd = reg_wdata[3];
- assign mp_region_cfg_3_scramble_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_scramble_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_scramble_en_3_wd = reg_wdata[4];
- assign mp_region_cfg_3_ecc_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_ecc_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_ecc_en_3_wd = reg_wdata[5];
- assign mp_region_cfg_3_he_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_he_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_he_en_3_wd = reg_wdata[6];
- assign mp_region_cfg_3_base_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_base_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_base_3_wd = reg_wdata[16:8];
- assign mp_region_cfg_3_size_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_size_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_size_3_wd = reg_wdata[29:20];
- assign mp_region_cfg_4_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_en_4_wd = reg_wdata[0];
- assign mp_region_cfg_4_rd_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_rd_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_rd_en_4_wd = reg_wdata[1];
- assign mp_region_cfg_4_prog_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_prog_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_prog_en_4_wd = reg_wdata[2];
- assign mp_region_cfg_4_erase_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_erase_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_erase_en_4_wd = reg_wdata[3];
- assign mp_region_cfg_4_scramble_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_scramble_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_scramble_en_4_wd = reg_wdata[4];
- assign mp_region_cfg_4_ecc_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_ecc_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_ecc_en_4_wd = reg_wdata[5];
- assign mp_region_cfg_4_he_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_he_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_he_en_4_wd = reg_wdata[6];
- assign mp_region_cfg_4_base_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_base_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_base_4_wd = reg_wdata[16:8];
- assign mp_region_cfg_4_size_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_size_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_size_4_wd = reg_wdata[29:20];
- assign mp_region_cfg_5_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_en_5_wd = reg_wdata[0];
- assign mp_region_cfg_5_rd_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_rd_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_rd_en_5_wd = reg_wdata[1];
- assign mp_region_cfg_5_prog_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_prog_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_prog_en_5_wd = reg_wdata[2];
- assign mp_region_cfg_5_erase_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_erase_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_erase_en_5_wd = reg_wdata[3];
- assign mp_region_cfg_5_scramble_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_scramble_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_scramble_en_5_wd = reg_wdata[4];
- assign mp_region_cfg_5_ecc_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_ecc_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_ecc_en_5_wd = reg_wdata[5];
- assign mp_region_cfg_5_he_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_he_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_he_en_5_wd = reg_wdata[6];
- assign mp_region_cfg_5_base_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_base_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_base_5_wd = reg_wdata[16:8];
- assign mp_region_cfg_5_size_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_size_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_size_5_wd = reg_wdata[29:20];
- assign mp_region_cfg_6_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_en_6_wd = reg_wdata[0];
- assign mp_region_cfg_6_rd_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_rd_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_rd_en_6_wd = reg_wdata[1];
- assign mp_region_cfg_6_prog_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_prog_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_prog_en_6_wd = reg_wdata[2];
- assign mp_region_cfg_6_erase_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_erase_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_erase_en_6_wd = reg_wdata[3];
- assign mp_region_cfg_6_scramble_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_scramble_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_scramble_en_6_wd = reg_wdata[4];
- assign mp_region_cfg_6_ecc_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_ecc_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_ecc_en_6_wd = reg_wdata[5];
- assign mp_region_cfg_6_he_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_he_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_he_en_6_wd = reg_wdata[6];
- assign mp_region_cfg_6_base_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_base_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_base_6_wd = reg_wdata[16:8];
- assign mp_region_cfg_6_size_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_size_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_size_6_wd = reg_wdata[29:20];
- assign mp_region_cfg_7_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_en_7_wd = reg_wdata[0];
- assign mp_region_cfg_7_rd_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_rd_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_rd_en_7_wd = reg_wdata[1];
- assign mp_region_cfg_7_prog_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_prog_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_prog_en_7_wd = reg_wdata[2];
- assign mp_region_cfg_7_erase_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_erase_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_erase_en_7_wd = reg_wdata[3];
- assign mp_region_cfg_7_scramble_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_scramble_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_scramble_en_7_wd = reg_wdata[4];
- assign mp_region_cfg_7_ecc_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_ecc_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_ecc_en_7_wd = reg_wdata[5];
- assign mp_region_cfg_7_he_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_he_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_he_en_7_wd = reg_wdata[6];
- assign mp_region_cfg_7_base_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_base_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_base_7_wd = reg_wdata[16:8];
- assign mp_region_cfg_7_size_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_size_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_size_7_wd = reg_wdata[29:20];
- assign default_region_rd_en_we = addr_hit[23] & reg_we & ~wr_err;
+ assign default_region_rd_en_we = addr_hit[24] & reg_we & ~wr_err;
assign default_region_rd_en_wd = reg_wdata[0];
- assign default_region_prog_en_we = addr_hit[23] & reg_we & ~wr_err;
+ assign default_region_prog_en_we = addr_hit[24] & reg_we & ~wr_err;
assign default_region_prog_en_wd = reg_wdata[1];
- assign default_region_erase_en_we = addr_hit[23] & reg_we & ~wr_err;
+ assign default_region_erase_en_we = addr_hit[24] & reg_we & ~wr_err;
assign default_region_erase_en_wd = reg_wdata[2];
- assign default_region_scramble_en_we = addr_hit[23] & reg_we & ~wr_err;
+ assign default_region_scramble_en_we = addr_hit[24] & reg_we & ~wr_err;
assign default_region_scramble_en_wd = reg_wdata[3];
- assign default_region_ecc_en_we = addr_hit[23] & reg_we & ~wr_err;
+ assign default_region_ecc_en_we = addr_hit[24] & reg_we & ~wr_err;
assign default_region_ecc_en_wd = reg_wdata[4];
- assign default_region_he_en_we = addr_hit[23] & reg_we & ~wr_err;
+ assign default_region_he_en_we = addr_hit[24] & reg_we & ~wr_err;
assign default_region_he_en_wd = reg_wdata[5];
- assign bank0_info0_regwen_0_we = addr_hit[24] & reg_we & ~wr_err;
+ assign bank0_info0_regwen_0_we = addr_hit[25] & reg_we & ~wr_err;
assign bank0_info0_regwen_0_wd = reg_wdata[0];
- assign bank0_info0_regwen_1_we = addr_hit[25] & reg_we & ~wr_err;
+ assign bank0_info0_regwen_1_we = addr_hit[26] & reg_we & ~wr_err;
assign bank0_info0_regwen_1_wd = reg_wdata[0];
- assign bank0_info0_regwen_2_we = addr_hit[26] & reg_we & ~wr_err;
+ assign bank0_info0_regwen_2_we = addr_hit[27] & reg_we & ~wr_err;
assign bank0_info0_regwen_2_wd = reg_wdata[0];
- assign bank0_info0_regwen_3_we = addr_hit[27] & reg_we & ~wr_err;
+ assign bank0_info0_regwen_3_we = addr_hit[28] & reg_we & ~wr_err;
assign bank0_info0_regwen_3_wd = reg_wdata[0];
- assign bank0_info0_page_cfg_0_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_en_0_wd = reg_wdata[0];
- assign bank0_info0_page_cfg_0_rd_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_rd_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_rd_en_0_wd = reg_wdata[1];
- assign bank0_info0_page_cfg_0_prog_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_prog_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_prog_en_0_wd = reg_wdata[2];
- assign bank0_info0_page_cfg_0_erase_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_erase_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_erase_en_0_wd = reg_wdata[3];
- assign bank0_info0_page_cfg_0_scramble_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_scramble_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
- assign bank0_info0_page_cfg_0_ecc_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_ecc_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
- assign bank0_info0_page_cfg_0_he_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_he_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_he_en_0_wd = reg_wdata[6];
- assign bank0_info0_page_cfg_1_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_en_1_wd = reg_wdata[0];
- assign bank0_info0_page_cfg_1_rd_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_rd_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_rd_en_1_wd = reg_wdata[1];
- assign bank0_info0_page_cfg_1_prog_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_prog_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_prog_en_1_wd = reg_wdata[2];
- assign bank0_info0_page_cfg_1_erase_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_erase_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_erase_en_1_wd = reg_wdata[3];
- assign bank0_info0_page_cfg_1_scramble_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_scramble_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
- assign bank0_info0_page_cfg_1_ecc_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_ecc_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
- assign bank0_info0_page_cfg_1_he_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_he_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_he_en_1_wd = reg_wdata[6];
- assign bank0_info0_page_cfg_2_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_en_2_wd = reg_wdata[0];
- assign bank0_info0_page_cfg_2_rd_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_rd_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_rd_en_2_wd = reg_wdata[1];
- assign bank0_info0_page_cfg_2_prog_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_prog_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_prog_en_2_wd = reg_wdata[2];
- assign bank0_info0_page_cfg_2_erase_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_erase_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_erase_en_2_wd = reg_wdata[3];
- assign bank0_info0_page_cfg_2_scramble_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_scramble_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
- assign bank0_info0_page_cfg_2_ecc_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_ecc_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
- assign bank0_info0_page_cfg_2_he_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_he_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_he_en_2_wd = reg_wdata[6];
- assign bank0_info0_page_cfg_3_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_en_3_wd = reg_wdata[0];
- assign bank0_info0_page_cfg_3_rd_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_rd_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_rd_en_3_wd = reg_wdata[1];
- assign bank0_info0_page_cfg_3_prog_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_prog_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_prog_en_3_wd = reg_wdata[2];
- assign bank0_info0_page_cfg_3_erase_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_erase_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_erase_en_3_wd = reg_wdata[3];
- assign bank0_info0_page_cfg_3_scramble_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_scramble_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
- assign bank0_info0_page_cfg_3_ecc_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_ecc_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
- assign bank0_info0_page_cfg_3_he_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_he_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_he_en_3_wd = reg_wdata[6];
- assign bank0_info1_regwen_0_we = addr_hit[32] & reg_we & ~wr_err;
+ assign bank0_info1_regwen_0_we = addr_hit[33] & reg_we & ~wr_err;
assign bank0_info1_regwen_0_wd = reg_wdata[0];
- assign bank0_info1_regwen_1_we = addr_hit[33] & reg_we & ~wr_err;
+ assign bank0_info1_regwen_1_we = addr_hit[34] & reg_we & ~wr_err;
assign bank0_info1_regwen_1_wd = reg_wdata[0];
- assign bank0_info1_regwen_2_we = addr_hit[34] & reg_we & ~wr_err;
+ assign bank0_info1_regwen_2_we = addr_hit[35] & reg_we & ~wr_err;
assign bank0_info1_regwen_2_wd = reg_wdata[0];
- assign bank0_info1_regwen_3_we = addr_hit[35] & reg_we & ~wr_err;
+ assign bank0_info1_regwen_3_we = addr_hit[36] & reg_we & ~wr_err;
assign bank0_info1_regwen_3_wd = reg_wdata[0];
- assign bank0_info1_page_cfg_0_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_en_0_wd = reg_wdata[0];
- assign bank0_info1_page_cfg_0_rd_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_rd_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_rd_en_0_wd = reg_wdata[1];
- assign bank0_info1_page_cfg_0_prog_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_prog_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_prog_en_0_wd = reg_wdata[2];
- assign bank0_info1_page_cfg_0_erase_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_erase_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_erase_en_0_wd = reg_wdata[3];
- assign bank0_info1_page_cfg_0_scramble_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_scramble_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
- assign bank0_info1_page_cfg_0_ecc_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_ecc_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
- assign bank0_info1_page_cfg_0_he_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_he_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_he_en_0_wd = reg_wdata[6];
- assign bank0_info1_page_cfg_1_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_en_1_wd = reg_wdata[0];
- assign bank0_info1_page_cfg_1_rd_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_rd_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_rd_en_1_wd = reg_wdata[1];
- assign bank0_info1_page_cfg_1_prog_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_prog_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_prog_en_1_wd = reg_wdata[2];
- assign bank0_info1_page_cfg_1_erase_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_erase_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_erase_en_1_wd = reg_wdata[3];
- assign bank0_info1_page_cfg_1_scramble_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_scramble_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
- assign bank0_info1_page_cfg_1_ecc_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_ecc_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
- assign bank0_info1_page_cfg_1_he_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_he_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_he_en_1_wd = reg_wdata[6];
- assign bank0_info1_page_cfg_2_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_en_2_wd = reg_wdata[0];
- assign bank0_info1_page_cfg_2_rd_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_rd_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_rd_en_2_wd = reg_wdata[1];
- assign bank0_info1_page_cfg_2_prog_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_prog_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_prog_en_2_wd = reg_wdata[2];
- assign bank0_info1_page_cfg_2_erase_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_erase_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_erase_en_2_wd = reg_wdata[3];
- assign bank0_info1_page_cfg_2_scramble_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_scramble_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
- assign bank0_info1_page_cfg_2_ecc_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_ecc_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
- assign bank0_info1_page_cfg_2_he_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_he_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_he_en_2_wd = reg_wdata[6];
- assign bank0_info1_page_cfg_3_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_en_3_wd = reg_wdata[0];
- assign bank0_info1_page_cfg_3_rd_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_rd_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_rd_en_3_wd = reg_wdata[1];
- assign bank0_info1_page_cfg_3_prog_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_prog_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_prog_en_3_wd = reg_wdata[2];
- assign bank0_info1_page_cfg_3_erase_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_erase_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_erase_en_3_wd = reg_wdata[3];
- assign bank0_info1_page_cfg_3_scramble_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_scramble_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
- assign bank0_info1_page_cfg_3_ecc_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_ecc_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
- assign bank0_info1_page_cfg_3_he_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_he_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_he_en_3_wd = reg_wdata[6];
- assign bank1_info0_regwen_0_we = addr_hit[40] & reg_we & ~wr_err;
+ assign bank1_info0_regwen_0_we = addr_hit[41] & reg_we & ~wr_err;
assign bank1_info0_regwen_0_wd = reg_wdata[0];
- assign bank1_info0_regwen_1_we = addr_hit[41] & reg_we & ~wr_err;
+ assign bank1_info0_regwen_1_we = addr_hit[42] & reg_we & ~wr_err;
assign bank1_info0_regwen_1_wd = reg_wdata[0];
- assign bank1_info0_regwen_2_we = addr_hit[42] & reg_we & ~wr_err;
+ assign bank1_info0_regwen_2_we = addr_hit[43] & reg_we & ~wr_err;
assign bank1_info0_regwen_2_wd = reg_wdata[0];
- assign bank1_info0_regwen_3_we = addr_hit[43] & reg_we & ~wr_err;
+ assign bank1_info0_regwen_3_we = addr_hit[44] & reg_we & ~wr_err;
assign bank1_info0_regwen_3_wd = reg_wdata[0];
- assign bank1_info0_page_cfg_0_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_en_0_wd = reg_wdata[0];
- assign bank1_info0_page_cfg_0_rd_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_rd_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_rd_en_0_wd = reg_wdata[1];
- assign bank1_info0_page_cfg_0_prog_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_prog_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_prog_en_0_wd = reg_wdata[2];
- assign bank1_info0_page_cfg_0_erase_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_erase_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_erase_en_0_wd = reg_wdata[3];
- assign bank1_info0_page_cfg_0_scramble_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_scramble_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
- assign bank1_info0_page_cfg_0_ecc_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_ecc_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
- assign bank1_info0_page_cfg_0_he_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_he_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_he_en_0_wd = reg_wdata[6];
- assign bank1_info0_page_cfg_1_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_en_1_wd = reg_wdata[0];
- assign bank1_info0_page_cfg_1_rd_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_rd_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_rd_en_1_wd = reg_wdata[1];
- assign bank1_info0_page_cfg_1_prog_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_prog_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_prog_en_1_wd = reg_wdata[2];
- assign bank1_info0_page_cfg_1_erase_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_erase_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_erase_en_1_wd = reg_wdata[3];
- assign bank1_info0_page_cfg_1_scramble_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_scramble_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
- assign bank1_info0_page_cfg_1_ecc_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_ecc_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
- assign bank1_info0_page_cfg_1_he_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_he_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_he_en_1_wd = reg_wdata[6];
- assign bank1_info0_page_cfg_2_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_en_2_wd = reg_wdata[0];
- assign bank1_info0_page_cfg_2_rd_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_rd_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_rd_en_2_wd = reg_wdata[1];
- assign bank1_info0_page_cfg_2_prog_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_prog_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_prog_en_2_wd = reg_wdata[2];
- assign bank1_info0_page_cfg_2_erase_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_erase_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_erase_en_2_wd = reg_wdata[3];
- assign bank1_info0_page_cfg_2_scramble_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_scramble_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
- assign bank1_info0_page_cfg_2_ecc_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_ecc_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
- assign bank1_info0_page_cfg_2_he_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_he_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_he_en_2_wd = reg_wdata[6];
- assign bank1_info0_page_cfg_3_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_en_3_wd = reg_wdata[0];
- assign bank1_info0_page_cfg_3_rd_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_rd_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_rd_en_3_wd = reg_wdata[1];
- assign bank1_info0_page_cfg_3_prog_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_prog_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_prog_en_3_wd = reg_wdata[2];
- assign bank1_info0_page_cfg_3_erase_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_erase_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_erase_en_3_wd = reg_wdata[3];
- assign bank1_info0_page_cfg_3_scramble_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_scramble_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
- assign bank1_info0_page_cfg_3_ecc_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_ecc_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
- assign bank1_info0_page_cfg_3_he_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_he_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_he_en_3_wd = reg_wdata[6];
- assign bank1_info1_regwen_0_we = addr_hit[48] & reg_we & ~wr_err;
+ assign bank1_info1_regwen_0_we = addr_hit[49] & reg_we & ~wr_err;
assign bank1_info1_regwen_0_wd = reg_wdata[0];
- assign bank1_info1_regwen_1_we = addr_hit[49] & reg_we & ~wr_err;
+ assign bank1_info1_regwen_1_we = addr_hit[50] & reg_we & ~wr_err;
assign bank1_info1_regwen_1_wd = reg_wdata[0];
- assign bank1_info1_regwen_2_we = addr_hit[50] & reg_we & ~wr_err;
+ assign bank1_info1_regwen_2_we = addr_hit[51] & reg_we & ~wr_err;
assign bank1_info1_regwen_2_wd = reg_wdata[0];
- assign bank1_info1_regwen_3_we = addr_hit[51] & reg_we & ~wr_err;
+ assign bank1_info1_regwen_3_we = addr_hit[52] & reg_we & ~wr_err;
assign bank1_info1_regwen_3_wd = reg_wdata[0];
- assign bank1_info1_page_cfg_0_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_en_0_wd = reg_wdata[0];
- assign bank1_info1_page_cfg_0_rd_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_rd_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_rd_en_0_wd = reg_wdata[1];
- assign bank1_info1_page_cfg_0_prog_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_prog_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_prog_en_0_wd = reg_wdata[2];
- assign bank1_info1_page_cfg_0_erase_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_erase_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_erase_en_0_wd = reg_wdata[3];
- assign bank1_info1_page_cfg_0_scramble_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_scramble_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
- assign bank1_info1_page_cfg_0_ecc_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_ecc_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
- assign bank1_info1_page_cfg_0_he_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_he_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_he_en_0_wd = reg_wdata[6];
- assign bank1_info1_page_cfg_1_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_en_1_wd = reg_wdata[0];
- assign bank1_info1_page_cfg_1_rd_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_rd_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_rd_en_1_wd = reg_wdata[1];
- assign bank1_info1_page_cfg_1_prog_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_prog_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_prog_en_1_wd = reg_wdata[2];
- assign bank1_info1_page_cfg_1_erase_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_erase_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_erase_en_1_wd = reg_wdata[3];
- assign bank1_info1_page_cfg_1_scramble_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_scramble_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
- assign bank1_info1_page_cfg_1_ecc_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_ecc_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
- assign bank1_info1_page_cfg_1_he_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_he_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_he_en_1_wd = reg_wdata[6];
- assign bank1_info1_page_cfg_2_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_en_2_wd = reg_wdata[0];
- assign bank1_info1_page_cfg_2_rd_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_rd_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_rd_en_2_wd = reg_wdata[1];
- assign bank1_info1_page_cfg_2_prog_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_prog_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_prog_en_2_wd = reg_wdata[2];
- assign bank1_info1_page_cfg_2_erase_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_erase_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_erase_en_2_wd = reg_wdata[3];
- assign bank1_info1_page_cfg_2_scramble_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_scramble_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
- assign bank1_info1_page_cfg_2_ecc_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_ecc_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
- assign bank1_info1_page_cfg_2_he_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_he_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_he_en_2_wd = reg_wdata[6];
- assign bank1_info1_page_cfg_3_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_en_3_wd = reg_wdata[0];
- assign bank1_info1_page_cfg_3_rd_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_rd_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_rd_en_3_wd = reg_wdata[1];
- assign bank1_info1_page_cfg_3_prog_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_prog_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_prog_en_3_wd = reg_wdata[2];
- assign bank1_info1_page_cfg_3_erase_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_erase_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_erase_en_3_wd = reg_wdata[3];
- assign bank1_info1_page_cfg_3_scramble_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_scramble_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
- assign bank1_info1_page_cfg_3_ecc_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_ecc_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
- assign bank1_info1_page_cfg_3_he_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_he_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_he_en_3_wd = reg_wdata[6];
- assign bank_cfg_regwen_we = addr_hit[56] & reg_we & ~wr_err;
+ assign bank_cfg_regwen_we = addr_hit[57] & reg_we & ~wr_err;
assign bank_cfg_regwen_wd = reg_wdata[0];
- assign mp_bank_cfg_erase_en_0_we = addr_hit[57] & reg_we & ~wr_err;
+ assign mp_bank_cfg_erase_en_0_we = addr_hit[58] & reg_we & ~wr_err;
assign mp_bank_cfg_erase_en_0_wd = reg_wdata[0];
- assign mp_bank_cfg_erase_en_1_we = addr_hit[57] & reg_we & ~wr_err;
+ assign mp_bank_cfg_erase_en_1_we = addr_hit[58] & reg_we & ~wr_err;
assign mp_bank_cfg_erase_en_1_wd = reg_wdata[1];
- assign op_status_done_we = addr_hit[58] & reg_we & ~wr_err;
+ assign op_status_done_we = addr_hit[59] & reg_we & ~wr_err;
assign op_status_done_wd = reg_wdata[0];
- assign op_status_err_we = addr_hit[58] & reg_we & ~wr_err;
+ assign op_status_err_we = addr_hit[59] & reg_we & ~wr_err;
assign op_status_err_wd = reg_wdata[1];
@@ -8621,16 +8656,16 @@
- assign scratch_we = addr_hit[61] & reg_we & ~wr_err;
+ assign scratch_we = addr_hit[62] & reg_we & ~wr_err;
assign scratch_wd = reg_wdata[31:0];
- assign fifo_lvl_prog_we = addr_hit[62] & reg_we & ~wr_err;
+ assign fifo_lvl_prog_we = addr_hit[63] & reg_we & ~wr_err;
assign fifo_lvl_prog_wd = reg_wdata[4:0];
- assign fifo_lvl_rd_we = addr_hit[62] & reg_we & ~wr_err;
+ assign fifo_lvl_rd_we = addr_hit[63] & reg_we & ~wr_err;
assign fifo_lvl_rd_wd = reg_wdata[12:8];
- assign fifo_rst_we = addr_hit[63] & reg_we & ~wr_err;
+ assign fifo_rst_we = addr_hit[64] & reg_we & ~wr_err;
assign fifo_rst_wd = reg_wdata[0];
// Read data return
@@ -8688,38 +8723,42 @@
end
addr_hit[7]: begin
- reg_rdata_next[0] = region_cfg_regwen_0_qs;
+ reg_rdata_next[0] = erase_suspend_qs;
end
addr_hit[8]: begin
- reg_rdata_next[0] = region_cfg_regwen_1_qs;
+ reg_rdata_next[0] = region_cfg_regwen_0_qs;
end
addr_hit[9]: begin
- reg_rdata_next[0] = region_cfg_regwen_2_qs;
+ reg_rdata_next[0] = region_cfg_regwen_1_qs;
end
addr_hit[10]: begin
- reg_rdata_next[0] = region_cfg_regwen_3_qs;
+ reg_rdata_next[0] = region_cfg_regwen_2_qs;
end
addr_hit[11]: begin
- reg_rdata_next[0] = region_cfg_regwen_4_qs;
+ reg_rdata_next[0] = region_cfg_regwen_3_qs;
end
addr_hit[12]: begin
- reg_rdata_next[0] = region_cfg_regwen_5_qs;
+ reg_rdata_next[0] = region_cfg_regwen_4_qs;
end
addr_hit[13]: begin
- reg_rdata_next[0] = region_cfg_regwen_6_qs;
+ reg_rdata_next[0] = region_cfg_regwen_5_qs;
end
addr_hit[14]: begin
- reg_rdata_next[0] = region_cfg_regwen_7_qs;
+ reg_rdata_next[0] = region_cfg_regwen_6_qs;
end
addr_hit[15]: begin
+ reg_rdata_next[0] = region_cfg_regwen_7_qs;
+ end
+
+ addr_hit[16]: begin
reg_rdata_next[0] = mp_region_cfg_0_en_0_qs;
reg_rdata_next[1] = mp_region_cfg_0_rd_en_0_qs;
reg_rdata_next[2] = mp_region_cfg_0_prog_en_0_qs;
@@ -8731,7 +8770,7 @@
reg_rdata_next[29:20] = mp_region_cfg_0_size_0_qs;
end
- addr_hit[16]: begin
+ addr_hit[17]: begin
reg_rdata_next[0] = mp_region_cfg_1_en_1_qs;
reg_rdata_next[1] = mp_region_cfg_1_rd_en_1_qs;
reg_rdata_next[2] = mp_region_cfg_1_prog_en_1_qs;
@@ -8743,7 +8782,7 @@
reg_rdata_next[29:20] = mp_region_cfg_1_size_1_qs;
end
- addr_hit[17]: begin
+ addr_hit[18]: begin
reg_rdata_next[0] = mp_region_cfg_2_en_2_qs;
reg_rdata_next[1] = mp_region_cfg_2_rd_en_2_qs;
reg_rdata_next[2] = mp_region_cfg_2_prog_en_2_qs;
@@ -8755,7 +8794,7 @@
reg_rdata_next[29:20] = mp_region_cfg_2_size_2_qs;
end
- addr_hit[18]: begin
+ addr_hit[19]: begin
reg_rdata_next[0] = mp_region_cfg_3_en_3_qs;
reg_rdata_next[1] = mp_region_cfg_3_rd_en_3_qs;
reg_rdata_next[2] = mp_region_cfg_3_prog_en_3_qs;
@@ -8767,7 +8806,7 @@
reg_rdata_next[29:20] = mp_region_cfg_3_size_3_qs;
end
- addr_hit[19]: begin
+ addr_hit[20]: begin
reg_rdata_next[0] = mp_region_cfg_4_en_4_qs;
reg_rdata_next[1] = mp_region_cfg_4_rd_en_4_qs;
reg_rdata_next[2] = mp_region_cfg_4_prog_en_4_qs;
@@ -8779,7 +8818,7 @@
reg_rdata_next[29:20] = mp_region_cfg_4_size_4_qs;
end
- addr_hit[20]: begin
+ addr_hit[21]: begin
reg_rdata_next[0] = mp_region_cfg_5_en_5_qs;
reg_rdata_next[1] = mp_region_cfg_5_rd_en_5_qs;
reg_rdata_next[2] = mp_region_cfg_5_prog_en_5_qs;
@@ -8791,7 +8830,7 @@
reg_rdata_next[29:20] = mp_region_cfg_5_size_5_qs;
end
- addr_hit[21]: begin
+ addr_hit[22]: begin
reg_rdata_next[0] = mp_region_cfg_6_en_6_qs;
reg_rdata_next[1] = mp_region_cfg_6_rd_en_6_qs;
reg_rdata_next[2] = mp_region_cfg_6_prog_en_6_qs;
@@ -8803,7 +8842,7 @@
reg_rdata_next[29:20] = mp_region_cfg_6_size_6_qs;
end
- addr_hit[22]: begin
+ addr_hit[23]: begin
reg_rdata_next[0] = mp_region_cfg_7_en_7_qs;
reg_rdata_next[1] = mp_region_cfg_7_rd_en_7_qs;
reg_rdata_next[2] = mp_region_cfg_7_prog_en_7_qs;
@@ -8815,7 +8854,7 @@
reg_rdata_next[29:20] = mp_region_cfg_7_size_7_qs;
end
- addr_hit[23]: begin
+ addr_hit[24]: begin
reg_rdata_next[0] = default_region_rd_en_qs;
reg_rdata_next[1] = default_region_prog_en_qs;
reg_rdata_next[2] = default_region_erase_en_qs;
@@ -8824,23 +8863,23 @@
reg_rdata_next[5] = default_region_he_en_qs;
end
- addr_hit[24]: begin
+ addr_hit[25]: begin
reg_rdata_next[0] = bank0_info0_regwen_0_qs;
end
- addr_hit[25]: begin
+ addr_hit[26]: begin
reg_rdata_next[0] = bank0_info0_regwen_1_qs;
end
- addr_hit[26]: begin
+ addr_hit[27]: begin
reg_rdata_next[0] = bank0_info0_regwen_2_qs;
end
- addr_hit[27]: begin
+ addr_hit[28]: begin
reg_rdata_next[0] = bank0_info0_regwen_3_qs;
end
- addr_hit[28]: begin
+ addr_hit[29]: begin
reg_rdata_next[0] = bank0_info0_page_cfg_0_en_0_qs;
reg_rdata_next[1] = bank0_info0_page_cfg_0_rd_en_0_qs;
reg_rdata_next[2] = bank0_info0_page_cfg_0_prog_en_0_qs;
@@ -8850,7 +8889,7 @@
reg_rdata_next[6] = bank0_info0_page_cfg_0_he_en_0_qs;
end
- addr_hit[29]: begin
+ addr_hit[30]: begin
reg_rdata_next[0] = bank0_info0_page_cfg_1_en_1_qs;
reg_rdata_next[1] = bank0_info0_page_cfg_1_rd_en_1_qs;
reg_rdata_next[2] = bank0_info0_page_cfg_1_prog_en_1_qs;
@@ -8860,7 +8899,7 @@
reg_rdata_next[6] = bank0_info0_page_cfg_1_he_en_1_qs;
end
- addr_hit[30]: begin
+ addr_hit[31]: begin
reg_rdata_next[0] = bank0_info0_page_cfg_2_en_2_qs;
reg_rdata_next[1] = bank0_info0_page_cfg_2_rd_en_2_qs;
reg_rdata_next[2] = bank0_info0_page_cfg_2_prog_en_2_qs;
@@ -8870,7 +8909,7 @@
reg_rdata_next[6] = bank0_info0_page_cfg_2_he_en_2_qs;
end
- addr_hit[31]: begin
+ addr_hit[32]: begin
reg_rdata_next[0] = bank0_info0_page_cfg_3_en_3_qs;
reg_rdata_next[1] = bank0_info0_page_cfg_3_rd_en_3_qs;
reg_rdata_next[2] = bank0_info0_page_cfg_3_prog_en_3_qs;
@@ -8880,23 +8919,23 @@
reg_rdata_next[6] = bank0_info0_page_cfg_3_he_en_3_qs;
end
- addr_hit[32]: begin
+ addr_hit[33]: begin
reg_rdata_next[0] = bank0_info1_regwen_0_qs;
end
- addr_hit[33]: begin
+ addr_hit[34]: begin
reg_rdata_next[0] = bank0_info1_regwen_1_qs;
end
- addr_hit[34]: begin
+ addr_hit[35]: begin
reg_rdata_next[0] = bank0_info1_regwen_2_qs;
end
- addr_hit[35]: begin
+ addr_hit[36]: begin
reg_rdata_next[0] = bank0_info1_regwen_3_qs;
end
- addr_hit[36]: begin
+ addr_hit[37]: begin
reg_rdata_next[0] = bank0_info1_page_cfg_0_en_0_qs;
reg_rdata_next[1] = bank0_info1_page_cfg_0_rd_en_0_qs;
reg_rdata_next[2] = bank0_info1_page_cfg_0_prog_en_0_qs;
@@ -8906,7 +8945,7 @@
reg_rdata_next[6] = bank0_info1_page_cfg_0_he_en_0_qs;
end
- addr_hit[37]: begin
+ addr_hit[38]: begin
reg_rdata_next[0] = bank0_info1_page_cfg_1_en_1_qs;
reg_rdata_next[1] = bank0_info1_page_cfg_1_rd_en_1_qs;
reg_rdata_next[2] = bank0_info1_page_cfg_1_prog_en_1_qs;
@@ -8916,7 +8955,7 @@
reg_rdata_next[6] = bank0_info1_page_cfg_1_he_en_1_qs;
end
- addr_hit[38]: begin
+ addr_hit[39]: begin
reg_rdata_next[0] = bank0_info1_page_cfg_2_en_2_qs;
reg_rdata_next[1] = bank0_info1_page_cfg_2_rd_en_2_qs;
reg_rdata_next[2] = bank0_info1_page_cfg_2_prog_en_2_qs;
@@ -8926,7 +8965,7 @@
reg_rdata_next[6] = bank0_info1_page_cfg_2_he_en_2_qs;
end
- addr_hit[39]: begin
+ addr_hit[40]: begin
reg_rdata_next[0] = bank0_info1_page_cfg_3_en_3_qs;
reg_rdata_next[1] = bank0_info1_page_cfg_3_rd_en_3_qs;
reg_rdata_next[2] = bank0_info1_page_cfg_3_prog_en_3_qs;
@@ -8936,23 +8975,23 @@
reg_rdata_next[6] = bank0_info1_page_cfg_3_he_en_3_qs;
end
- addr_hit[40]: begin
+ addr_hit[41]: begin
reg_rdata_next[0] = bank1_info0_regwen_0_qs;
end
- addr_hit[41]: begin
+ addr_hit[42]: begin
reg_rdata_next[0] = bank1_info0_regwen_1_qs;
end
- addr_hit[42]: begin
+ addr_hit[43]: begin
reg_rdata_next[0] = bank1_info0_regwen_2_qs;
end
- addr_hit[43]: begin
+ addr_hit[44]: begin
reg_rdata_next[0] = bank1_info0_regwen_3_qs;
end
- addr_hit[44]: begin
+ addr_hit[45]: begin
reg_rdata_next[0] = bank1_info0_page_cfg_0_en_0_qs;
reg_rdata_next[1] = bank1_info0_page_cfg_0_rd_en_0_qs;
reg_rdata_next[2] = bank1_info0_page_cfg_0_prog_en_0_qs;
@@ -8962,7 +9001,7 @@
reg_rdata_next[6] = bank1_info0_page_cfg_0_he_en_0_qs;
end
- addr_hit[45]: begin
+ addr_hit[46]: begin
reg_rdata_next[0] = bank1_info0_page_cfg_1_en_1_qs;
reg_rdata_next[1] = bank1_info0_page_cfg_1_rd_en_1_qs;
reg_rdata_next[2] = bank1_info0_page_cfg_1_prog_en_1_qs;
@@ -8972,7 +9011,7 @@
reg_rdata_next[6] = bank1_info0_page_cfg_1_he_en_1_qs;
end
- addr_hit[46]: begin
+ addr_hit[47]: begin
reg_rdata_next[0] = bank1_info0_page_cfg_2_en_2_qs;
reg_rdata_next[1] = bank1_info0_page_cfg_2_rd_en_2_qs;
reg_rdata_next[2] = bank1_info0_page_cfg_2_prog_en_2_qs;
@@ -8982,7 +9021,7 @@
reg_rdata_next[6] = bank1_info0_page_cfg_2_he_en_2_qs;
end
- addr_hit[47]: begin
+ addr_hit[48]: begin
reg_rdata_next[0] = bank1_info0_page_cfg_3_en_3_qs;
reg_rdata_next[1] = bank1_info0_page_cfg_3_rd_en_3_qs;
reg_rdata_next[2] = bank1_info0_page_cfg_3_prog_en_3_qs;
@@ -8992,23 +9031,23 @@
reg_rdata_next[6] = bank1_info0_page_cfg_3_he_en_3_qs;
end
- addr_hit[48]: begin
+ addr_hit[49]: begin
reg_rdata_next[0] = bank1_info1_regwen_0_qs;
end
- addr_hit[49]: begin
+ addr_hit[50]: begin
reg_rdata_next[0] = bank1_info1_regwen_1_qs;
end
- addr_hit[50]: begin
+ addr_hit[51]: begin
reg_rdata_next[0] = bank1_info1_regwen_2_qs;
end
- addr_hit[51]: begin
+ addr_hit[52]: begin
reg_rdata_next[0] = bank1_info1_regwen_3_qs;
end
- addr_hit[52]: begin
+ addr_hit[53]: begin
reg_rdata_next[0] = bank1_info1_page_cfg_0_en_0_qs;
reg_rdata_next[1] = bank1_info1_page_cfg_0_rd_en_0_qs;
reg_rdata_next[2] = bank1_info1_page_cfg_0_prog_en_0_qs;
@@ -9018,7 +9057,7 @@
reg_rdata_next[6] = bank1_info1_page_cfg_0_he_en_0_qs;
end
- addr_hit[53]: begin
+ addr_hit[54]: begin
reg_rdata_next[0] = bank1_info1_page_cfg_1_en_1_qs;
reg_rdata_next[1] = bank1_info1_page_cfg_1_rd_en_1_qs;
reg_rdata_next[2] = bank1_info1_page_cfg_1_prog_en_1_qs;
@@ -9028,7 +9067,7 @@
reg_rdata_next[6] = bank1_info1_page_cfg_1_he_en_1_qs;
end
- addr_hit[54]: begin
+ addr_hit[55]: begin
reg_rdata_next[0] = bank1_info1_page_cfg_2_en_2_qs;
reg_rdata_next[1] = bank1_info1_page_cfg_2_rd_en_2_qs;
reg_rdata_next[2] = bank1_info1_page_cfg_2_prog_en_2_qs;
@@ -9038,7 +9077,7 @@
reg_rdata_next[6] = bank1_info1_page_cfg_2_he_en_2_qs;
end
- addr_hit[55]: begin
+ addr_hit[56]: begin
reg_rdata_next[0] = bank1_info1_page_cfg_3_en_3_qs;
reg_rdata_next[1] = bank1_info1_page_cfg_3_rd_en_3_qs;
reg_rdata_next[2] = bank1_info1_page_cfg_3_prog_en_3_qs;
@@ -9048,21 +9087,21 @@
reg_rdata_next[6] = bank1_info1_page_cfg_3_he_en_3_qs;
end
- addr_hit[56]: begin
+ addr_hit[57]: begin
reg_rdata_next[0] = bank_cfg_regwen_qs;
end
- addr_hit[57]: begin
+ addr_hit[58]: begin
reg_rdata_next[0] = mp_bank_cfg_erase_en_0_qs;
reg_rdata_next[1] = mp_bank_cfg_erase_en_1_qs;
end
- addr_hit[58]: begin
+ addr_hit[59]: begin
reg_rdata_next[0] = op_status_done_qs;
reg_rdata_next[1] = op_status_err_qs;
end
- addr_hit[59]: begin
+ addr_hit[60]: begin
reg_rdata_next[0] = status_rd_full_qs;
reg_rdata_next[1] = status_rd_empty_qs;
reg_rdata_next[2] = status_prog_full_qs;
@@ -9071,22 +9110,22 @@
reg_rdata_next[16:8] = status_error_addr_qs;
end
- addr_hit[60]: begin
+ addr_hit[61]: begin
reg_rdata_next[0] = phy_status_init_wip_qs;
reg_rdata_next[1] = phy_status_prog_normal_avail_qs;
reg_rdata_next[2] = phy_status_prog_repair_avail_qs;
end
- addr_hit[61]: begin
+ addr_hit[62]: begin
reg_rdata_next[31:0] = scratch_qs;
end
- addr_hit[62]: begin
+ addr_hit[63]: begin
reg_rdata_next[4:0] = fifo_lvl_prog_qs;
reg_rdata_next[12:8] = fifo_lvl_rd_qs;
end
- addr_hit[63]: begin
+ addr_hit[64]: begin
reg_rdata_next[0] = fifo_rst_qs;
end
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 5d52357..c8d795b 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -2775,6 +2775,30 @@
name_top: RndCnstFlashCtrlDataKey
randwidth: 128
}
+ {
+ name: RndCnstLfsrSeed
+ desc: Compile-time random bits for initial LFSR seed
+ type: flash_ctrl_pkg::lfsr_seed_t
+ randcount: "32"
+ randtype: data
+ local: "false"
+ default: 0xd89f9dfc
+ expose: "false"
+ name_top: RndCnstFlashCtrlLfsrSeed
+ randwidth: 32
+ }
+ {
+ name: RndCnstLfsrPerm
+ desc: Compile-time random permutation for LFSR output
+ type: flash_ctrl_pkg::lfsr_perm_t
+ randcount: "32"
+ randtype: perm
+ local: "false"
+ default: 0x26ff203d990d87c5e8a98bafec7506855aa99c54
+ expose: "false"
+ name_top: RndCnstFlashCtrlLfsrPerm
+ randwidth: 160
+ }
]
interrupt_list:
[
@@ -2952,11 +2976,11 @@
index: -1
}
{
- struct: edn_entropy
- type: uni
+ struct: edn
+ type: req_rsp
name: edn
- act: rcv
- package: flash_ctrl_pkg
+ act: req
+ package: edn_pkg
inst_name: flash_ctrl
index: -1
}
@@ -9004,11 +9028,11 @@
index: -1
}
{
- struct: edn_entropy
- type: uni
+ struct: edn
+ type: req_rsp
name: edn
- act: rcv
- package: flash_ctrl_pkg
+ act: req
+ package: edn_pkg
inst_name: flash_ctrl
index: -1
}
diff --git a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
index 11e5f61..4e78b11 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
+++ b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
@@ -80,11 +80,11 @@
package: "flash_ctrl_pkg"
},
- { struct: "edn_entropy",
- type: "uni",
+ { struct: "edn",
+ type: "req_rsp",
name: "edn",
- act: "rcv",
- package: "flash_ctrl_pkg"
+ act: "req",
+ package: "edn_pkg"
},
{ struct: "pwr_flash",
@@ -113,13 +113,26 @@
type: "flash_ctrl_pkg::flash_key_t"
randcount: "128",
randtype: "data", // randomize randcount databits
- }
+ },
{ name: "RndCnstDataKey",
desc: "Compile-time random bits for default data key",
type: "flash_ctrl_pkg::flash_key_t"
randcount: "128",
randtype: "data", // randomize randcount databits
- }
+ },
+ { name: "RndCnstLfsrSeed",
+ desc: "Compile-time random bits for initial LFSR seed",
+ type: "flash_ctrl_pkg::lfsr_seed_t"
+ randcount: "32",
+ randtype: "data",
+ },
+ { name: "RndCnstLfsrPerm",
+ desc: "Compile-time random permutation for LFSR output",
+ type: "flash_ctrl_pkg::lfsr_perm_t"
+ randcount: "32",
+ randtype: "perm",
+ },
+
{ name: "RegNumBanks",
desc: "Number of flash banks",
type: "int",
@@ -399,6 +412,26 @@
]
},
+ // erase suspend support
+ { name: "ERASE_SUSPEND",
+ desc: "Suspend erase",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ resval: "0",
+ name: "REQ",
+ desc: '''
+ When 1, request erase suspend.
+ If no erase ongoing, the request is immediately cleared by hardware
+ If erase ongoing, the request is fed to the flash_phy and cleared when the suspend is handled.
+ '''
+ },
+ ],
+ tags: [// Erase suspend must be directly tested
+ "excl:CsrAllTests:CsrExclWrite"],
+ },
+
// Data partition memory properties region setup
{ multireg: {
cname: "FLASH_CTRL",
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
index 3817cfc..d63b801 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
@@ -15,8 +15,10 @@
`include "prim_assert.sv"
module flash_ctrl import flash_ctrl_pkg::*; #(
- parameter flash_key_t RndCnstAddrKey = RndCnstAddrKeyDefault,
- parameter flash_key_t RndCnstDataKey = RndCnstDataKeyDefault
+ parameter flash_key_t RndCnstAddrKey = RndCnstAddrKeyDefault,
+ parameter flash_key_t RndCnstDataKey = RndCnstDataKeyDefault,
+ parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
+ parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault
) (
input clk_i,
input rst_ni,
@@ -46,7 +48,8 @@
output lc_flash_rsp_t lc_o,
input pwrmgr_pkg::pwr_flash_req_t pwrmgr_i,
output pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_o,
- input edn_entropy_t edn_i,
+ output edn_pkg::edn_req_t edn_o,
+ input edn_pkg::edn_rsp_t edn_i,
output keymgr_flash_t keymgr_o,
// Interrupts
@@ -237,16 +240,19 @@
);
prim_lfsr #(
- .EntropyDw(4),
+ .EntropyDw(EdnWidth),
.LfsrDw(LfsrWidth),
- .StateOutDw(LfsrWidth)
+ .StateOutDw(LfsrWidth),
+ .DefaultSeed(RndCnstLfsrSeed),
+ .StatePermEn(1),
+ .StatePerm(RndCnstLfsrPerm)
) u_lfsr (
.clk_i,
.rst_ni,
- .seed_en_i('0),
- .seed_i('0),
+ .seed_en_i(edn_i.edn_ack),
+ .seed_i(edn_i.edn_bus),
.lfsr_en_i(lfsr_en),
- .entropy_i(edn_i.valid ? edn_i.entropy : '0),
+ .entropy_i('0),
.state_o(rand_val)
);
@@ -315,10 +321,7 @@
.phase_o(phase),
// indication that sw has been selected
- .sel_o(if_sel),
-
- // enable lfsr
- .lfsr_en_o(lfsr_en)
+ .sel_o(if_sel)
);
assign op_start = muxed_ctrl.start.q;
@@ -374,9 +377,6 @@
.rma_token_o(lc_o.rma_ack_token),
.rma_rsp_o(lc_o.rma_ack),
- // random value
- .rand_i(rand_val),
-
// outgoing seeds
.seeds_o(keymgr_o.seeds),
.seed_err_o(), // TBD hook-up to Err code register
@@ -393,10 +393,19 @@
.addr_key_o(addr_key),
.data_key_o(data_key),
+ // entropy interface
+ .edn_req_o(edn_o.edn_req),
+ .edn_ack_i(edn_i.edn_ack),
+ .lfsr_en_o(lfsr_en),
+ .rand_i(rand_val),
+
// init ongoing
.init_busy_o(ctrl_init_busy)
);
+ logic unused_edn_fips;
+ assign unused_edn_fips = edn_i.edn_fips;
+
// Program FIFO
// Since the program and read FIFOs are never used at the same time, it should really be one
// FIFO with muxed inputs and outputs. This should be addressed once the flash integration
@@ -642,6 +651,9 @@
assign flash_part_sel = op_part;
assign flash_info_sel = op_info_sel;
+ // tie off hardware clear path
+ assign hw2reg.erase_suspend.d = 1'b0;
+
// Flash memory Properties
// Memory property is page based and thus should use phy addressing
// This should move to flash_phy long term
@@ -670,6 +682,8 @@
.prog_i(prog_op),
.pg_erase_i(erase_op & (erase_flash_type == FlashErasePage)),
.bk_erase_i(erase_op & (erase_flash_type == FlashEraseBank)),
+ .erase_suspend_i(reg2hw.erase_suspend),
+ .erase_suspend_done_o(hw2reg.erase_suspend.de),
.rd_done_o(flash_rd_done),
.prog_done_o(flash_prog_done),
.erase_done_o(flash_erase_done),
@@ -685,6 +699,8 @@
.prog_o(flash_o.prog),
.pg_erase_o(flash_o.pg_erase),
.bk_erase_o(flash_o.bk_erase),
+ .erase_suspend_o(flash_o.erase_suspend),
+ .erase_suspend_done_i(flash_i.erase_suspend_done),
.rd_done_i(flash_i.rd_done),
.prog_done_i(flash_i.prog_done),
.erase_done_i(flash_i.erase_done)
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
index ada0f0a..80e596d 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
@@ -82,10 +82,24 @@
// parameters for connected components
parameter int SeedWidth = 256;
parameter int KeyWidth = 128;
- parameter int LfsrWidth = 32;
-
+ parameter int EdnWidth = edn_pkg::ENDPOINT_BUS_WIDTH;
typedef logic [KeyWidth-1:0] flash_key_t;
+ // Default Lfsr configurations
+ // These LFSR parameters have been generated with
+ // $ hw/ip/prim/util/gen-lfsr-seed.py --width 32 --seed 1274809145 --prefix ""
+ parameter int LfsrWidth = 32;
+ typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+ typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+ parameter lfsr_seed_t RndCnstLfsrSeedDefault = 32'ha8cee782;
+ parameter lfsr_perm_t RndCnstLfsrPermDefault = {
+ 160'hd60bc7d86445da9347e0ccdd05b281df95238bb5
+ };
+
+ // These LFSR parameters have been generated with
+ // $ hw/ip/prim/util/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix ""
+
+
// lcmgr phase enum
typedef enum logic [1:0] {
PhaseSeed,
@@ -271,6 +285,7 @@
logic prog;
logic pg_erase;
logic bk_erase;
+ logic erase_suspend;
flash_part_e part;
logic [InfoTypesWidth-1:0] info_sel;
logic [BusAddrW-1:0] addr;
@@ -285,24 +300,25 @@
// default value of flash_req_t (for dangling ports)
parameter flash_req_t FLASH_REQ_DEFAULT = '{
- req: '0,
- scramble_en: '0,
- ecc_en: '0,
- he_en: '0,
- rd: '0,
- prog: '0,
- pg_erase: '0,
- bk_erase: '0,
- part: FlashPartData,
- info_sel: '0,
- addr: '0,
- prog_data: '0,
- prog_last: '0,
- prog_type: FlashProgNormal,
- region_cfgs: '0,
- addr_key: RndCnstAddrKeyDefault,
- data_key: RndCnstDataKeyDefault,
- rd_buf_en: 1'b0
+ req: '0,
+ scramble_en: '0,
+ ecc_en: '0,
+ he_en: '0,
+ rd: '0,
+ prog: '0,
+ pg_erase: '0,
+ bk_erase: '0,
+ erase_suspend: '0,
+ part: FlashPartData,
+ info_sel: '0,
+ addr: '0,
+ prog_data: '0,
+ prog_last: '0,
+ prog_type: FlashProgNormal,
+ region_cfgs: '0,
+ addr_key: RndCnstAddrKeyDefault,
+ data_key: RndCnstDataKeyDefault,
+ rd_buf_en: 1'b0
};
// memory to flash controller
@@ -314,17 +330,19 @@
logic rd_err;
logic [BusWidth-1:0] rd_data;
logic init_busy;
+ logic erase_suspend_done;
} flash_rsp_t;
// default value of flash_rsp_t (for dangling ports)
parameter flash_rsp_t FLASH_RSP_DEFAULT = '{
- prog_type_avail: '{default: '1},
- rd_done: 1'b0,
- prog_done: 1'b0,
- erase_done: 1'b0,
- rd_err: '0,
- rd_data: '0,
- init_busy: 1'b0
+ prog_type_avail: '{default: '1},
+ rd_done: 1'b0,
+ prog_done: 1'b0,
+ erase_done: 1'b0,
+ rd_err: '0,
+ rd_data: '0,
+ init_busy: 1'b0,
+ erase_suspend_done: 1'b1
};
////////////////////////////
@@ -356,22 +374,11 @@
}
};
- // place holder for interface to EDN, replace with real one later
- typedef struct packed {
- logic valid;
- logic [3:0] entropy;
- } edn_entropy_t;
-
parameter lc_flash_req_t LC_FLASH_REQ_DEFAULT = '{
rma_req: 1'b0,
rma_req_token: '0
};
- parameter edn_entropy_t EDN_ENTROPY_DEFAULT = '{
- valid: 1'b1,
- entropy: '0
- };
-
// dft_en jtag selection
typedef enum logic [2:0] {
FlashLcTckSel,
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
index b89a355..8636b46 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
@@ -128,6 +128,10 @@
} flash_ctrl_reg2hw_prog_type_en_reg_t;
typedef struct packed {
+ logic q;
+ } flash_ctrl_reg2hw_erase_suspend_reg_t;
+
+ typedef struct packed {
struct packed {
logic q;
} en;
@@ -335,6 +339,11 @@
} flash_ctrl_hw2reg_control_reg_t;
typedef struct packed {
+ logic d;
+ logic de;
+ } flash_ctrl_hw2reg_erase_suspend_reg_t;
+
+ typedef struct packed {
struct packed {
logic d;
logic de;
@@ -392,12 +401,13 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [447:442]
- flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [441:436]
- flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [435:424]
- flash_ctrl_reg2hw_control_reg_t control; // [423:405]
- flash_ctrl_reg2hw_addr_reg_t addr; // [404:373]
- flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en; // [372:371]
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [448:443]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [442:437]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [436:425]
+ flash_ctrl_reg2hw_control_reg_t control; // [424:406]
+ flash_ctrl_reg2hw_addr_reg_t addr; // [405:374]
+ flash_ctrl_reg2hw_prog_type_en_reg_t prog_type_en; // [373:372]
+ flash_ctrl_reg2hw_erase_suspend_reg_t erase_suspend; // [371:371]
flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [370:163]
flash_ctrl_reg2hw_default_region_reg_t default_region; // [162:157]
flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t [3:0] bank0_info0_page_cfg; // [156:129]
@@ -414,9 +424,10 @@
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- flash_ctrl_hw2reg_intr_state_reg_t intr_state; // [44:33]
- flash_ctrl_hw2reg_ctrl_regwen_reg_t ctrl_regwen; // [32:32]
- flash_ctrl_hw2reg_control_reg_t control; // [31:30]
+ flash_ctrl_hw2reg_intr_state_reg_t intr_state; // [46:35]
+ flash_ctrl_hw2reg_ctrl_regwen_reg_t ctrl_regwen; // [34:34]
+ flash_ctrl_hw2reg_control_reg_t control; // [33:32]
+ flash_ctrl_hw2reg_erase_suspend_reg_t erase_suspend; // [31:30]
flash_ctrl_hw2reg_op_status_reg_t op_status; // [29:26]
flash_ctrl_hw2reg_status_reg_t status; // [25:6]
flash_ctrl_hw2reg_phy_status_reg_t phy_status; // [5:0]
@@ -430,68 +441,69 @@
parameter logic [8:0] FLASH_CTRL_CONTROL_OFFSET = 9'h 10;
parameter logic [8:0] FLASH_CTRL_ADDR_OFFSET = 9'h 14;
parameter logic [8:0] FLASH_CTRL_PROG_TYPE_EN_OFFSET = 9'h 18;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET = 9'h 1c;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET = 9'h 20;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET = 9'h 24;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET = 9'h 28;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET = 9'h 2c;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET = 9'h 30;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET = 9'h 34;
- parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET = 9'h 38;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_0_OFFSET = 9'h 3c;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_1_OFFSET = 9'h 40;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_2_OFFSET = 9'h 44;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_3_OFFSET = 9'h 48;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_4_OFFSET = 9'h 4c;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_5_OFFSET = 9'h 50;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_6_OFFSET = 9'h 54;
- parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_7_OFFSET = 9'h 58;
- parameter logic [8:0] FLASH_CTRL_DEFAULT_REGION_OFFSET = 9'h 5c;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET = 9'h 60;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET = 9'h 64;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET = 9'h 68;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET = 9'h 6c;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET = 9'h 70;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET = 9'h 74;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET = 9'h 78;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET = 9'h 7c;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_0_OFFSET = 9'h 80;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_1_OFFSET = 9'h 84;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_2_OFFSET = 9'h 88;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_3_OFFSET = 9'h 8c;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0_OFFSET = 9'h 90;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1_OFFSET = 9'h 94;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2_OFFSET = 9'h 98;
- parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3_OFFSET = 9'h 9c;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET = 9'h a0;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET = 9'h a4;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET = 9'h a8;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET = 9'h ac;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET = 9'h b0;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET = 9'h b4;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET = 9'h b8;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET = 9'h bc;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_0_OFFSET = 9'h c0;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_1_OFFSET = 9'h c4;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_2_OFFSET = 9'h c8;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_3_OFFSET = 9'h cc;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0_OFFSET = 9'h d0;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1_OFFSET = 9'h d4;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2_OFFSET = 9'h d8;
- parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3_OFFSET = 9'h dc;
- parameter logic [8:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 9'h e0;
- parameter logic [8:0] FLASH_CTRL_MP_BANK_CFG_OFFSET = 9'h e4;
- parameter logic [8:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h e8;
- parameter logic [8:0] FLASH_CTRL_STATUS_OFFSET = 9'h ec;
- parameter logic [8:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h f0;
- parameter logic [8:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h f4;
- parameter logic [8:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h f8;
- parameter logic [8:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h fc;
+ parameter logic [8:0] FLASH_CTRL_ERASE_SUSPEND_OFFSET = 9'h 1c;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET = 9'h 20;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET = 9'h 24;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET = 9'h 28;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET = 9'h 2c;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET = 9'h 30;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET = 9'h 34;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET = 9'h 38;
+ parameter logic [8:0] FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET = 9'h 3c;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_0_OFFSET = 9'h 40;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_1_OFFSET = 9'h 44;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_2_OFFSET = 9'h 48;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_3_OFFSET = 9'h 4c;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_4_OFFSET = 9'h 50;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_5_OFFSET = 9'h 54;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_6_OFFSET = 9'h 58;
+ parameter logic [8:0] FLASH_CTRL_MP_REGION_CFG_7_OFFSET = 9'h 5c;
+ parameter logic [8:0] FLASH_CTRL_DEFAULT_REGION_OFFSET = 9'h 60;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET = 9'h 64;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET = 9'h 68;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET = 9'h 6c;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET = 9'h 70;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET = 9'h 74;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET = 9'h 78;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET = 9'h 7c;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET = 9'h 80;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_0_OFFSET = 9'h 84;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_1_OFFSET = 9'h 88;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_2_OFFSET = 9'h 8c;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_REGWEN_3_OFFSET = 9'h 90;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0_OFFSET = 9'h 94;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1_OFFSET = 9'h 98;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2_OFFSET = 9'h 9c;
+ parameter logic [8:0] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3_OFFSET = 9'h a0;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET = 9'h a4;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET = 9'h a8;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET = 9'h ac;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET = 9'h b0;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET = 9'h b4;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET = 9'h b8;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET = 9'h bc;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET = 9'h c0;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_0_OFFSET = 9'h c4;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_1_OFFSET = 9'h c8;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_2_OFFSET = 9'h cc;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_REGWEN_3_OFFSET = 9'h d0;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0_OFFSET = 9'h d4;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1_OFFSET = 9'h d8;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2_OFFSET = 9'h dc;
+ parameter logic [8:0] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3_OFFSET = 9'h e0;
+ parameter logic [8:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 9'h e4;
+ parameter logic [8:0] FLASH_CTRL_MP_BANK_CFG_OFFSET = 9'h e8;
+ parameter logic [8:0] FLASH_CTRL_OP_STATUS_OFFSET = 9'h ec;
+ parameter logic [8:0] FLASH_CTRL_STATUS_OFFSET = 9'h f0;
+ parameter logic [8:0] FLASH_CTRL_PHY_STATUS_OFFSET = 9'h f4;
+ parameter logic [8:0] FLASH_CTRL_SCRATCH_OFFSET = 9'h f8;
+ parameter logic [8:0] FLASH_CTRL_FIFO_LVL_OFFSET = 9'h fc;
+ parameter logic [8:0] FLASH_CTRL_FIFO_RST_OFFSET = 9'h 100;
// Window parameter
- parameter logic [8:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 100;
+ parameter logic [8:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 104;
parameter logic [8:0] FLASH_CTRL_PROG_FIFO_SIZE = 9'h 4;
- parameter logic [8:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 104;
+ parameter logic [8:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 108;
parameter logic [8:0] FLASH_CTRL_RD_FIFO_SIZE = 9'h 4;
// Register Index
@@ -503,6 +515,7 @@
FLASH_CTRL_CONTROL,
FLASH_CTRL_ADDR,
FLASH_CTRL_PROG_TYPE_EN,
+ FLASH_CTRL_ERASE_SUSPEND,
FLASH_CTRL_REGION_CFG_REGWEN_0,
FLASH_CTRL_REGION_CFG_REGWEN_1,
FLASH_CTRL_REGION_CFG_REGWEN_2,
@@ -563,7 +576,7 @@
} flash_ctrl_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] FLASH_CTRL_PERMIT [64] = '{
+ parameter logic [3:0] FLASH_CTRL_PERMIT [65] = '{
4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE
4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST
@@ -571,63 +584,64 @@
4'b 1111, // index[ 4] FLASH_CTRL_CONTROL
4'b 1111, // index[ 5] FLASH_CTRL_ADDR
4'b 0001, // index[ 6] FLASH_CTRL_PROG_TYPE_EN
- 4'b 0001, // index[ 7] FLASH_CTRL_REGION_CFG_REGWEN_0
- 4'b 0001, // index[ 8] FLASH_CTRL_REGION_CFG_REGWEN_1
- 4'b 0001, // index[ 9] FLASH_CTRL_REGION_CFG_REGWEN_2
- 4'b 0001, // index[10] FLASH_CTRL_REGION_CFG_REGWEN_3
- 4'b 0001, // index[11] FLASH_CTRL_REGION_CFG_REGWEN_4
- 4'b 0001, // index[12] FLASH_CTRL_REGION_CFG_REGWEN_5
- 4'b 0001, // index[13] FLASH_CTRL_REGION_CFG_REGWEN_6
- 4'b 0001, // index[14] FLASH_CTRL_REGION_CFG_REGWEN_7
- 4'b 1111, // index[15] FLASH_CTRL_MP_REGION_CFG_0
- 4'b 1111, // index[16] FLASH_CTRL_MP_REGION_CFG_1
- 4'b 1111, // index[17] FLASH_CTRL_MP_REGION_CFG_2
- 4'b 1111, // index[18] FLASH_CTRL_MP_REGION_CFG_3
- 4'b 1111, // index[19] FLASH_CTRL_MP_REGION_CFG_4
- 4'b 1111, // index[20] FLASH_CTRL_MP_REGION_CFG_5
- 4'b 1111, // index[21] FLASH_CTRL_MP_REGION_CFG_6
- 4'b 1111, // index[22] FLASH_CTRL_MP_REGION_CFG_7
- 4'b 0001, // index[23] FLASH_CTRL_DEFAULT_REGION
- 4'b 0001, // index[24] FLASH_CTRL_BANK0_INFO0_REGWEN_0
- 4'b 0001, // index[25] FLASH_CTRL_BANK0_INFO0_REGWEN_1
- 4'b 0001, // index[26] FLASH_CTRL_BANK0_INFO0_REGWEN_2
- 4'b 0001, // index[27] FLASH_CTRL_BANK0_INFO0_REGWEN_3
- 4'b 0001, // index[28] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0
- 4'b 0001, // index[29] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1
- 4'b 0001, // index[30] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2
- 4'b 0001, // index[31] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3
- 4'b 0001, // index[32] FLASH_CTRL_BANK0_INFO1_REGWEN_0
- 4'b 0001, // index[33] FLASH_CTRL_BANK0_INFO1_REGWEN_1
- 4'b 0001, // index[34] FLASH_CTRL_BANK0_INFO1_REGWEN_2
- 4'b 0001, // index[35] FLASH_CTRL_BANK0_INFO1_REGWEN_3
- 4'b 0001, // index[36] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0
- 4'b 0001, // index[37] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1
- 4'b 0001, // index[38] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2
- 4'b 0001, // index[39] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3
- 4'b 0001, // index[40] FLASH_CTRL_BANK1_INFO0_REGWEN_0
- 4'b 0001, // index[41] FLASH_CTRL_BANK1_INFO0_REGWEN_1
- 4'b 0001, // index[42] FLASH_CTRL_BANK1_INFO0_REGWEN_2
- 4'b 0001, // index[43] FLASH_CTRL_BANK1_INFO0_REGWEN_3
- 4'b 0001, // index[44] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0
- 4'b 0001, // index[45] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1
- 4'b 0001, // index[46] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2
- 4'b 0001, // index[47] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3
- 4'b 0001, // index[48] FLASH_CTRL_BANK1_INFO1_REGWEN_0
- 4'b 0001, // index[49] FLASH_CTRL_BANK1_INFO1_REGWEN_1
- 4'b 0001, // index[50] FLASH_CTRL_BANK1_INFO1_REGWEN_2
- 4'b 0001, // index[51] FLASH_CTRL_BANK1_INFO1_REGWEN_3
- 4'b 0001, // index[52] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0
- 4'b 0001, // index[53] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1
- 4'b 0001, // index[54] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2
- 4'b 0001, // index[55] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3
- 4'b 0001, // index[56] FLASH_CTRL_BANK_CFG_REGWEN
- 4'b 0001, // index[57] FLASH_CTRL_MP_BANK_CFG
- 4'b 0001, // index[58] FLASH_CTRL_OP_STATUS
- 4'b 0111, // index[59] FLASH_CTRL_STATUS
- 4'b 0001, // index[60] FLASH_CTRL_PHY_STATUS
- 4'b 1111, // index[61] FLASH_CTRL_SCRATCH
- 4'b 0011, // index[62] FLASH_CTRL_FIFO_LVL
- 4'b 0001 // index[63] FLASH_CTRL_FIFO_RST
+ 4'b 0001, // index[ 7] FLASH_CTRL_ERASE_SUSPEND
+ 4'b 0001, // index[ 8] FLASH_CTRL_REGION_CFG_REGWEN_0
+ 4'b 0001, // index[ 9] FLASH_CTRL_REGION_CFG_REGWEN_1
+ 4'b 0001, // index[10] FLASH_CTRL_REGION_CFG_REGWEN_2
+ 4'b 0001, // index[11] FLASH_CTRL_REGION_CFG_REGWEN_3
+ 4'b 0001, // index[12] FLASH_CTRL_REGION_CFG_REGWEN_4
+ 4'b 0001, // index[13] FLASH_CTRL_REGION_CFG_REGWEN_5
+ 4'b 0001, // index[14] FLASH_CTRL_REGION_CFG_REGWEN_6
+ 4'b 0001, // index[15] FLASH_CTRL_REGION_CFG_REGWEN_7
+ 4'b 1111, // index[16] FLASH_CTRL_MP_REGION_CFG_0
+ 4'b 1111, // index[17] FLASH_CTRL_MP_REGION_CFG_1
+ 4'b 1111, // index[18] FLASH_CTRL_MP_REGION_CFG_2
+ 4'b 1111, // index[19] FLASH_CTRL_MP_REGION_CFG_3
+ 4'b 1111, // index[20] FLASH_CTRL_MP_REGION_CFG_4
+ 4'b 1111, // index[21] FLASH_CTRL_MP_REGION_CFG_5
+ 4'b 1111, // index[22] FLASH_CTRL_MP_REGION_CFG_6
+ 4'b 1111, // index[23] FLASH_CTRL_MP_REGION_CFG_7
+ 4'b 0001, // index[24] FLASH_CTRL_DEFAULT_REGION
+ 4'b 0001, // index[25] FLASH_CTRL_BANK0_INFO0_REGWEN_0
+ 4'b 0001, // index[26] FLASH_CTRL_BANK0_INFO0_REGWEN_1
+ 4'b 0001, // index[27] FLASH_CTRL_BANK0_INFO0_REGWEN_2
+ 4'b 0001, // index[28] FLASH_CTRL_BANK0_INFO0_REGWEN_3
+ 4'b 0001, // index[29] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0
+ 4'b 0001, // index[30] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1
+ 4'b 0001, // index[31] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2
+ 4'b 0001, // index[32] FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3
+ 4'b 0001, // index[33] FLASH_CTRL_BANK0_INFO1_REGWEN_0
+ 4'b 0001, // index[34] FLASH_CTRL_BANK0_INFO1_REGWEN_1
+ 4'b 0001, // index[35] FLASH_CTRL_BANK0_INFO1_REGWEN_2
+ 4'b 0001, // index[36] FLASH_CTRL_BANK0_INFO1_REGWEN_3
+ 4'b 0001, // index[37] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0
+ 4'b 0001, // index[38] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1
+ 4'b 0001, // index[39] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2
+ 4'b 0001, // index[40] FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3
+ 4'b 0001, // index[41] FLASH_CTRL_BANK1_INFO0_REGWEN_0
+ 4'b 0001, // index[42] FLASH_CTRL_BANK1_INFO0_REGWEN_1
+ 4'b 0001, // index[43] FLASH_CTRL_BANK1_INFO0_REGWEN_2
+ 4'b 0001, // index[44] FLASH_CTRL_BANK1_INFO0_REGWEN_3
+ 4'b 0001, // index[45] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0
+ 4'b 0001, // index[46] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1
+ 4'b 0001, // index[47] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2
+ 4'b 0001, // index[48] FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3
+ 4'b 0001, // index[49] FLASH_CTRL_BANK1_INFO1_REGWEN_0
+ 4'b 0001, // index[50] FLASH_CTRL_BANK1_INFO1_REGWEN_1
+ 4'b 0001, // index[51] FLASH_CTRL_BANK1_INFO1_REGWEN_2
+ 4'b 0001, // index[52] FLASH_CTRL_BANK1_INFO1_REGWEN_3
+ 4'b 0001, // index[53] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0
+ 4'b 0001, // index[54] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1
+ 4'b 0001, // index[55] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2
+ 4'b 0001, // index[56] FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3
+ 4'b 0001, // index[57] FLASH_CTRL_BANK_CFG_REGWEN
+ 4'b 0001, // index[58] FLASH_CTRL_MP_BANK_CFG
+ 4'b 0001, // index[59] FLASH_CTRL_OP_STATUS
+ 4'b 0111, // index[60] FLASH_CTRL_STATUS
+ 4'b 0001, // index[61] FLASH_CTRL_PHY_STATUS
+ 4'b 1111, // index[62] FLASH_CTRL_SCRATCH
+ 4'b 0011, // index[63] FLASH_CTRL_FIFO_LVL
+ 4'b 0001 // index[64] FLASH_CTRL_FIFO_RST
};
endpackage
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv
index a45cd51..b9b23df 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv
@@ -88,10 +88,10 @@
reg_steer = 2; // Default set to register
// TODO: Can below codes be unique case () inside ?
- if (tl_i.a_address[AW-1:0] >= 256 && tl_i.a_address[AW-1:0] < 260) begin
+ if (tl_i.a_address[AW-1:0] >= 260 && tl_i.a_address[AW-1:0] < 264) begin
reg_steer = 0;
end
- if (tl_i.a_address[AW-1:0] >= 260 && tl_i.a_address[AW-1:0] < 264) begin
+ if (tl_i.a_address[AW-1:0] >= 264 && tl_i.a_address[AW-1:0] < 268) begin
reg_steer = 1;
end
end
@@ -201,6 +201,9 @@
logic prog_type_en_repair_qs;
logic prog_type_en_repair_wd;
logic prog_type_en_repair_we;
+ logic erase_suspend_qs;
+ logic erase_suspend_wd;
+ logic erase_suspend_we;
logic region_cfg_regwen_0_qs;
logic region_cfg_regwen_0_wd;
logic region_cfg_regwen_0_we;
@@ -1570,6 +1573,33 @@
);
+ // R[erase_suspend]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_erase_suspend (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (erase_suspend_we),
+ .wd (erase_suspend_wd),
+
+ // from internal hardware
+ .de (hw2reg.erase_suspend.de),
+ .d (hw2reg.erase_suspend.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.erase_suspend.q ),
+
+ // to register interface (read)
+ .qs (erase_suspend_qs)
+ );
+
+
// Subregister 0 of Multireg region_cfg_regwen
// R[region_cfg_regwen_0]: V(False)
@@ -7729,7 +7759,7 @@
- logic [63:0] addr_hit;
+ logic [64:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
@@ -7739,63 +7769,64 @@
addr_hit[ 4] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET);
addr_hit[ 5] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
addr_hit[ 6] = (reg_addr == FLASH_CTRL_PROG_TYPE_EN_OFFSET);
- addr_hit[ 7] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET);
- addr_hit[ 8] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET);
- addr_hit[ 9] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET);
- addr_hit[10] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET);
- addr_hit[11] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET);
- addr_hit[12] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET);
- addr_hit[13] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET);
- addr_hit[14] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET);
- addr_hit[15] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_0_OFFSET);
- addr_hit[16] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_1_OFFSET);
- addr_hit[17] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_2_OFFSET);
- addr_hit[18] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_3_OFFSET);
- addr_hit[19] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_4_OFFSET);
- addr_hit[20] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_5_OFFSET);
- addr_hit[21] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_6_OFFSET);
- addr_hit[22] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_7_OFFSET);
- addr_hit[23] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
- addr_hit[24] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET);
- addr_hit[25] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET);
- addr_hit[26] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET);
- addr_hit[27] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET);
- addr_hit[28] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET);
- addr_hit[29] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET);
- addr_hit[30] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET);
- addr_hit[31] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET);
- addr_hit[32] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_0_OFFSET);
- addr_hit[33] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_1_OFFSET);
- addr_hit[34] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_2_OFFSET);
- addr_hit[35] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_3_OFFSET);
- addr_hit[36] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0_OFFSET);
- addr_hit[37] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1_OFFSET);
- addr_hit[38] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2_OFFSET);
- addr_hit[39] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3_OFFSET);
- addr_hit[40] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET);
- addr_hit[41] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET);
- addr_hit[42] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET);
- addr_hit[43] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET);
- addr_hit[44] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET);
- addr_hit[45] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET);
- addr_hit[46] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET);
- addr_hit[47] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET);
- addr_hit[48] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_0_OFFSET);
- addr_hit[49] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_1_OFFSET);
- addr_hit[50] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_2_OFFSET);
- addr_hit[51] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_3_OFFSET);
- addr_hit[52] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0_OFFSET);
- addr_hit[53] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1_OFFSET);
- addr_hit[54] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2_OFFSET);
- addr_hit[55] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3_OFFSET);
- addr_hit[56] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET);
- addr_hit[57] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET);
- addr_hit[58] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
- addr_hit[59] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
- addr_hit[60] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
- addr_hit[61] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
- addr_hit[62] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
- addr_hit[63] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
+ addr_hit[ 7] = (reg_addr == FLASH_CTRL_ERASE_SUSPEND_OFFSET);
+ addr_hit[ 8] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET);
+ addr_hit[ 9] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET);
+ addr_hit[10] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET);
+ addr_hit[11] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET);
+ addr_hit[12] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET);
+ addr_hit[13] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET);
+ addr_hit[14] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET);
+ addr_hit[15] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET);
+ addr_hit[16] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_0_OFFSET);
+ addr_hit[17] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_1_OFFSET);
+ addr_hit[18] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_2_OFFSET);
+ addr_hit[19] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_3_OFFSET);
+ addr_hit[20] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_4_OFFSET);
+ addr_hit[21] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_5_OFFSET);
+ addr_hit[22] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_6_OFFSET);
+ addr_hit[23] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_7_OFFSET);
+ addr_hit[24] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
+ addr_hit[25] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET);
+ addr_hit[26] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET);
+ addr_hit[27] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET);
+ addr_hit[28] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET);
+ addr_hit[29] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET);
+ addr_hit[30] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET);
+ addr_hit[31] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET);
+ addr_hit[32] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET);
+ addr_hit[33] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_0_OFFSET);
+ addr_hit[34] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_1_OFFSET);
+ addr_hit[35] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_2_OFFSET);
+ addr_hit[36] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_3_OFFSET);
+ addr_hit[37] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_0_OFFSET);
+ addr_hit[38] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_1_OFFSET);
+ addr_hit[39] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_2_OFFSET);
+ addr_hit[40] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_3_OFFSET);
+ addr_hit[41] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET);
+ addr_hit[42] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET);
+ addr_hit[43] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET);
+ addr_hit[44] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET);
+ addr_hit[45] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET);
+ addr_hit[46] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET);
+ addr_hit[47] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET);
+ addr_hit[48] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET);
+ addr_hit[49] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_0_OFFSET);
+ addr_hit[50] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_1_OFFSET);
+ addr_hit[51] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_2_OFFSET);
+ addr_hit[52] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_3_OFFSET);
+ addr_hit[53] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_0_OFFSET);
+ addr_hit[54] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_1_OFFSET);
+ addr_hit[55] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_2_OFFSET);
+ addr_hit[56] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_3_OFFSET);
+ addr_hit[57] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET);
+ addr_hit[58] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET);
+ addr_hit[59] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
+ addr_hit[60] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
+ addr_hit[61] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
+ addr_hit[62] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
+ addr_hit[63] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
+ addr_hit[64] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -7867,6 +7898,7 @@
if (addr_hit[61] && reg_we && (FLASH_CTRL_PERMIT[61] != (FLASH_CTRL_PERMIT[61] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[62] && reg_we && (FLASH_CTRL_PERMIT[62] != (FLASH_CTRL_PERMIT[62] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[63] && reg_we && (FLASH_CTRL_PERMIT[63] != (FLASH_CTRL_PERMIT[63] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[64] && reg_we && (FLASH_CTRL_PERMIT[64] != (FLASH_CTRL_PERMIT[64] & reg_be))) wr_err = 1'b1 ;
end
assign intr_state_prog_empty_we = addr_hit[0] & reg_we & ~wr_err;
@@ -7955,661 +7987,664 @@
assign prog_type_en_repair_we = addr_hit[6] & reg_we & ~wr_err;
assign prog_type_en_repair_wd = reg_wdata[1];
- assign region_cfg_regwen_0_we = addr_hit[7] & reg_we & ~wr_err;
+ assign erase_suspend_we = addr_hit[7] & reg_we & ~wr_err;
+ assign erase_suspend_wd = reg_wdata[0];
+
+ assign region_cfg_regwen_0_we = addr_hit[8] & reg_we & ~wr_err;
assign region_cfg_regwen_0_wd = reg_wdata[0];
- assign region_cfg_regwen_1_we = addr_hit[8] & reg_we & ~wr_err;
+ assign region_cfg_regwen_1_we = addr_hit[9] & reg_we & ~wr_err;
assign region_cfg_regwen_1_wd = reg_wdata[0];
- assign region_cfg_regwen_2_we = addr_hit[9] & reg_we & ~wr_err;
+ assign region_cfg_regwen_2_we = addr_hit[10] & reg_we & ~wr_err;
assign region_cfg_regwen_2_wd = reg_wdata[0];
- assign region_cfg_regwen_3_we = addr_hit[10] & reg_we & ~wr_err;
+ assign region_cfg_regwen_3_we = addr_hit[11] & reg_we & ~wr_err;
assign region_cfg_regwen_3_wd = reg_wdata[0];
- assign region_cfg_regwen_4_we = addr_hit[11] & reg_we & ~wr_err;
+ assign region_cfg_regwen_4_we = addr_hit[12] & reg_we & ~wr_err;
assign region_cfg_regwen_4_wd = reg_wdata[0];
- assign region_cfg_regwen_5_we = addr_hit[12] & reg_we & ~wr_err;
+ assign region_cfg_regwen_5_we = addr_hit[13] & reg_we & ~wr_err;
assign region_cfg_regwen_5_wd = reg_wdata[0];
- assign region_cfg_regwen_6_we = addr_hit[13] & reg_we & ~wr_err;
+ assign region_cfg_regwen_6_we = addr_hit[14] & reg_we & ~wr_err;
assign region_cfg_regwen_6_wd = reg_wdata[0];
- assign region_cfg_regwen_7_we = addr_hit[14] & reg_we & ~wr_err;
+ assign region_cfg_regwen_7_we = addr_hit[15] & reg_we & ~wr_err;
assign region_cfg_regwen_7_wd = reg_wdata[0];
- assign mp_region_cfg_0_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_en_0_wd = reg_wdata[0];
- assign mp_region_cfg_0_rd_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_rd_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_rd_en_0_wd = reg_wdata[1];
- assign mp_region_cfg_0_prog_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_prog_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_prog_en_0_wd = reg_wdata[2];
- assign mp_region_cfg_0_erase_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_erase_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_erase_en_0_wd = reg_wdata[3];
- assign mp_region_cfg_0_scramble_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_scramble_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_scramble_en_0_wd = reg_wdata[4];
- assign mp_region_cfg_0_ecc_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_ecc_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_ecc_en_0_wd = reg_wdata[5];
- assign mp_region_cfg_0_he_en_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_he_en_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_he_en_0_wd = reg_wdata[6];
- assign mp_region_cfg_0_base_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_base_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_base_0_wd = reg_wdata[16:8];
- assign mp_region_cfg_0_size_0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_size_0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_0_size_0_wd = reg_wdata[29:20];
- assign mp_region_cfg_1_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_en_1_wd = reg_wdata[0];
- assign mp_region_cfg_1_rd_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_rd_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_rd_en_1_wd = reg_wdata[1];
- assign mp_region_cfg_1_prog_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_prog_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_prog_en_1_wd = reg_wdata[2];
- assign mp_region_cfg_1_erase_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_erase_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_erase_en_1_wd = reg_wdata[3];
- assign mp_region_cfg_1_scramble_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_scramble_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_scramble_en_1_wd = reg_wdata[4];
- assign mp_region_cfg_1_ecc_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_ecc_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_ecc_en_1_wd = reg_wdata[5];
- assign mp_region_cfg_1_he_en_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_he_en_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_he_en_1_wd = reg_wdata[6];
- assign mp_region_cfg_1_base_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_base_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_base_1_wd = reg_wdata[16:8];
- assign mp_region_cfg_1_size_1_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_size_1_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_1_size_1_wd = reg_wdata[29:20];
- assign mp_region_cfg_2_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_en_2_wd = reg_wdata[0];
- assign mp_region_cfg_2_rd_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_rd_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_rd_en_2_wd = reg_wdata[1];
- assign mp_region_cfg_2_prog_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_prog_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_prog_en_2_wd = reg_wdata[2];
- assign mp_region_cfg_2_erase_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_erase_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_erase_en_2_wd = reg_wdata[3];
- assign mp_region_cfg_2_scramble_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_scramble_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_scramble_en_2_wd = reg_wdata[4];
- assign mp_region_cfg_2_ecc_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_ecc_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_ecc_en_2_wd = reg_wdata[5];
- assign mp_region_cfg_2_he_en_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_he_en_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_he_en_2_wd = reg_wdata[6];
- assign mp_region_cfg_2_base_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_base_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_base_2_wd = reg_wdata[16:8];
- assign mp_region_cfg_2_size_2_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_size_2_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_2_size_2_wd = reg_wdata[29:20];
- assign mp_region_cfg_3_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_en_3_wd = reg_wdata[0];
- assign mp_region_cfg_3_rd_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_rd_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_rd_en_3_wd = reg_wdata[1];
- assign mp_region_cfg_3_prog_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_prog_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_prog_en_3_wd = reg_wdata[2];
- assign mp_region_cfg_3_erase_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_erase_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_erase_en_3_wd = reg_wdata[3];
- assign mp_region_cfg_3_scramble_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_scramble_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_scramble_en_3_wd = reg_wdata[4];
- assign mp_region_cfg_3_ecc_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_ecc_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_ecc_en_3_wd = reg_wdata[5];
- assign mp_region_cfg_3_he_en_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_he_en_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_he_en_3_wd = reg_wdata[6];
- assign mp_region_cfg_3_base_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_base_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_base_3_wd = reg_wdata[16:8];
- assign mp_region_cfg_3_size_3_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_size_3_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_3_size_3_wd = reg_wdata[29:20];
- assign mp_region_cfg_4_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_en_4_wd = reg_wdata[0];
- assign mp_region_cfg_4_rd_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_rd_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_rd_en_4_wd = reg_wdata[1];
- assign mp_region_cfg_4_prog_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_prog_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_prog_en_4_wd = reg_wdata[2];
- assign mp_region_cfg_4_erase_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_erase_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_erase_en_4_wd = reg_wdata[3];
- assign mp_region_cfg_4_scramble_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_scramble_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_scramble_en_4_wd = reg_wdata[4];
- assign mp_region_cfg_4_ecc_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_ecc_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_ecc_en_4_wd = reg_wdata[5];
- assign mp_region_cfg_4_he_en_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_he_en_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_he_en_4_wd = reg_wdata[6];
- assign mp_region_cfg_4_base_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_base_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_base_4_wd = reg_wdata[16:8];
- assign mp_region_cfg_4_size_4_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_size_4_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_4_size_4_wd = reg_wdata[29:20];
- assign mp_region_cfg_5_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_en_5_wd = reg_wdata[0];
- assign mp_region_cfg_5_rd_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_rd_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_rd_en_5_wd = reg_wdata[1];
- assign mp_region_cfg_5_prog_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_prog_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_prog_en_5_wd = reg_wdata[2];
- assign mp_region_cfg_5_erase_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_erase_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_erase_en_5_wd = reg_wdata[3];
- assign mp_region_cfg_5_scramble_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_scramble_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_scramble_en_5_wd = reg_wdata[4];
- assign mp_region_cfg_5_ecc_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_ecc_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_ecc_en_5_wd = reg_wdata[5];
- assign mp_region_cfg_5_he_en_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_he_en_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_he_en_5_wd = reg_wdata[6];
- assign mp_region_cfg_5_base_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_base_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_base_5_wd = reg_wdata[16:8];
- assign mp_region_cfg_5_size_5_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_size_5_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_5_size_5_wd = reg_wdata[29:20];
- assign mp_region_cfg_6_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_en_6_wd = reg_wdata[0];
- assign mp_region_cfg_6_rd_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_rd_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_rd_en_6_wd = reg_wdata[1];
- assign mp_region_cfg_6_prog_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_prog_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_prog_en_6_wd = reg_wdata[2];
- assign mp_region_cfg_6_erase_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_erase_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_erase_en_6_wd = reg_wdata[3];
- assign mp_region_cfg_6_scramble_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_scramble_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_scramble_en_6_wd = reg_wdata[4];
- assign mp_region_cfg_6_ecc_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_ecc_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_ecc_en_6_wd = reg_wdata[5];
- assign mp_region_cfg_6_he_en_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_he_en_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_he_en_6_wd = reg_wdata[6];
- assign mp_region_cfg_6_base_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_base_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_base_6_wd = reg_wdata[16:8];
- assign mp_region_cfg_6_size_6_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_size_6_we = addr_hit[22] & reg_we & ~wr_err;
assign mp_region_cfg_6_size_6_wd = reg_wdata[29:20];
- assign mp_region_cfg_7_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_en_7_wd = reg_wdata[0];
- assign mp_region_cfg_7_rd_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_rd_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_rd_en_7_wd = reg_wdata[1];
- assign mp_region_cfg_7_prog_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_prog_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_prog_en_7_wd = reg_wdata[2];
- assign mp_region_cfg_7_erase_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_erase_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_erase_en_7_wd = reg_wdata[3];
- assign mp_region_cfg_7_scramble_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_scramble_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_scramble_en_7_wd = reg_wdata[4];
- assign mp_region_cfg_7_ecc_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_ecc_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_ecc_en_7_wd = reg_wdata[5];
- assign mp_region_cfg_7_he_en_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_he_en_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_he_en_7_wd = reg_wdata[6];
- assign mp_region_cfg_7_base_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_base_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_base_7_wd = reg_wdata[16:8];
- assign mp_region_cfg_7_size_7_we = addr_hit[22] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_size_7_we = addr_hit[23] & reg_we & ~wr_err;
assign mp_region_cfg_7_size_7_wd = reg_wdata[29:20];
- assign default_region_rd_en_we = addr_hit[23] & reg_we & ~wr_err;
+ assign default_region_rd_en_we = addr_hit[24] & reg_we & ~wr_err;
assign default_region_rd_en_wd = reg_wdata[0];
- assign default_region_prog_en_we = addr_hit[23] & reg_we & ~wr_err;
+ assign default_region_prog_en_we = addr_hit[24] & reg_we & ~wr_err;
assign default_region_prog_en_wd = reg_wdata[1];
- assign default_region_erase_en_we = addr_hit[23] & reg_we & ~wr_err;
+ assign default_region_erase_en_we = addr_hit[24] & reg_we & ~wr_err;
assign default_region_erase_en_wd = reg_wdata[2];
- assign default_region_scramble_en_we = addr_hit[23] & reg_we & ~wr_err;
+ assign default_region_scramble_en_we = addr_hit[24] & reg_we & ~wr_err;
assign default_region_scramble_en_wd = reg_wdata[3];
- assign default_region_ecc_en_we = addr_hit[23] & reg_we & ~wr_err;
+ assign default_region_ecc_en_we = addr_hit[24] & reg_we & ~wr_err;
assign default_region_ecc_en_wd = reg_wdata[4];
- assign default_region_he_en_we = addr_hit[23] & reg_we & ~wr_err;
+ assign default_region_he_en_we = addr_hit[24] & reg_we & ~wr_err;
assign default_region_he_en_wd = reg_wdata[5];
- assign bank0_info0_regwen_0_we = addr_hit[24] & reg_we & ~wr_err;
+ assign bank0_info0_regwen_0_we = addr_hit[25] & reg_we & ~wr_err;
assign bank0_info0_regwen_0_wd = reg_wdata[0];
- assign bank0_info0_regwen_1_we = addr_hit[25] & reg_we & ~wr_err;
+ assign bank0_info0_regwen_1_we = addr_hit[26] & reg_we & ~wr_err;
assign bank0_info0_regwen_1_wd = reg_wdata[0];
- assign bank0_info0_regwen_2_we = addr_hit[26] & reg_we & ~wr_err;
+ assign bank0_info0_regwen_2_we = addr_hit[27] & reg_we & ~wr_err;
assign bank0_info0_regwen_2_wd = reg_wdata[0];
- assign bank0_info0_regwen_3_we = addr_hit[27] & reg_we & ~wr_err;
+ assign bank0_info0_regwen_3_we = addr_hit[28] & reg_we & ~wr_err;
assign bank0_info0_regwen_3_wd = reg_wdata[0];
- assign bank0_info0_page_cfg_0_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_en_0_wd = reg_wdata[0];
- assign bank0_info0_page_cfg_0_rd_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_rd_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_rd_en_0_wd = reg_wdata[1];
- assign bank0_info0_page_cfg_0_prog_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_prog_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_prog_en_0_wd = reg_wdata[2];
- assign bank0_info0_page_cfg_0_erase_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_erase_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_erase_en_0_wd = reg_wdata[3];
- assign bank0_info0_page_cfg_0_scramble_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_scramble_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
- assign bank0_info0_page_cfg_0_ecc_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_ecc_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
- assign bank0_info0_page_cfg_0_he_en_0_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_he_en_0_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_he_en_0_wd = reg_wdata[6];
- assign bank0_info0_page_cfg_1_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_en_1_wd = reg_wdata[0];
- assign bank0_info0_page_cfg_1_rd_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_rd_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_rd_en_1_wd = reg_wdata[1];
- assign bank0_info0_page_cfg_1_prog_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_prog_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_prog_en_1_wd = reg_wdata[2];
- assign bank0_info0_page_cfg_1_erase_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_erase_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_erase_en_1_wd = reg_wdata[3];
- assign bank0_info0_page_cfg_1_scramble_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_scramble_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
- assign bank0_info0_page_cfg_1_ecc_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_ecc_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
- assign bank0_info0_page_cfg_1_he_en_1_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_he_en_1_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_he_en_1_wd = reg_wdata[6];
- assign bank0_info0_page_cfg_2_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_en_2_wd = reg_wdata[0];
- assign bank0_info0_page_cfg_2_rd_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_rd_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_rd_en_2_wd = reg_wdata[1];
- assign bank0_info0_page_cfg_2_prog_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_prog_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_prog_en_2_wd = reg_wdata[2];
- assign bank0_info0_page_cfg_2_erase_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_erase_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_erase_en_2_wd = reg_wdata[3];
- assign bank0_info0_page_cfg_2_scramble_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_scramble_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
- assign bank0_info0_page_cfg_2_ecc_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_ecc_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
- assign bank0_info0_page_cfg_2_he_en_2_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_he_en_2_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_he_en_2_wd = reg_wdata[6];
- assign bank0_info0_page_cfg_3_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_en_3_wd = reg_wdata[0];
- assign bank0_info0_page_cfg_3_rd_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_rd_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_rd_en_3_wd = reg_wdata[1];
- assign bank0_info0_page_cfg_3_prog_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_prog_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_prog_en_3_wd = reg_wdata[2];
- assign bank0_info0_page_cfg_3_erase_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_erase_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_erase_en_3_wd = reg_wdata[3];
- assign bank0_info0_page_cfg_3_scramble_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_scramble_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
- assign bank0_info0_page_cfg_3_ecc_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_ecc_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
- assign bank0_info0_page_cfg_3_he_en_3_we = addr_hit[31] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_he_en_3_we = addr_hit[32] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_he_en_3_wd = reg_wdata[6];
- assign bank0_info1_regwen_0_we = addr_hit[32] & reg_we & ~wr_err;
+ assign bank0_info1_regwen_0_we = addr_hit[33] & reg_we & ~wr_err;
assign bank0_info1_regwen_0_wd = reg_wdata[0];
- assign bank0_info1_regwen_1_we = addr_hit[33] & reg_we & ~wr_err;
+ assign bank0_info1_regwen_1_we = addr_hit[34] & reg_we & ~wr_err;
assign bank0_info1_regwen_1_wd = reg_wdata[0];
- assign bank0_info1_regwen_2_we = addr_hit[34] & reg_we & ~wr_err;
+ assign bank0_info1_regwen_2_we = addr_hit[35] & reg_we & ~wr_err;
assign bank0_info1_regwen_2_wd = reg_wdata[0];
- assign bank0_info1_regwen_3_we = addr_hit[35] & reg_we & ~wr_err;
+ assign bank0_info1_regwen_3_we = addr_hit[36] & reg_we & ~wr_err;
assign bank0_info1_regwen_3_wd = reg_wdata[0];
- assign bank0_info1_page_cfg_0_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_en_0_wd = reg_wdata[0];
- assign bank0_info1_page_cfg_0_rd_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_rd_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_rd_en_0_wd = reg_wdata[1];
- assign bank0_info1_page_cfg_0_prog_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_prog_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_prog_en_0_wd = reg_wdata[2];
- assign bank0_info1_page_cfg_0_erase_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_erase_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_erase_en_0_wd = reg_wdata[3];
- assign bank0_info1_page_cfg_0_scramble_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_scramble_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
- assign bank0_info1_page_cfg_0_ecc_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_ecc_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
- assign bank0_info1_page_cfg_0_he_en_0_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_he_en_0_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_he_en_0_wd = reg_wdata[6];
- assign bank0_info1_page_cfg_1_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_en_1_wd = reg_wdata[0];
- assign bank0_info1_page_cfg_1_rd_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_rd_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_rd_en_1_wd = reg_wdata[1];
- assign bank0_info1_page_cfg_1_prog_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_prog_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_prog_en_1_wd = reg_wdata[2];
- assign bank0_info1_page_cfg_1_erase_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_erase_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_erase_en_1_wd = reg_wdata[3];
- assign bank0_info1_page_cfg_1_scramble_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_scramble_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
- assign bank0_info1_page_cfg_1_ecc_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_ecc_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
- assign bank0_info1_page_cfg_1_he_en_1_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_he_en_1_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_he_en_1_wd = reg_wdata[6];
- assign bank0_info1_page_cfg_2_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_en_2_wd = reg_wdata[0];
- assign bank0_info1_page_cfg_2_rd_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_rd_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_rd_en_2_wd = reg_wdata[1];
- assign bank0_info1_page_cfg_2_prog_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_prog_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_prog_en_2_wd = reg_wdata[2];
- assign bank0_info1_page_cfg_2_erase_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_erase_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_erase_en_2_wd = reg_wdata[3];
- assign bank0_info1_page_cfg_2_scramble_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_scramble_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
- assign bank0_info1_page_cfg_2_ecc_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_ecc_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
- assign bank0_info1_page_cfg_2_he_en_2_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_he_en_2_we = addr_hit[39] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_he_en_2_wd = reg_wdata[6];
- assign bank0_info1_page_cfg_3_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_en_3_wd = reg_wdata[0];
- assign bank0_info1_page_cfg_3_rd_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_rd_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_rd_en_3_wd = reg_wdata[1];
- assign bank0_info1_page_cfg_3_prog_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_prog_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_prog_en_3_wd = reg_wdata[2];
- assign bank0_info1_page_cfg_3_erase_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_erase_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_erase_en_3_wd = reg_wdata[3];
- assign bank0_info1_page_cfg_3_scramble_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_scramble_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
- assign bank0_info1_page_cfg_3_ecc_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_ecc_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
- assign bank0_info1_page_cfg_3_he_en_3_we = addr_hit[39] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_he_en_3_we = addr_hit[40] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_he_en_3_wd = reg_wdata[6];
- assign bank1_info0_regwen_0_we = addr_hit[40] & reg_we & ~wr_err;
+ assign bank1_info0_regwen_0_we = addr_hit[41] & reg_we & ~wr_err;
assign bank1_info0_regwen_0_wd = reg_wdata[0];
- assign bank1_info0_regwen_1_we = addr_hit[41] & reg_we & ~wr_err;
+ assign bank1_info0_regwen_1_we = addr_hit[42] & reg_we & ~wr_err;
assign bank1_info0_regwen_1_wd = reg_wdata[0];
- assign bank1_info0_regwen_2_we = addr_hit[42] & reg_we & ~wr_err;
+ assign bank1_info0_regwen_2_we = addr_hit[43] & reg_we & ~wr_err;
assign bank1_info0_regwen_2_wd = reg_wdata[0];
- assign bank1_info0_regwen_3_we = addr_hit[43] & reg_we & ~wr_err;
+ assign bank1_info0_regwen_3_we = addr_hit[44] & reg_we & ~wr_err;
assign bank1_info0_regwen_3_wd = reg_wdata[0];
- assign bank1_info0_page_cfg_0_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_en_0_wd = reg_wdata[0];
- assign bank1_info0_page_cfg_0_rd_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_rd_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_rd_en_0_wd = reg_wdata[1];
- assign bank1_info0_page_cfg_0_prog_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_prog_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_prog_en_0_wd = reg_wdata[2];
- assign bank1_info0_page_cfg_0_erase_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_erase_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_erase_en_0_wd = reg_wdata[3];
- assign bank1_info0_page_cfg_0_scramble_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_scramble_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
- assign bank1_info0_page_cfg_0_ecc_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_ecc_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
- assign bank1_info0_page_cfg_0_he_en_0_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_he_en_0_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_he_en_0_wd = reg_wdata[6];
- assign bank1_info0_page_cfg_1_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_en_1_wd = reg_wdata[0];
- assign bank1_info0_page_cfg_1_rd_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_rd_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_rd_en_1_wd = reg_wdata[1];
- assign bank1_info0_page_cfg_1_prog_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_prog_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_prog_en_1_wd = reg_wdata[2];
- assign bank1_info0_page_cfg_1_erase_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_erase_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_erase_en_1_wd = reg_wdata[3];
- assign bank1_info0_page_cfg_1_scramble_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_scramble_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
- assign bank1_info0_page_cfg_1_ecc_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_ecc_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
- assign bank1_info0_page_cfg_1_he_en_1_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_he_en_1_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_he_en_1_wd = reg_wdata[6];
- assign bank1_info0_page_cfg_2_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_en_2_wd = reg_wdata[0];
- assign bank1_info0_page_cfg_2_rd_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_rd_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_rd_en_2_wd = reg_wdata[1];
- assign bank1_info0_page_cfg_2_prog_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_prog_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_prog_en_2_wd = reg_wdata[2];
- assign bank1_info0_page_cfg_2_erase_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_erase_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_erase_en_2_wd = reg_wdata[3];
- assign bank1_info0_page_cfg_2_scramble_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_scramble_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
- assign bank1_info0_page_cfg_2_ecc_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_ecc_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
- assign bank1_info0_page_cfg_2_he_en_2_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_he_en_2_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_he_en_2_wd = reg_wdata[6];
- assign bank1_info0_page_cfg_3_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_en_3_wd = reg_wdata[0];
- assign bank1_info0_page_cfg_3_rd_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_rd_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_rd_en_3_wd = reg_wdata[1];
- assign bank1_info0_page_cfg_3_prog_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_prog_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_prog_en_3_wd = reg_wdata[2];
- assign bank1_info0_page_cfg_3_erase_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_erase_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_erase_en_3_wd = reg_wdata[3];
- assign bank1_info0_page_cfg_3_scramble_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_scramble_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
- assign bank1_info0_page_cfg_3_ecc_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_ecc_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
- assign bank1_info0_page_cfg_3_he_en_3_we = addr_hit[47] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_he_en_3_we = addr_hit[48] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_he_en_3_wd = reg_wdata[6];
- assign bank1_info1_regwen_0_we = addr_hit[48] & reg_we & ~wr_err;
+ assign bank1_info1_regwen_0_we = addr_hit[49] & reg_we & ~wr_err;
assign bank1_info1_regwen_0_wd = reg_wdata[0];
- assign bank1_info1_regwen_1_we = addr_hit[49] & reg_we & ~wr_err;
+ assign bank1_info1_regwen_1_we = addr_hit[50] & reg_we & ~wr_err;
assign bank1_info1_regwen_1_wd = reg_wdata[0];
- assign bank1_info1_regwen_2_we = addr_hit[50] & reg_we & ~wr_err;
+ assign bank1_info1_regwen_2_we = addr_hit[51] & reg_we & ~wr_err;
assign bank1_info1_regwen_2_wd = reg_wdata[0];
- assign bank1_info1_regwen_3_we = addr_hit[51] & reg_we & ~wr_err;
+ assign bank1_info1_regwen_3_we = addr_hit[52] & reg_we & ~wr_err;
assign bank1_info1_regwen_3_wd = reg_wdata[0];
- assign bank1_info1_page_cfg_0_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_en_0_wd = reg_wdata[0];
- assign bank1_info1_page_cfg_0_rd_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_rd_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_rd_en_0_wd = reg_wdata[1];
- assign bank1_info1_page_cfg_0_prog_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_prog_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_prog_en_0_wd = reg_wdata[2];
- assign bank1_info1_page_cfg_0_erase_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_erase_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_erase_en_0_wd = reg_wdata[3];
- assign bank1_info1_page_cfg_0_scramble_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_scramble_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_scramble_en_0_wd = reg_wdata[4];
- assign bank1_info1_page_cfg_0_ecc_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_ecc_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
- assign bank1_info1_page_cfg_0_he_en_0_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_he_en_0_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_he_en_0_wd = reg_wdata[6];
- assign bank1_info1_page_cfg_1_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_en_1_wd = reg_wdata[0];
- assign bank1_info1_page_cfg_1_rd_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_rd_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_rd_en_1_wd = reg_wdata[1];
- assign bank1_info1_page_cfg_1_prog_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_prog_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_prog_en_1_wd = reg_wdata[2];
- assign bank1_info1_page_cfg_1_erase_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_erase_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_erase_en_1_wd = reg_wdata[3];
- assign bank1_info1_page_cfg_1_scramble_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_scramble_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_scramble_en_1_wd = reg_wdata[4];
- assign bank1_info1_page_cfg_1_ecc_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_ecc_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
- assign bank1_info1_page_cfg_1_he_en_1_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_he_en_1_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_he_en_1_wd = reg_wdata[6];
- assign bank1_info1_page_cfg_2_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_en_2_wd = reg_wdata[0];
- assign bank1_info1_page_cfg_2_rd_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_rd_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_rd_en_2_wd = reg_wdata[1];
- assign bank1_info1_page_cfg_2_prog_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_prog_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_prog_en_2_wd = reg_wdata[2];
- assign bank1_info1_page_cfg_2_erase_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_erase_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_erase_en_2_wd = reg_wdata[3];
- assign bank1_info1_page_cfg_2_scramble_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_scramble_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_scramble_en_2_wd = reg_wdata[4];
- assign bank1_info1_page_cfg_2_ecc_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_ecc_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
- assign bank1_info1_page_cfg_2_he_en_2_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_he_en_2_we = addr_hit[55] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_he_en_2_wd = reg_wdata[6];
- assign bank1_info1_page_cfg_3_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_en_3_wd = reg_wdata[0];
- assign bank1_info1_page_cfg_3_rd_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_rd_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_rd_en_3_wd = reg_wdata[1];
- assign bank1_info1_page_cfg_3_prog_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_prog_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_prog_en_3_wd = reg_wdata[2];
- assign bank1_info1_page_cfg_3_erase_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_erase_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_erase_en_3_wd = reg_wdata[3];
- assign bank1_info1_page_cfg_3_scramble_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_scramble_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_scramble_en_3_wd = reg_wdata[4];
- assign bank1_info1_page_cfg_3_ecc_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_ecc_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
- assign bank1_info1_page_cfg_3_he_en_3_we = addr_hit[55] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_he_en_3_we = addr_hit[56] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_he_en_3_wd = reg_wdata[6];
- assign bank_cfg_regwen_we = addr_hit[56] & reg_we & ~wr_err;
+ assign bank_cfg_regwen_we = addr_hit[57] & reg_we & ~wr_err;
assign bank_cfg_regwen_wd = reg_wdata[0];
- assign mp_bank_cfg_erase_en_0_we = addr_hit[57] & reg_we & ~wr_err;
+ assign mp_bank_cfg_erase_en_0_we = addr_hit[58] & reg_we & ~wr_err;
assign mp_bank_cfg_erase_en_0_wd = reg_wdata[0];
- assign mp_bank_cfg_erase_en_1_we = addr_hit[57] & reg_we & ~wr_err;
+ assign mp_bank_cfg_erase_en_1_we = addr_hit[58] & reg_we & ~wr_err;
assign mp_bank_cfg_erase_en_1_wd = reg_wdata[1];
- assign op_status_done_we = addr_hit[58] & reg_we & ~wr_err;
+ assign op_status_done_we = addr_hit[59] & reg_we & ~wr_err;
assign op_status_done_wd = reg_wdata[0];
- assign op_status_err_we = addr_hit[58] & reg_we & ~wr_err;
+ assign op_status_err_we = addr_hit[59] & reg_we & ~wr_err;
assign op_status_err_wd = reg_wdata[1];
@@ -8621,16 +8656,16 @@
- assign scratch_we = addr_hit[61] & reg_we & ~wr_err;
+ assign scratch_we = addr_hit[62] & reg_we & ~wr_err;
assign scratch_wd = reg_wdata[31:0];
- assign fifo_lvl_prog_we = addr_hit[62] & reg_we & ~wr_err;
+ assign fifo_lvl_prog_we = addr_hit[63] & reg_we & ~wr_err;
assign fifo_lvl_prog_wd = reg_wdata[4:0];
- assign fifo_lvl_rd_we = addr_hit[62] & reg_we & ~wr_err;
+ assign fifo_lvl_rd_we = addr_hit[63] & reg_we & ~wr_err;
assign fifo_lvl_rd_wd = reg_wdata[12:8];
- assign fifo_rst_we = addr_hit[63] & reg_we & ~wr_err;
+ assign fifo_rst_we = addr_hit[64] & reg_we & ~wr_err;
assign fifo_rst_wd = reg_wdata[0];
// Read data return
@@ -8688,38 +8723,42 @@
end
addr_hit[7]: begin
- reg_rdata_next[0] = region_cfg_regwen_0_qs;
+ reg_rdata_next[0] = erase_suspend_qs;
end
addr_hit[8]: begin
- reg_rdata_next[0] = region_cfg_regwen_1_qs;
+ reg_rdata_next[0] = region_cfg_regwen_0_qs;
end
addr_hit[9]: begin
- reg_rdata_next[0] = region_cfg_regwen_2_qs;
+ reg_rdata_next[0] = region_cfg_regwen_1_qs;
end
addr_hit[10]: begin
- reg_rdata_next[0] = region_cfg_regwen_3_qs;
+ reg_rdata_next[0] = region_cfg_regwen_2_qs;
end
addr_hit[11]: begin
- reg_rdata_next[0] = region_cfg_regwen_4_qs;
+ reg_rdata_next[0] = region_cfg_regwen_3_qs;
end
addr_hit[12]: begin
- reg_rdata_next[0] = region_cfg_regwen_5_qs;
+ reg_rdata_next[0] = region_cfg_regwen_4_qs;
end
addr_hit[13]: begin
- reg_rdata_next[0] = region_cfg_regwen_6_qs;
+ reg_rdata_next[0] = region_cfg_regwen_5_qs;
end
addr_hit[14]: begin
- reg_rdata_next[0] = region_cfg_regwen_7_qs;
+ reg_rdata_next[0] = region_cfg_regwen_6_qs;
end
addr_hit[15]: begin
+ reg_rdata_next[0] = region_cfg_regwen_7_qs;
+ end
+
+ addr_hit[16]: begin
reg_rdata_next[0] = mp_region_cfg_0_en_0_qs;
reg_rdata_next[1] = mp_region_cfg_0_rd_en_0_qs;
reg_rdata_next[2] = mp_region_cfg_0_prog_en_0_qs;
@@ -8731,7 +8770,7 @@
reg_rdata_next[29:20] = mp_region_cfg_0_size_0_qs;
end
- addr_hit[16]: begin
+ addr_hit[17]: begin
reg_rdata_next[0] = mp_region_cfg_1_en_1_qs;
reg_rdata_next[1] = mp_region_cfg_1_rd_en_1_qs;
reg_rdata_next[2] = mp_region_cfg_1_prog_en_1_qs;
@@ -8743,7 +8782,7 @@
reg_rdata_next[29:20] = mp_region_cfg_1_size_1_qs;
end
- addr_hit[17]: begin
+ addr_hit[18]: begin
reg_rdata_next[0] = mp_region_cfg_2_en_2_qs;
reg_rdata_next[1] = mp_region_cfg_2_rd_en_2_qs;
reg_rdata_next[2] = mp_region_cfg_2_prog_en_2_qs;
@@ -8755,7 +8794,7 @@
reg_rdata_next[29:20] = mp_region_cfg_2_size_2_qs;
end
- addr_hit[18]: begin
+ addr_hit[19]: begin
reg_rdata_next[0] = mp_region_cfg_3_en_3_qs;
reg_rdata_next[1] = mp_region_cfg_3_rd_en_3_qs;
reg_rdata_next[2] = mp_region_cfg_3_prog_en_3_qs;
@@ -8767,7 +8806,7 @@
reg_rdata_next[29:20] = mp_region_cfg_3_size_3_qs;
end
- addr_hit[19]: begin
+ addr_hit[20]: begin
reg_rdata_next[0] = mp_region_cfg_4_en_4_qs;
reg_rdata_next[1] = mp_region_cfg_4_rd_en_4_qs;
reg_rdata_next[2] = mp_region_cfg_4_prog_en_4_qs;
@@ -8779,7 +8818,7 @@
reg_rdata_next[29:20] = mp_region_cfg_4_size_4_qs;
end
- addr_hit[20]: begin
+ addr_hit[21]: begin
reg_rdata_next[0] = mp_region_cfg_5_en_5_qs;
reg_rdata_next[1] = mp_region_cfg_5_rd_en_5_qs;
reg_rdata_next[2] = mp_region_cfg_5_prog_en_5_qs;
@@ -8791,7 +8830,7 @@
reg_rdata_next[29:20] = mp_region_cfg_5_size_5_qs;
end
- addr_hit[21]: begin
+ addr_hit[22]: begin
reg_rdata_next[0] = mp_region_cfg_6_en_6_qs;
reg_rdata_next[1] = mp_region_cfg_6_rd_en_6_qs;
reg_rdata_next[2] = mp_region_cfg_6_prog_en_6_qs;
@@ -8803,7 +8842,7 @@
reg_rdata_next[29:20] = mp_region_cfg_6_size_6_qs;
end
- addr_hit[22]: begin
+ addr_hit[23]: begin
reg_rdata_next[0] = mp_region_cfg_7_en_7_qs;
reg_rdata_next[1] = mp_region_cfg_7_rd_en_7_qs;
reg_rdata_next[2] = mp_region_cfg_7_prog_en_7_qs;
@@ -8815,7 +8854,7 @@
reg_rdata_next[29:20] = mp_region_cfg_7_size_7_qs;
end
- addr_hit[23]: begin
+ addr_hit[24]: begin
reg_rdata_next[0] = default_region_rd_en_qs;
reg_rdata_next[1] = default_region_prog_en_qs;
reg_rdata_next[2] = default_region_erase_en_qs;
@@ -8824,23 +8863,23 @@
reg_rdata_next[5] = default_region_he_en_qs;
end
- addr_hit[24]: begin
+ addr_hit[25]: begin
reg_rdata_next[0] = bank0_info0_regwen_0_qs;
end
- addr_hit[25]: begin
+ addr_hit[26]: begin
reg_rdata_next[0] = bank0_info0_regwen_1_qs;
end
- addr_hit[26]: begin
+ addr_hit[27]: begin
reg_rdata_next[0] = bank0_info0_regwen_2_qs;
end
- addr_hit[27]: begin
+ addr_hit[28]: begin
reg_rdata_next[0] = bank0_info0_regwen_3_qs;
end
- addr_hit[28]: begin
+ addr_hit[29]: begin
reg_rdata_next[0] = bank0_info0_page_cfg_0_en_0_qs;
reg_rdata_next[1] = bank0_info0_page_cfg_0_rd_en_0_qs;
reg_rdata_next[2] = bank0_info0_page_cfg_0_prog_en_0_qs;
@@ -8850,7 +8889,7 @@
reg_rdata_next[6] = bank0_info0_page_cfg_0_he_en_0_qs;
end
- addr_hit[29]: begin
+ addr_hit[30]: begin
reg_rdata_next[0] = bank0_info0_page_cfg_1_en_1_qs;
reg_rdata_next[1] = bank0_info0_page_cfg_1_rd_en_1_qs;
reg_rdata_next[2] = bank0_info0_page_cfg_1_prog_en_1_qs;
@@ -8860,7 +8899,7 @@
reg_rdata_next[6] = bank0_info0_page_cfg_1_he_en_1_qs;
end
- addr_hit[30]: begin
+ addr_hit[31]: begin
reg_rdata_next[0] = bank0_info0_page_cfg_2_en_2_qs;
reg_rdata_next[1] = bank0_info0_page_cfg_2_rd_en_2_qs;
reg_rdata_next[2] = bank0_info0_page_cfg_2_prog_en_2_qs;
@@ -8870,7 +8909,7 @@
reg_rdata_next[6] = bank0_info0_page_cfg_2_he_en_2_qs;
end
- addr_hit[31]: begin
+ addr_hit[32]: begin
reg_rdata_next[0] = bank0_info0_page_cfg_3_en_3_qs;
reg_rdata_next[1] = bank0_info0_page_cfg_3_rd_en_3_qs;
reg_rdata_next[2] = bank0_info0_page_cfg_3_prog_en_3_qs;
@@ -8880,23 +8919,23 @@
reg_rdata_next[6] = bank0_info0_page_cfg_3_he_en_3_qs;
end
- addr_hit[32]: begin
+ addr_hit[33]: begin
reg_rdata_next[0] = bank0_info1_regwen_0_qs;
end
- addr_hit[33]: begin
+ addr_hit[34]: begin
reg_rdata_next[0] = bank0_info1_regwen_1_qs;
end
- addr_hit[34]: begin
+ addr_hit[35]: begin
reg_rdata_next[0] = bank0_info1_regwen_2_qs;
end
- addr_hit[35]: begin
+ addr_hit[36]: begin
reg_rdata_next[0] = bank0_info1_regwen_3_qs;
end
- addr_hit[36]: begin
+ addr_hit[37]: begin
reg_rdata_next[0] = bank0_info1_page_cfg_0_en_0_qs;
reg_rdata_next[1] = bank0_info1_page_cfg_0_rd_en_0_qs;
reg_rdata_next[2] = bank0_info1_page_cfg_0_prog_en_0_qs;
@@ -8906,7 +8945,7 @@
reg_rdata_next[6] = bank0_info1_page_cfg_0_he_en_0_qs;
end
- addr_hit[37]: begin
+ addr_hit[38]: begin
reg_rdata_next[0] = bank0_info1_page_cfg_1_en_1_qs;
reg_rdata_next[1] = bank0_info1_page_cfg_1_rd_en_1_qs;
reg_rdata_next[2] = bank0_info1_page_cfg_1_prog_en_1_qs;
@@ -8916,7 +8955,7 @@
reg_rdata_next[6] = bank0_info1_page_cfg_1_he_en_1_qs;
end
- addr_hit[38]: begin
+ addr_hit[39]: begin
reg_rdata_next[0] = bank0_info1_page_cfg_2_en_2_qs;
reg_rdata_next[1] = bank0_info1_page_cfg_2_rd_en_2_qs;
reg_rdata_next[2] = bank0_info1_page_cfg_2_prog_en_2_qs;
@@ -8926,7 +8965,7 @@
reg_rdata_next[6] = bank0_info1_page_cfg_2_he_en_2_qs;
end
- addr_hit[39]: begin
+ addr_hit[40]: begin
reg_rdata_next[0] = bank0_info1_page_cfg_3_en_3_qs;
reg_rdata_next[1] = bank0_info1_page_cfg_3_rd_en_3_qs;
reg_rdata_next[2] = bank0_info1_page_cfg_3_prog_en_3_qs;
@@ -8936,23 +8975,23 @@
reg_rdata_next[6] = bank0_info1_page_cfg_3_he_en_3_qs;
end
- addr_hit[40]: begin
+ addr_hit[41]: begin
reg_rdata_next[0] = bank1_info0_regwen_0_qs;
end
- addr_hit[41]: begin
+ addr_hit[42]: begin
reg_rdata_next[0] = bank1_info0_regwen_1_qs;
end
- addr_hit[42]: begin
+ addr_hit[43]: begin
reg_rdata_next[0] = bank1_info0_regwen_2_qs;
end
- addr_hit[43]: begin
+ addr_hit[44]: begin
reg_rdata_next[0] = bank1_info0_regwen_3_qs;
end
- addr_hit[44]: begin
+ addr_hit[45]: begin
reg_rdata_next[0] = bank1_info0_page_cfg_0_en_0_qs;
reg_rdata_next[1] = bank1_info0_page_cfg_0_rd_en_0_qs;
reg_rdata_next[2] = bank1_info0_page_cfg_0_prog_en_0_qs;
@@ -8962,7 +9001,7 @@
reg_rdata_next[6] = bank1_info0_page_cfg_0_he_en_0_qs;
end
- addr_hit[45]: begin
+ addr_hit[46]: begin
reg_rdata_next[0] = bank1_info0_page_cfg_1_en_1_qs;
reg_rdata_next[1] = bank1_info0_page_cfg_1_rd_en_1_qs;
reg_rdata_next[2] = bank1_info0_page_cfg_1_prog_en_1_qs;
@@ -8972,7 +9011,7 @@
reg_rdata_next[6] = bank1_info0_page_cfg_1_he_en_1_qs;
end
- addr_hit[46]: begin
+ addr_hit[47]: begin
reg_rdata_next[0] = bank1_info0_page_cfg_2_en_2_qs;
reg_rdata_next[1] = bank1_info0_page_cfg_2_rd_en_2_qs;
reg_rdata_next[2] = bank1_info0_page_cfg_2_prog_en_2_qs;
@@ -8982,7 +9021,7 @@
reg_rdata_next[6] = bank1_info0_page_cfg_2_he_en_2_qs;
end
- addr_hit[47]: begin
+ addr_hit[48]: begin
reg_rdata_next[0] = bank1_info0_page_cfg_3_en_3_qs;
reg_rdata_next[1] = bank1_info0_page_cfg_3_rd_en_3_qs;
reg_rdata_next[2] = bank1_info0_page_cfg_3_prog_en_3_qs;
@@ -8992,23 +9031,23 @@
reg_rdata_next[6] = bank1_info0_page_cfg_3_he_en_3_qs;
end
- addr_hit[48]: begin
+ addr_hit[49]: begin
reg_rdata_next[0] = bank1_info1_regwen_0_qs;
end
- addr_hit[49]: begin
+ addr_hit[50]: begin
reg_rdata_next[0] = bank1_info1_regwen_1_qs;
end
- addr_hit[50]: begin
+ addr_hit[51]: begin
reg_rdata_next[0] = bank1_info1_regwen_2_qs;
end
- addr_hit[51]: begin
+ addr_hit[52]: begin
reg_rdata_next[0] = bank1_info1_regwen_3_qs;
end
- addr_hit[52]: begin
+ addr_hit[53]: begin
reg_rdata_next[0] = bank1_info1_page_cfg_0_en_0_qs;
reg_rdata_next[1] = bank1_info1_page_cfg_0_rd_en_0_qs;
reg_rdata_next[2] = bank1_info1_page_cfg_0_prog_en_0_qs;
@@ -9018,7 +9057,7 @@
reg_rdata_next[6] = bank1_info1_page_cfg_0_he_en_0_qs;
end
- addr_hit[53]: begin
+ addr_hit[54]: begin
reg_rdata_next[0] = bank1_info1_page_cfg_1_en_1_qs;
reg_rdata_next[1] = bank1_info1_page_cfg_1_rd_en_1_qs;
reg_rdata_next[2] = bank1_info1_page_cfg_1_prog_en_1_qs;
@@ -9028,7 +9067,7 @@
reg_rdata_next[6] = bank1_info1_page_cfg_1_he_en_1_qs;
end
- addr_hit[54]: begin
+ addr_hit[55]: begin
reg_rdata_next[0] = bank1_info1_page_cfg_2_en_2_qs;
reg_rdata_next[1] = bank1_info1_page_cfg_2_rd_en_2_qs;
reg_rdata_next[2] = bank1_info1_page_cfg_2_prog_en_2_qs;
@@ -9038,7 +9077,7 @@
reg_rdata_next[6] = bank1_info1_page_cfg_2_he_en_2_qs;
end
- addr_hit[55]: begin
+ addr_hit[56]: begin
reg_rdata_next[0] = bank1_info1_page_cfg_3_en_3_qs;
reg_rdata_next[1] = bank1_info1_page_cfg_3_rd_en_3_qs;
reg_rdata_next[2] = bank1_info1_page_cfg_3_prog_en_3_qs;
@@ -9048,21 +9087,21 @@
reg_rdata_next[6] = bank1_info1_page_cfg_3_he_en_3_qs;
end
- addr_hit[56]: begin
+ addr_hit[57]: begin
reg_rdata_next[0] = bank_cfg_regwen_qs;
end
- addr_hit[57]: begin
+ addr_hit[58]: begin
reg_rdata_next[0] = mp_bank_cfg_erase_en_0_qs;
reg_rdata_next[1] = mp_bank_cfg_erase_en_1_qs;
end
- addr_hit[58]: begin
+ addr_hit[59]: begin
reg_rdata_next[0] = op_status_done_qs;
reg_rdata_next[1] = op_status_err_qs;
end
- addr_hit[59]: begin
+ addr_hit[60]: begin
reg_rdata_next[0] = status_rd_full_qs;
reg_rdata_next[1] = status_rd_empty_qs;
reg_rdata_next[2] = status_prog_full_qs;
@@ -9071,22 +9110,22 @@
reg_rdata_next[16:8] = status_error_addr_qs;
end
- addr_hit[60]: begin
+ addr_hit[61]: begin
reg_rdata_next[0] = phy_status_init_wip_qs;
reg_rdata_next[1] = phy_status_prog_normal_avail_qs;
reg_rdata_next[2] = phy_status_prog_repair_avail_qs;
end
- addr_hit[61]: begin
+ addr_hit[62]: begin
reg_rdata_next[31:0] = scratch_qs;
end
- addr_hit[62]: begin
+ addr_hit[63]: begin
reg_rdata_next[4:0] = fifo_lvl_prog_qs;
reg_rdata_next[12:8] = fifo_lvl_rd_qs;
end
- addr_hit[63]: begin
+ addr_hit[64]: begin
reg_rdata_next[0] = fifo_rst_qs;
end
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 2e53eaf..d4e1fa0 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -1090,7 +1090,9 @@
flash_ctrl #(
.RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
- .RndCnstDataKey(RndCnstFlashCtrlDataKey)
+ .RndCnstDataKey(RndCnstFlashCtrlDataKey),
+ .RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstFlashCtrlLfsrPerm)
) u_flash_ctrl (
// Interrupt
@@ -1113,7 +1115,8 @@
.lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en),
.lc_i(flash_ctrl_pkg::LC_FLASH_REQ_DEFAULT),
.lc_o(),
- .edn_i(flash_ctrl_pkg::EDN_ENTROPY_DEFAULT),
+ .edn_o(),
+ .edn_i(edn_pkg::EDN_RSP_DEFAULT),
.pwrmgr_i(pwrmgr_pwr_flash_req),
.pwrmgr_o(pwrmgr_pwr_flash_rsp),
.keymgr_o(flash_ctrl_keymgr),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv
index 5995e4a..cc1e23b 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv
@@ -83,6 +83,16 @@
128'hFABD19450B238D4C2D73930D4CAC3785
};
+ // Compile-time random bits for initial LFSR seed
+ parameter flash_ctrl_pkg::lfsr_seed_t RndCnstFlashCtrlLfsrSeed = {
+ 32'hD89F9DFC
+ };
+
+ // Compile-time random permutation for LFSR output
+ parameter flash_ctrl_pkg::lfsr_perm_t RndCnstFlashCtrlLfsrPerm = {
+ 160'h26FF203D990D87C5E8A98BAFEC7506855AA99C54
+ };
+
////////////////////////////////////////////
// keymgr
////////////////////////////////////////////
